Aarch32: Secure PMU counter leak tests
This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 1d5cc11..4e9c03b 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -152,6 +152,8 @@
#define ID_AA64DFR0_DEBUG_SHIFT U(0)
#define ID_AA64DFR0_DEBUG_LENGTH U(4)
#define ID_AA64DFR0_DEBUG_MASK ULL(0xf)
+#define ID_AA64DFR0_DEBUG_BITS (ID_AA64DFR0_DEBUG_MASK << \
+ ID_AA64DFR0_DEBUG_SHIFT)
#define ID_AA64DFR0_V8_DEBUG_ARCH_SUPPORTED U(6)
#define ID_AA64DFR0_V8_DEBUG_ARCH_VHE_SUPPORTED U(7)
#define ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED U(8)