Aarch32: Secure PMU counter leak tests
This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
7 files changed