diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 8de7a86..fe29ee5 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -327,6 +327,30 @@
 		}								\
 	} while (false)
 
+#define SKIP_TEST_IF_SCTLR2_NOT_SUPPORTED()					\
+	do {									\
+		if (!is_feat_sctlr2_supported()) {				\
+			tftf_testcase_printf("FEAT_SCTLR2 not supported\n");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
+#define SKIP_TEST_IF_THE_NOT_SUPPORTED()					\
+	do {									\
+		if (!is_feat_the_supported()) {					\
+			tftf_testcase_printf("FEAT_THE not supported\n");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
+#define SKIP_TEST_IF_D128_NOT_SUPPORTED()					\
+	do {									\
+		if (!is_feat_d128_supported()) {				\
+			tftf_testcase_printf("FEAT_D128 not supported\n");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
 #define SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP()				\
 	do {									\
 		u_register_t retrmm = 0U;					\
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 0580f8a..f0c10ef 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -432,6 +432,11 @@
 /* ID_AA64MMFR3_EL1 definitions */
 #define ID_AA64MMFR3_EL1			S3_0_C0_C7_3
 
+#define ID_AA64MMFR3_EL1_D128_SHIFT		U(32)
+#define ID_AA64MMFR3_EL1_D128_MASK		ULL(0xf)
+#define ID_AA64MMFR3_EL1_D128_WIDTH		U(4)
+#define ID_AA64MMFR3_EL1_D128_SUPPORTED		ULL(0x1)
+
 #define ID_AA64MMFR3_EL1_S2POE_SHIFT		U(20)
 #define ID_AA64MMFR3_EL1_S2POE_MASK		ULL(0xf)
 #define ID_AA64MMFR3_EL1_S2POE_WIDTH		U(4)
@@ -453,7 +458,9 @@
 #define ID_AA64MMFR3_EL1_S1PIE_SUPPORTED	ULL(0x1)
 
 #define ID_AA64MMFR3_EL1_SCTLRX_SHIFT		U(4)
+#define ID_AA64MMFR3_EL1_SCTLRX_MASK		ULL(0xf)
 #define ID_AA64MMFR3_EL1_SCTLRX_WIDTH		ULL(0x4)
+#define ID_AA64MMFR3_EL1_SCTLR2_SUPPORTED	ULL(0x1)
 
 #define ID_AA64MMFR3_EL1_TCRX_SHIFT		U(0)
 #define ID_AA64MMFR3_EL1_TCRX_MASK		ULL(0xf)
@@ -465,6 +472,11 @@
 #define ID_AA64PFR1_EL1_DF2_WIDTH		U(4)
 #define ID_AA64PFR1_EL1_DF2_MASK		(0xf << ID_AA64PFR1_EL1_DF2_SHIFT)
 
+#define ID_AA64PFR1_EL1_THE_SHIFT		U(48)
+#define ID_AA64PFR1_EL1_THE_MASK		ULL(0xf)
+#define ID_AA64PFR1_EL1_THE_WIDTH		U(4)
+#define ID_AA64PFR1_EL1_THE_SUPPORTED		ULL(1)
+
 #define ID_AA64PFR1_EL1_GCS_SHIFT		U(44)
 #define ID_AA64PFR1_EL1_GCS_MASK		ULL(0xf)
 #define ID_AA64PFR1_EL1_GCS_WIDTH		U(4)
@@ -571,7 +583,8 @@
 #define SCTLR_DSSBS_BIT		(ULL(1) << 44)
 #define SCTLR_RESET_VAL		SCTLR_EL3_RES1
 
-/* SCTLR2_EL1 register definitions */
+/* SCTLR2 register definitions */
+#define SCTLR2_EL2		S3_4_C1_C0_3
 #define SCTLR2_EL1		S3_0_C1_C0_3
 
 #define SCTLR2_NMEA_BIT		(UL(1) << 2)
@@ -1418,6 +1431,12 @@
  ******************************************************************************/
 #define MDSELR_EL1		S2_0_C0_C4_2
 
+/******************************************************************************
+ * Armv8.9 - Translation Hardening Extension Registers
+ ******************************************************************************/
+#define RCWMASK_EL1		S3_0_C13_C0_6
+#define RCWSMASK_EL1		S3_0_C13_C0_3
+
 /*******************************************************************************
  * Armv9.0 - Trace Buffer Extension System Registers
  ******************************************************************************/
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 2c9ae80..27f5c82 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -537,4 +537,22 @@
 	return EXTRACT(ID_AA64PFR2_EL1_FPMR, read_id_aa64pfr2_el1())
 		== ID_AA64PFR2_EL1_FPMR_SUPPORTED;
 }
+
+static inline bool is_feat_sctlr2_supported(void)
+{
+	return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_SCTLRX_SHIFT) &
+		ID_AA64MMFR3_EL1_SCTLRX_MASK) == ID_AA64MMFR3_EL1_SCTLR2_SUPPORTED);
+}
+
+static inline bool is_feat_the_supported(void)
+{
+	return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_THE_SHIFT) &
+		ID_AA64PFR1_EL1_THE_MASK) == ID_AA64PFR1_EL1_THE_SUPPORTED);
+}
+
+static inline bool is_feat_d128_supported(void)
+{
+	return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_D128_SHIFT) &
+		ID_AA64MMFR3_EL1_D128_MASK) == ID_AA64MMFR3_EL1_D128_SUPPORTED);
+}
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 0774e7b..35d2454 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -324,6 +324,7 @@
 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
 
 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
@@ -648,6 +649,10 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
 
+/* Armv8.9 Translation Hardening Extension */
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
+
 /* Armv9.4 Guarded Control Stack Extension */
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
diff --git a/include/lib/extensions/sysreg128.h b/include/lib/extensions/sysreg128.h
new file mode 100644
index 0000000..5be2ffc
--- /dev/null
+++ b/include/lib/extensions/sysreg128.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SYSREG128_H
+#define SYSREG128_H
+
+#include <stdint.h>
+
+#ifdef __aarch64__
+
+/* Assembly function prototypes. */
+uint128_t read128_par_el1(void);
+uint128_t read128_ttbr0_el1(void);
+uint128_t read128_ttbr1_el1(void);
+uint128_t read128_ttbr0_el2(void);
+uint128_t read128_ttbr1_el2(void);
+uint128_t read128_vttbr_el2(void);
+uint128_t read128_rcwmask_el1(void);
+uint128_t read128_rcwsmask_el1(void);
+
+void write128_par_el1(uint128_t v);
+void write128_ttbr0_el1(uint128_t v);
+void write128_ttbr1_el1(uint128_t v);
+void write128_ttbr0_el2(uint128_t v);
+void write128_ttbr1_el2(uint128_t v);
+void write128_vttbr_el2(uint128_t v);
+void write128_rcwmask_el1(uint128_t v);
+void write128_rcwsmask_el1(uint128_t v);
+
+#endif /* __aarch64__ */
+
+#endif /* SYSREG128_H */