fix(realm): fix realm PMU tests
- FEATURE_PMU_NUM_CTRS field in feature_flag was used
to pass number of PMU event counters in realm creation.
The width of this field was set to 4, which was not
enough to pass numbers > 15 and was causing PMU tests
failures in FVP configuration with more than 15 event
counters implemented.
- This patch removes all FEATURE_XXX macros for setting
feature_flag and replaces them with the corresponding
RMI_FEATURE_REGISTER_0_XXX to match feature register 0.
- In host_set_pmu_state() function was setting PMSELR_EL0
to incorrect value 0 instead of 31 to select PMU cycle
counter for configurations with no event counters implemented.
- Test host_realm_pmuv3_mul_rec() was running incorrectly
with number of event counters set to 0 or 31.
- Reads and writes of PMXEVCNTR_EL0 and PMXEVTYPER_EL0
can be constrained unpredictable depending on the
value of PMSELR_EL0.SEL and number of accessible event
counters. See corresponding TF-RMM patch
https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/34573
This patch fixes host_set_pmu_state() and
host_check_pmu_state() functions to avoid unpredictable access
to these registers.
This patch makes Realm PMU tests pass for all possible FVP
configurations clusterN.pmu-num_counters=[0...31].
Change-Id: I07cc0c14d5705338cb946ddbeddf4c2bad93abe8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 90d4706..1d5e75a 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1171,6 +1171,10 @@
#define PMSELR_EL0_SEL_SHIFT U(0)
#define PMSELR_EL0_SEL_MASK U(0x1f)
+/* PMINTENSET_EL1 definitions */
+#define PMINTENSET_EL1_C_BIT (U(1) << 31)
+#define PMINTENSET_EL1_P_BIT(x) (U(1) << x)
+
/* PMU event counter ID definitions */
#define PMU_EV_PC_WRITE_RETIRED U(0x000C)
diff --git a/include/runtime_services/host_realm_managment/host_realm_rmi.h b/include/runtime_services/host_realm_managment/host_realm_rmi.h
index 4de9671..6394fb6 100644
--- a/include/runtime_services/host_realm_managment/host_realm_rmi.h
+++ b/include/runtime_services/host_realm_managment/host_realm_rmi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -582,15 +582,6 @@
#define RMI_FEATURE_REGISTER_0_MAX_NUM_AUX_PLANES_SHIFT 45UL
#define RMI_FEATURE_REGISTER_0_MAX_NUM_AUX_PLANES_WIDTH 4UL
-#define FEATURE_SVE_VL_SHIFT 56UL
-#define FEATURE_SVE_VL_WIDTH 4UL
-#define FEATURE_NUM_BPS_SHIFT 14UL
-#define FEATURE_NUM_BPS_WIDTH 6UL
-#define FEATURE_NUM_WPS_SHIFT 20UL
-#define FEATURE_NUM_WPS_WIDTH 6UL
-#define FEATURE_PMU_NUM_CTRS_SHIFT 35UL
-#define FEATURE_PMU_NUM_CTRS_WIDTH 4UL
-
/* Possible values for RmiPlaneRttFeature */
#define RMI_PLANE_RTT_AUX 0UL
#define RMI_PLANE_RTT_AUX_SINGLE 1UL
diff --git a/include/runtime_services/host_realm_managment/host_shared_data.h b/include/runtime_services/host_realm_managment/host_shared_data.h
index fecb27b..e9f070c 100644
--- a/include/runtime_services/host_realm_managment/host_shared_data.h
+++ b/include/runtime_services/host_realm_managment/host_shared_data.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,8 @@
REALM_PMU_COUNTER,
REALM_PMU_EVENT,
REALM_PMU_PRESERVE,
- REALM_PMU_INTERRUPT,
+ REALM_PMU_CYCLE_INTERRUPT,
+ REALM_PMU_EVENT_INTERRUPT,
REALM_REQ_FPU_FILL_CMD,
REALM_REQ_FPU_CMP_CMD,
REALM_SET_RIPAS_CMD,
diff --git a/realm/include/realm_tests.h b/realm/include/realm_tests.h
index 2c1d3a1..9abbb4a 100644
--- a/realm/include/realm_tests.h
+++ b/realm/include/realm_tests.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -12,7 +12,7 @@
bool test_pmuv3_counter(void);
bool test_pmuv3_event_works_realm(void);
bool test_pmuv3_rmm_preserves(void);
-bool test_pmuv3_overflow_interrupt(void);
+bool test_pmuv3_overflow_interrupt(bool cycle_cnt);
bool test_realm_pauth_set_cmd(void);
bool test_realm_pauth_check_cmd(void);
bool test_realm_pauth_fault(void);
diff --git a/realm/realm_payload_main.c b/realm/realm_payload_main.c
index aeadb9e..5bc1ef4 100644
--- a/realm/realm_payload_main.c
+++ b/realm/realm_payload_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -433,8 +433,11 @@
case REALM_PMU_PRESERVE:
test_succeed = test_pmuv3_rmm_preserves();
break;
- case REALM_PMU_INTERRUPT:
- test_succeed = test_pmuv3_overflow_interrupt();
+ case REALM_PMU_CYCLE_INTERRUPT:
+ test_succeed = test_pmuv3_overflow_interrupt(true);
+ break;
+ case REALM_PMU_EVENT_INTERRUPT:
+ test_succeed = test_pmuv3_overflow_interrupt(false);
break;
case REALM_REQ_FPU_FILL_CMD:
fpu_state_write_rand(&rl_fpu_state_write);
diff --git a/realm/realm_pmuv3.c b/realm/realm_pmuv3.c
index 214f6df..620daf3 100644
--- a/realm/realm_pmuv3.c
+++ b/realm/realm_pmuv3.c
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <stdlib.h>
+
#include <arch_helpers.h>
#include <arm_arch_svc.h>
#include <debug.h>
@@ -22,20 +24,20 @@
#define PRE_OVERFLOW ~(0xF)
-#define DELAY_MS 3000ULL
+#define DELAY_MS 3000UL
-static inline void read_all_counters(u_register_t *array, int impl_ev_ctrs)
+static inline void read_all_counters(u_register_t *array, unsigned int num_cnts)
{
array[0] = read_pmccntr_el0();
- for (unsigned int i = 0U; i < impl_ev_ctrs; i++) {
+ for (unsigned int i = 0U; i < num_cnts; i++) {
array[i + 1] = read_pmevcntrn_el0(i);
}
}
-static inline void read_all_counter_configs(u_register_t *array, int impl_ev_ctrs)
+static inline void read_all_counter_configs(u_register_t *array, unsigned int num_cnts)
{
array[0] = read_pmccfiltr_el0();
- for (unsigned int i = 0U; i < impl_ev_ctrs; i++) {
+ for (unsigned int i = 0U; i < num_cnts; i++) {
array[i + 1] = read_pmevtypern_el0(i);
}
}
@@ -106,7 +108,7 @@
isb();
}
-static inline void enable_event_counter(int ctr_num)
+static inline void enable_event_counter(unsigned int ctr_num)
{
/*
* Set PMEVTYPER_EL0.U != PMEVTYPER_EL0.RLU
@@ -153,27 +155,21 @@
disable_counting();
clear_counters();
- realm_printf("counted from %lu to %lu\n",
- ccounter_start, ccounter_end);
- if (ccounter_start != ccounter_end) {
- return true;
- }
- return false;
+ realm_printf("cycle counter counted from %lu to %lu\n",
+ ccounter_start, ccounter_end);
+ return (ccounter_start != ccounter_end);
}
/* Test if max counter available is same as that programmed by host */
bool test_pmuv3_counter(void)
{
- uint64_t num_cnts, num_cnts_host;
+ unsigned int num_cnts, num_cnts_host;
num_cnts_host = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
num_cnts = GET_PMU_CNT;
- realm_printf("CPU=%u num_cnts=%lu num_cnts_host=%lu\n", read_mpidr_el1() & MPID_MASK,
+ realm_printf("CPU=%u num_cnts=%u num_cnts_host=%u\n", read_mpidr_el1() & MPID_MASK,
num_cnts, num_cnts_host);
- if (num_cnts == num_cnts_host) {
- return true;
- }
- return false;
+ return (num_cnts == num_cnts_host);
}
/*
@@ -183,28 +179,31 @@
{
u_register_t evcounter_start;
u_register_t evcounter_end;
+ unsigned int num_cnts = GET_PMU_CNT;
+ unsigned int ctr_num;
- if (GET_PMU_CNT == 0) {
- realm_printf("no event counters implemented\n");
- return false;
- }
+ /* Seed the random number generator */
+ srand((unsigned int)read_cntpct_el0());
+
+ /* Select a random number of event counter */
+ ctr_num = (unsigned int)rand() % num_cnts;
pmu_reset();
- enable_event_counter(0);
+ enable_event_counter(ctr_num);
enable_counting();
/*
* If any is enabled it will be in the first range.
*/
- evcounter_start = read_pmevcntrn_el0(0);
+ evcounter_start = read_pmevcntrn_el0(ctr_num);
execute_nops();
disable_counting();
- evcounter_end = read_pmevcntrn_el0(0);
+ evcounter_end = read_pmevcntrn_el0(ctr_num);
clear_counters();
- realm_printf("counted from %lu to %lu\n",
- evcounter_start, evcounter_end);
+ realm_printf("event counter #%u counted from %lu to %lu\n",
+ ctr_num, evcounter_start, evcounter_end);
if (evcounter_start != evcounter_end) {
return true;
}
@@ -222,30 +221,38 @@
u_register_t ctr_end[MAX_COUNTERS] = {0};
u_register_t ctr_cfg_end[MAX_COUNTERS] = {0};
u_register_t pmu_cfg_end[3];
- unsigned int impl_ev_ctrs = GET_PMU_CNT;
+ unsigned int num_cnts = GET_PMU_CNT;
- realm_printf("testing %u event counters\n", impl_ev_ctrs);
+ if (num_cnts == 0U) {
+ realm_printf("testing cycle counter\n");
+ } else {
+ realm_printf("testing %u event counters\n", num_cnts);
+ }
pmu_reset();
- /* Pretend counters have just been used */
+ /* Pretend all counters have just been used */
enable_cycle_counter();
- enable_event_counter(0);
+
+ for (unsigned int i = 0U; i < num_cnts; i++) {
+ enable_event_counter(i);
+ }
+
enable_counting();
execute_nops();
disable_counting();
/* Get before reading */
- read_all_counters(ctr_start, impl_ev_ctrs);
- read_all_counter_configs(ctr_cfg_start, impl_ev_ctrs);
+ read_all_counters(ctr_start, num_cnts);
+ read_all_counter_configs(ctr_cfg_start, num_cnts);
read_all_pmu_configs(pmu_cfg_start);
/* Give RMM a chance to scramble everything */
(void)rsi_get_version(RSI_ABI_VERSION_VAL);
/* Get after reading */
- read_all_counters(ctr_end, impl_ev_ctrs);
- read_all_counter_configs(ctr_cfg_end, impl_ev_ctrs);
+ read_all_counters(ctr_end, num_cnts);
+ read_all_counter_configs(ctr_cfg_end, num_cnts);
read_all_pmu_configs(pmu_cfg_end);
if (memcmp(ctr_start, ctr_end, sizeof(ctr_start)) != 0) {
@@ -269,10 +276,11 @@
return true;
}
-bool test_pmuv3_overflow_interrupt(void)
+bool test_pmuv3_overflow_interrupt(bool cycle_cnt)
{
unsigned long priority_bits, priority;
- uint64_t delay_time = DELAY_MS;
+ unsigned long delay_time = DELAY_MS;
+ unsigned int num_cnts, ctr_num;
pmu_reset();
@@ -292,13 +300,30 @@
/* Enable IRQ */
enable_irq();
- write_pmevcntrn_el0(0, PRE_OVERFLOW);
- enable_event_counter(0);
+ if (cycle_cnt) {
+ write_pmccntr_el0(PRE_OVERFLOW);
+ enable_cycle_counter();
- /* Enable interrupt on event counter #0 */
- write_pmintenset_el1((1UL << 0));
+ /* Enable interrupt on cycle counter */
+ write_pmintenset_el1(PMINTENSET_EL1_C_BIT);
+ realm_printf("waiting for PMU cycle counter vIRQ...\n");
+ } else {
+ num_cnts = GET_PMU_CNT;
- realm_printf("waiting for PMU vIRQ...\n");
+ /* Seed the random number generator */
+ srand((unsigned int)read_cntpct_el0());
+
+ /* Select a random number of event counter */
+ ctr_num = (unsigned int)rand() % num_cnts;
+
+ write_pmevcntrn_el0(ctr_num, PRE_OVERFLOW);
+ enable_event_counter(ctr_num);
+
+ /* Enable interrupt on event counter */
+ write_pmintenset_el1(PMINTENSET_EL1_P_BIT(ctr_num));
+ realm_printf("waiting for PMU event counter #%u vIRQ...\n",
+ ctr_num);
+ }
enable_counting();
execute_nops();
@@ -308,7 +333,7 @@
* Performance Monitors Interrupt Enable Set register
* as part of handling the overflow interrupt.
*/
- while ((read_pmintenset_el1() != 0UL) && (delay_time != 0ULL)) {
+ while ((read_pmintenset_el1() != 0UL) && (delay_time != 0UL)) {
--delay_time;
}
@@ -317,14 +342,13 @@
pmu_reset();
- if (delay_time == 0ULL) {
- realm_printf("PMU vIRQ %sreceived in %llums\n", "not ",
+ if (delay_time == 0UL) {
+ realm_printf("PMU vIRQ %sreceived in %lums\n", "not ",
DELAY_MS);
return false;
}
- realm_printf("PMU vIRQ %sreceived in %llums\n", "",
+ realm_printf("PMU vIRQ %sreceived in %lums\n", "",
DELAY_MS - delay_time);
-
return true;
}
diff --git a/tftf/tests/runtime_services/host_realm_managment/host_pmuv3.c b/tftf/tests/runtime_services/host_realm_managment/host_pmuv3.c
index 16e87e9..04c56a2 100644
--- a/tftf/tests/runtime_services/host_realm_managment/host_pmuv3.c
+++ b/tftf/tests/runtime_services/host_realm_managment/host_pmuv3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,9 +65,9 @@
CHECK_PMEV_REG(n, pmevtyper); \
}
-#define WRITE_PMREG(reg, mask) { \
+#define WRITE_PMREG(reg, mask) { \
pmu_ptr->reg = rand64() & mask; \
- write_##reg(pmu_ptr->reg); \
+ write_##reg(pmu_ptr->reg); \
}
#define CHECK_PMREG(reg) { \
@@ -103,11 +103,15 @@
pmu_ptr->pmintenset_el1 = 0UL;
write_pmintenclr_el1(PMU_CLEAR_ALL);
+ /* Seed the random number generator */
+ srand((unsigned int)read_cntpct_el0());
+
WRITE_PMREG(pmccntr_el0, UINT64_MAX);
WRITE_PMREG(pmccfiltr_el0, PMCCFILTR_EL0_MASK);
pmu_ptr->pmuserenr_el0 = read_pmuserenr_el0();
+ /* Check number of event counters implemented */
if (num_cnts != 0U) {
switch (--num_cnts) {
WRITE_PMEV_REGS(30);
@@ -144,17 +148,37 @@
WRITE_PMEV_REGS(0);
}
- /* Generate a random number between 0 and num_cnts */
+ /* Seed the random number generator */
+ srand((unsigned int)read_cntpct_el0());
+
+ /*
+ * Select a random number of event counter
+ * between 0 and num_cnts - 1
+ */
val = rand() % ++num_cnts;
} else {
- val = 0UL;
+ /* Select the cycle counter, PMCCNTR_EL0 */
+ val = 31UL;
}
pmu_ptr->pmselr_el0 = val;
write_pmselr_el0(val);
- pmu_ptr->pmxevcntr_el0 = read_pmxevcntr_el0();
- pmu_ptr->pmxevtyper_el0 = read_pmxevtyper_el0();
+ /*
+ * When PMSELR_EL0.SEL is greater than or equal to the number of
+ * accessible event counters, then reads and writes of PMXEVCNTR_EL0
+ * are CONSTRAINED UNPREDICTABLE.
+ *
+ * When PMSELR_EL0.SEL is not 31 and is greater than or equal to the
+ * number of accessible event counters, then reads and writes of
+ * PMXEVTYPER_EL0 are CONSTRAINED UNPREDICTABLE.
+ */
+ if (val < num_cnts) {
+ pmu_ptr->pmxevcntr_el0 = read_pmxevcntr_el0();
+ pmu_ptr->pmxevtyper_el0 = read_pmxevtyper_el0();
+ } else if (val == 31UL) {
+ pmu_ptr->pmxevtyper_el0 = read_pmxevtyper_el0();
+ }
}
bool host_check_pmu_state(struct pmu_registers *pmu_ptr)
@@ -173,9 +197,15 @@
CHECK_PMREG(pmccfiltr_el0);
CHECK_PMREG(pmuserenr_el0);
CHECK_PMREG(pmselr_el0);
- CHECK_PMREG(pmxevcntr_el0);
- CHECK_PMREG(pmxevtyper_el0);
+ if (pmu_ptr->pmselr_el0 < num_cnts) {
+ CHECK_PMREG(pmxevcntr_el0);
+ CHECK_PMREG(pmxevtyper_el0);
+ } else if (pmu_ptr->pmselr_el0 == 31UL) {
+ CHECK_PMREG(pmxevtyper_el0);
+ }
+
+ /* Check number of event counters implemented */
if (num_cnts != 0UL) {
switch (--num_cnts) {
CHECK_PMEV_REGS(30);
diff --git a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
index c1edd79..e73fe0d 100644
--- a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
+++ b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -179,14 +179,9 @@
realm_ptr->rmm_feat_reg0 &= ~RMI_FEATURE_REGISTER_0_PMU_EN;
realm_ptr->pmu_num_ctrs = 0U;
} else {
- value = EXTRACT(FEATURE_PMU_NUM_CTRS, feature_flag);
- if (value != -1) {
- realm_ptr->pmu_num_ctrs = (unsigned int)value;
- } else {
- realm_ptr->pmu_num_ctrs =
- EXTRACT(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS,
- realm_ptr->rmm_feat_reg0);
- }
+ /* Requested number of event counters */
+ realm_ptr->pmu_num_ctrs = EXTRACT(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS,
+ feature_flag);
}
/* Disable SVE if not required */
@@ -194,11 +189,12 @@
realm_ptr->rmm_feat_reg0 &= ~RMI_FEATURE_REGISTER_0_SVE_EN;
realm_ptr->sve_vl = 0U;
} else {
- realm_ptr->sve_vl = EXTRACT(FEATURE_SVE_VL, feature_flag);
+ realm_ptr->sve_vl = EXTRACT(RMI_FEATURE_REGISTER_0_SVE_VL,
+ feature_flag);
}
/* Requested number of breakpoints */
- value = EXTRACT(FEATURE_NUM_BPS, feature_flag);
+ value = EXTRACT(RMI_FEATURE_REGISTER_0_NUM_BPS, feature_flag);
if (value != 0) {
realm_ptr->num_bps = (unsigned int)value;
} else {
@@ -207,7 +203,7 @@
}
/* Requested number of watchpoints */
- value = EXTRACT(FEATURE_NUM_WPS, feature_flag);
+ value = EXTRACT(RMI_FEATURE_REGISTER_0_NUM_WPS, feature_flag);
if (value != 0) {
realm_ptr->num_wps = (unsigned int)value;
} else {
@@ -423,7 +419,6 @@
return false;
}
-
if (test_exit_reason == realm_exit_reason) {
if (realm_exit_reason != RMI_EXIT_HOST_CALL) {
return true;
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c b/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
index 00d2d57..5c3299a 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,7 +38,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -109,7 +109,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -250,7 +250,7 @@
rec_count = tftf_get_total_cpus_count();
assert(rec_count <= MAX_REC_COUNT);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -354,7 +354,7 @@
rec_count = tftf_get_total_cpus_count();
assert(rec_count <= MAX_REC_COUNT);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -492,7 +492,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -640,10 +640,12 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
+ host_rmi_init_cmp_result();
+
rec_count = tftf_get_total_cpus_count();
assert(rec_count <= MAX_REC_COUNT);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -652,7 +654,7 @@
rec_flag[i] = RMI_RUNNABLE;
}
- /* Get Max PMU counter implemented through RMI_FEATURES */
+ /* Get number of PMU event counters implemented through RMI_FEATURES */
if (host_rmi_features(0UL, &rmm_feat_reg0) != REALM_SUCCESS) {
ERROR("%s() failed\n", "host_rmi_features");
return TEST_RESULT_FAIL;
@@ -664,127 +666,141 @@
is_secondary_cpu_on = 0;
my_mpidr = read_mpidr_el1() & MPID_MASK;
- if (num_cnts == 0U) {
- ERROR("No PMU counters implemented\n");
- return TEST_RESULT_SKIPPED;
+ if (num_cnts == 0) {
+ INFO("No event counters implemented\n");
+ } else {
+ INFO("Testing %u event counters\n", num_cnts);
}
- feature_flag |= RMI_FEATURE_REGISTER_0_PMU_EN |
- INPLACE(FEATURE_PMU_NUM_CTRS, num_cnts + 1U);
+ /*
+ * Check that number of event counters is less
+ * than maximum supported by architecture.
+ */
+ if (num_cnts < ((1U << RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS_WIDTH) - 1U)) {
+ feature_flag |= RMI_FEATURE_REGISTER_0_PMU_EN |
+ INPLACE(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS, num_cnts + 1U);
- /* Request more PMU counter than total, expect failure */
- if (host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
- feature_flag, sl, rec_flag, 1U, 0U)) {
- ERROR("Realm create should have failed\n");
- host_destroy_realm(&realm);
- return TEST_RESULT_FAIL;
+ if (is_feat_52b_on_4k_2_supported()) {
+ feature_flag |= RMI_FEATURE_REGISTER_0_LPA2;
+ }
+
+ /* Request more event counters than total, expect failure */
+ if (host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
+ feature_flag, sl, rec_flag, 1U, 0U)) {
+ ERROR("Realm create should have failed\n");
+ host_destroy_realm(&realm);
+ return TEST_RESULT_FAIL;
+ }
}
- /* Request 0 PMU counter */
+ /* Request Cycle Counter with no event counters */
feature_flag = RMI_FEATURE_REGISTER_0_PMU_EN |
- INPLACE(FEATURE_PMU_NUM_CTRS, 0U);
+ INPLACE(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS, 0U);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag |= RMI_FEATURE_REGISTER_0_LPA2;
}
ret1 = host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
- feature_flag, sl, rec_flag, 1U, 0U);
+ feature_flag, sl, rec_flag, 1U, 0U);
+ host_destroy_realm(&realm);
if (!get_feat_hpmn0_supported()) {
if (ret1) {
- ERROR("Realm create with 0 PMU Counter should have failed\n");
- host_destroy_realm(&realm);
+ ERROR("Realm create with 0 event counters should have failed\n");
return TEST_RESULT_FAIL;
}
} else {
if (!ret1) {
- ERROR("Realm create with 0 PMU Counter should not have failed\n");
+ ERROR("Realm create with 0 event counters should not have failed\n");
return TEST_RESULT_FAIL;
}
- host_destroy_realm(&realm);
}
- /* Test 2 create first realm with max PMU counters */
+ /* Create first realm with number of PMU event counters */
feature_flag = RMI_FEATURE_REGISTER_0_PMU_EN |
- INPLACE(FEATURE_PMU_NUM_CTRS, num_cnts);
+ INPLACE(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS, num_cnts);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag |= RMI_FEATURE_REGISTER_0_LPA2;
}
- /* Prepare realm0, create recs for realm0 later */
+ /* Prepare realm, create recs later */
if (!host_prepare_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
feature_flag, sl, rec_flag, rec_count, 0U)) {
- goto test_exit;
return TEST_RESULT_FAIL;
}
- /* Second realm with less num of PMU counters */
+ /*
+ * Second realm1 with less or equal number of event counters.
+ * When no event counters are implemented, only Cycle Counter
+ * will be tested.
+ */
feature_flag = RMI_FEATURE_REGISTER_0_PMU_EN |
- INPLACE(FEATURE_PMU_NUM_CTRS, num_cnts - 1U);
+ INPLACE(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS,
+ (num_cnts == 0U) ? num_cnts : num_cnts - 1U);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag |= RMI_FEATURE_REGISTER_0_LPA2;
}
- if (!host_create_activate_realm_payload(&realm1, (u_register_t)REALM_IMAGE_BASE,
- feature_flag, sl, rec_flag, rec_count, 0U)) {
- goto test_exit2;
+ ret1 = host_create_activate_realm_payload(&realm1, (u_register_t)REALM_IMAGE_BASE,
+ feature_flag, sl, rec_flag, rec_count, 0U);
+ if (!ret1) {
+ goto test_exit;
}
- /* create realm0 recs, activate realm0 */
+ /* Create realm recs, activate realm0 */
if (host_realm_rec_create(&realm) != REALM_SUCCESS) {
ERROR("%s() failed\n", "host_realm_rec_create");
- goto test_exit2;
+ goto test_exit;
}
if (host_realm_init_ipa_state(&realm, sl, 0U, 1ULL << 32)
!= RMI_SUCCESS) {
ERROR("%s() failed\n", "host_realm_init_ipa_state");
- goto test_exit2;
+ goto test_exit;
}
if (host_realm_activate(&realm) != REALM_SUCCESS) {
ERROR("%s() failed\n", "host_realm_activate");
- goto test_exit2;
+ goto test_exit;
}
- INFO("MAX PMU Counter=%u\n", num_cnts);
- /* Pass num of PMU counters programmed to realm */
+ /* Pass number of event counters programmed to realms */
for (unsigned int j = 0U; j < rec_count; j++) {
host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, j,
- HOST_ARG1_INDEX, num_cnts);
-
+ HOST_ARG1_INDEX, num_cnts);
host_shared_data_set_host_val(&realm1, PRIMARY_PLANE_ID, j,
- HOST_ARG1_INDEX, num_cnts - 1U);
+ HOST_ARG1_INDEX,
+ (num_cnts == 0U) ? 0U : num_cnts - 1U);
}
/*
- * Enter realm0 rec0 test PMU counters available is same as that programmed by host
- * Validation is done by the Realm and will return error if the count does not match
+ * Enter realm rec0 test PMU counters available is same as that programmed by host.
+ * Validation is done by the Realm and will return error if the count does not match.
*/
ret1 = host_enter_realm_execute(&realm, REALM_PMU_COUNTER, RMI_EXIT_HOST_CALL, 0U);
if (!ret1) {
- goto test_exit2;
+ goto test_exit;
}
/* Enter realm1 rec0 test PMU counters available is same as that programmed by host */
ret1 = host_enter_realm_execute(&realm1, REALM_PMU_COUNTER, RMI_EXIT_HOST_CALL, 0U);
if (!ret1) {
- goto test_exit2;
+ goto test_exit;
}
- /* Test if Realm0 rec0 entering/exiting preserves PMU state */
+ /* Test if realm rec0 entering/exiting preserves PMU state */
ret1 = host_enter_realm_execute(&realm, REALM_PMU_PRESERVE, RMI_EXIT_HOST_CALL, 0U);
if (!ret1) {
- goto test_exit2;
+ goto test_exit;
}
- /* Test if Realm1 rec0 entering/exiting preserves PMU state */
+ /* Test if realm1 rec0 entering/exiting preserves PMU state */
ret1 = host_enter_realm_execute(&realm1, REALM_PMU_PRESERVE, RMI_EXIT_HOST_CALL, 0U);
if (!ret1) {
- goto test_exit2;
+ goto test_exit;
}
if (!host_check_pmu_state(&pmu_state[0U])) {
@@ -807,7 +823,7 @@
ret = tftf_try_cpu_on(other_mpidr, (uintptr_t)cpu_on_handler_pmu, 0);
if (ret != PSCI_E_SUCCESS) {
ERROR("TFTF CPU ON failed\n");
- goto test_exit2;
+ goto test_exit;
}
i++;
}
@@ -828,17 +844,17 @@
}
}
-test_exit2:
+test_exit:
ret2 = host_destroy_realm(&realm1);
if (!ret1 || !ret2) {
ERROR("%s() enter=%u destroy=%u\n", __func__, ret1, ret2);
}
-test_exit:
+
ret2 = host_destroy_realm(&realm);
if (!ret1 || !ret2) {
ERROR("%s() enter=%u destroy=%u\n", __func__, ret1, ret2);
return TEST_RESULT_FAIL;
}
- return TEST_RESULT_SUCCESS;
+ return host_cmp_result();
}
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
index 760a286..9b03393 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -188,7 +188,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -236,7 +236,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -275,7 +275,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -340,7 +340,7 @@
u_register_t feature_flag = 0U;
long sl = RTT_MIN_LEVEL;
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -444,9 +444,9 @@
host_set_pmu_state(&pmu_state);
feature_flag = RMI_FEATURE_REGISTER_0_PMU_EN |
- INPLACE(FEATURE_PMU_NUM_CTRS, num_cnts);
+ INPLACE(RMI_FEATURE_REGISTER_0_PMU_NUM_CTRS, num_cnts);
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag |= RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -457,9 +457,11 @@
}
ret1 = host_enter_realm_execute(&realm, cmd,
- (cmd == REALM_PMU_INTERRUPT) ?
+ ((cmd == REALM_PMU_CYCLE_INTERRUPT) ||
+ (cmd == REALM_PMU_EVENT_INTERRUPT)) ?
RMI_EXIT_IRQ : RMI_EXIT_HOST_CALL, 0U);
- if (!ret1 || (cmd != REALM_PMU_INTERRUPT)) {
+ if (!ret1 || ((cmd != REALM_PMU_CYCLE_INTERRUPT) &&
+ (cmd != REALM_PMU_EVENT_INTERRUPT))) {
goto test_exit;
}
@@ -492,6 +494,11 @@
*/
test_result_t host_realm_pmuv3_event_works(void)
{
+ if (GET_PMU_CNT == 0) {
+ tftf_testcase_printf("No event counters implemented\n");
+ return TEST_RESULT_SKIPPED;
+ }
+
return host_test_realm_pmuv3(REALM_PMU_EVENT);
}
@@ -515,22 +522,50 @@
return -1;
}
-/*
- * Test PMU interrupt functionality in Realm
- */
-test_result_t host_realm_pmuv3_overflow_interrupt(void)
+static test_result_t host_realm_pmuv3_overflow_interrupt(uint8_t cmd)
{
- /* Register PMU IRQ handler */
- int ret = tftf_irq_register_handler(PMU_PPI, host_overflow_interrupt);
+ test_result_t ret;
- if (ret != 0) {
- tftf_testcase_printf("Failed to %sregister IRQ handler\n",
- "");
+ /* Register PMU IRQ handler */
+ if (tftf_irq_register_handler(PMU_PPI, host_overflow_interrupt) != 0) {
+ tftf_testcase_printf("Failed to %sregister IRQ handler\n", "");
return TEST_RESULT_FAIL;
}
tftf_irq_enable(PMU_PPI, GIC_HIGHEST_NS_PRIORITY);
- return host_test_realm_pmuv3(REALM_PMU_INTERRUPT);
+
+ ret = host_test_realm_pmuv3(cmd);
+ if (ret != TEST_RESULT_SUCCESS) {
+ tftf_irq_disable(PMU_PPI);
+ if (tftf_irq_unregister_handler(PMU_PPI) != 0) {
+ ERROR("Failed to %sregister IRQ handler\n", "un");
+ return TEST_RESULT_FAIL;
+ }
+ return ret;
+ }
+
+ return TEST_RESULT_SUCCESS;
+}
+
+/*
+ * Test PMU cycle counter interrupt functionality in Realm
+ */
+test_result_t host_realm_pmuv3_cycle_overflow_interrupt(void)
+{
+ return host_realm_pmuv3_overflow_interrupt(REALM_PMU_CYCLE_INTERRUPT);
+}
+
+/*
+ * Test PMU event counter interrupt functionality in Realm
+ */
+test_result_t host_realm_pmuv3_event_overflow_interrupt(void)
+{
+ if (GET_PMU_CNT == 0) {
+ tftf_testcase_printf("No event counters implemented\n");
+ return TEST_RESULT_SKIPPED;
+ }
+
+ return host_realm_pmuv3_overflow_interrupt(REALM_PMU_EVENT_INTERRUPT);
}
/*
@@ -550,7 +585,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -625,7 +660,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -724,7 +759,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -796,7 +831,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -922,7 +957,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1031,7 +1066,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1166,7 +1201,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1308,7 +1343,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1412,7 +1447,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1646,7 +1681,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -1832,7 +1867,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2025,7 +2060,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2182,7 +2217,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2357,7 +2392,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2472,7 +2507,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2585,7 +2620,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2698,7 +2733,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
SKIP_TEST_IF_DOUBLE_FAULT2_NOT_SUPPORTED();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2761,7 +2796,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
@@ -2802,7 +2837,7 @@
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- if (is_feat_52b_on_4k_2_supported() == true) {
+ if (is_feat_52b_on_4k_2_supported()) {
feature_flag = RMI_FEATURE_REGISTER_0_LPA2;
sl = RTT_MIN_LEVEL_LPA2;
}
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.c b/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.c
index 235e093..40e8590 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.c
@@ -33,7 +33,7 @@
if (sve_en) {
feature_flag |= RMI_FEATURE_REGISTER_0_SVE_EN |
- INPLACE(FEATURE_SVE_VL, sve_vq);
+ INPLACE(RMI_FEATURE_REGISTER_0_SVE_VL, sve_vq);
}
/* Initialise Realm payload */
diff --git a/tftf/tests/tests-realm-payload.xml b/tftf/tests/tests-realm-payload.xml
index 7cc7866..c63b296 100644
--- a/tftf/tests/tests-realm-payload.xml
+++ b/tftf/tests/tests-realm-payload.xml
@@ -70,8 +70,10 @@
function="host_realm_pmuv3_event_works" />
<testcase name="PMUv3 RSI SMC counter preservation"
function="host_realm_pmuv3_rmm_preserves" />
- <testcase name="PMUv3 overflow interrupt"
- function="host_realm_pmuv3_overflow_interrupt" />
+ <testcase name="PMUv3 cycle counter overflow interrupt"
+ function="host_realm_pmuv3_cycle_overflow_interrupt" />
+ <testcase name="PMUv3 event counter overflow interrupt"
+ function="host_realm_pmuv3_event_overflow_interrupt" />
<testcase name="PMUv3 multiple rec validations"
function="host_realm_pmuv3_mul_rec" />
<testcase name="Test Secure interrupt can preempt Realm EL1"