aarch64: enable SError aborts
This patch enables SError aborts for all CPUs, during their power
on sequence.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3be0e593c709d65f03275b641b506c8669f2b475
diff --git a/tftf/framework/aarch64/arch.c b/tftf/framework/aarch64/arch.c
index c3f57b8..56369ae 100644
--- a/tftf/framework/aarch64/arch.c
+++ b/tftf/framework/aarch64/arch.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +11,9 @@
{
/* Do not try to configure EL2 if TFTF is running at NS-EL1 */
if (IS_IN_EL2()) {
+ /* Enable asynchronous SError aborts to EL2 */
+ enable_serror();
+
/*
* Route physical interrupts to EL2 regardless of the value of
* the IMO/FMO bits. Without this, interrupts would not be taken