test(realm): add test for multi rec planes
Test exercises SMC_PSCI_CPU_ON from aux plane.
Request is first routed to P0 and then to Host.
Host enters P0 and then P1 on all CPUs.
Change-Id: I7e34a0070ffa7305b97a0d93de62b64042771a18
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
diff --git a/realm/realm_plane.c b/realm/realm_plane.c
index c7225ed..3b79aff 100644
--- a/realm/realm_plane.c
+++ b/realm/realm_plane.c
@@ -11,6 +11,8 @@
#include <debug.h>
#include <host_realm_helper.h>
+#include <psci.h>
+#include <realm_psci.h>
#include <realm_psi.h>
#include <realm_rsi.h>
#include <sync.h>
@@ -102,10 +104,30 @@
/* Disallow SMC from Plane N */
if (ec == EC_AARCH64_SMC) {
- /* TODO Support PSCI in future */
+ u_register_t smc_id = run->exit.gprs[0];
+
restore_plane_context(run);
- run->enter.gprs[0] = RSI_ERROR_STATE;
- return PSI_RETURN_TO_PN;
+ switch (smc_id) {
+ case SMC_PSCI_CPU_ON_AARCH64:
+ assert(run->exit.gprs[1] < MAX_REC_COUNT);
+ assert(run->exit.gprs[1] != 0U);
+ /* Let P0 handle CPU ON */
+ return PSI_RETURN_TO_P0;
+ case SMC_PSCI_CPU_OFF:
+ realm_cpu_off();
+ /* Does not return. */
+ return PSI_RETURN_TO_PN;
+ case SMC_PSCI_FEATURES:
+ run->enter.gprs[0] = realm_psci_features(run->exit.gprs[1U]);
+ return PSI_RETURN_TO_PN;
+ case SMC_PSCI_AFFINITY_INFO:
+ run->enter.gprs[0] = realm_psci_affinity_info(run->exit.gprs[1U],
+ run->exit.gprs[2U]);
+ return PSI_RETURN_TO_PN;
+ default:
+ run->enter.gprs[0] = RSI_ERROR_STATE;
+ return PSI_RETURN_TO_PN;
+ }
}
/* Handle PSI HVC call from Plane N */