f369717f93ee8d7e2c12460e71d335bc702e37b4 - next/TF-A/tf-a-tests

commit	f369717f93ee8d7e2c12460e71d335bc702e37b4	[log] [tgz]
author	Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>	Mon Sep 04 15:04:46 2023 +0100
committer	Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>	Wed Oct 25 15:07:15 2023 +0100
tree	ff959de9f2e05c711dae73bedf2e5b8a34d56f2b
parent	6e587999a0b2f3055d14e08b7bbcfa5735db9891 [diff]

test(rme): check various SIMD state preserved across NS/RL switch

Thie test case verifies whether various SIMD related registers like
Q[0-31], FPCR, FPSR, Z[0-31], P[0-15], FFR are preserved by RMM during
world switch between NS world and Realm world.

Randomly verify FPU registers or SVE registers if the system supports
SVE. Within SVE, randomly configure SVE vector length.

This testcase runs on below configs:
* with SVE
* without SVE

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I3fc755f75bdcdc8c24af0440d8a5f094beafca73

include/runtime_services/host_realm_managment/host_shared_data.h[diff]
realm/include/realm_tests.h[diff]
realm/realm.mk[diff]
realm/realm_payload_main.c[diff]
realm/realm_simd.c[Renamed from realm/realm_sve.c - diff]
tftf/tests/runtime_services/realm_payload/host_realm_payload_simd_tests.c[Renamed from tftf/tests/runtime_services/realm_payload/host_realm_payload_sve_tests.c - diff]
tftf/tests/tests-realm-payload.mk[diff]
tftf/tests/tests-realm-payload.xml[diff]

8 files changed

tree: ff959de9f2e05c711dae73bedf2e5b8a34d56f2b