diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 8e17140..8d24a05 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -247,6 +247,14 @@
 		}								\
 	} while (false);
 
+#define SKIP_TEST_IF_TRBE_NOT_SUPPORTED()					\
+	do {									\
+		if (!get_armv9_0_trbe_support()) {				\
+			tftf_testcase_printf("ARMv9-TRBE not supported\n");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
 /* Helper macro to verify if system suspend API is supported */
 #define is_psci_sys_susp_supported()	\
 		(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND)		\
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index f268167..da76039 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -162,6 +162,11 @@
 #define ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED	U(8)
 #define ID_AA64DFR0_V8_4_DEBUG_ARCH_SUPPORTED	U(9)
 
+/* ID_AA64DFR0_EL1.TraceBuffer definitions */
+#define ID_AA64DFR0_TRACEBUFFER_SHIFT		U(44)
+#define ID_AA64DFR0_TRACEBUFFER_MASK		ULL(0xf)
+#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED	ULL(1)
+
 #define EL_IMPL_NONE		ULL(0)
 #define EL_IMPL_A64ONLY		ULL(1)
 #define EL_IMPL_A64_A32		ULL(2)
@@ -998,5 +1003,15 @@
  ******************************************************************************/
 #define CNTPOFF_EL2  S3_4_C14_C0_6
 
+/*******************************************************************************
+ * Armv9.0 - Trace Buffer Extension System Registers
+ ******************************************************************************/
+#define TRBLIMITR_EL1	S3_0_C9_C11_0
+#define TRBPTR_EL1	S3_0_C9_C11_1
+#define TRBBASER_EL1	S3_0_C9_C11_2
+#define TRBSR_EL1	S3_0_C9_C11_3
+#define TRBMAR_EL1	S3_0_C9_C11_4
+#define TRBTRG_EL1	S3_0_C9_C11_6
+#define TRBIDR_EL1	S3_0_C9_C11_7
 
 #endif /* ARCH_H */
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 15eb784..d2665b4 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -92,4 +92,11 @@
 		ID_AA64DFR0_DEBUG_SHIFT);
 }
 
+static inline bool get_armv9_0_trbe_support(void)
+{
+        return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) &
+		ID_AA64DFR0_TRACEBUFFER_MASK) ==
+		ID_AA64DFR0_TRACEBUFFER_SUPPORTED;
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 39f1e3b..cb10cfe 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -489,6 +489,15 @@
 /* Armv8.6 Enhanced Counter Virtualization Register */
 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2,  CNTPOFF_EL2)
 
+/* Armv9.0 Trace buffer extension System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(trblimitr_el1, TRBLIMITR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trbptr_el1, TRBPTR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trbbaser_el1, TRBBASER_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trbsr_el1, TRBSR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trbmar_el1, TRBMAR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trbtrg_el1, TRBTRG_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(trbidr_el1, TRBIDR_EL1)
+
 #define IS_IN_EL(x) \
 	(GET_EL(read_CurrentEl()) == MODE_EL##x)
 
diff --git a/tftf/tests/extensions/trbe/test_trbe.c b/tftf/tests/extensions/trbe/test_trbe.c
new file mode 100644
index 0000000..8ef9576
--- /dev/null
+++ b/tftf/tests/extensions/trbe/test_trbe.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+
+/*
+ * EL3 is expected to allow access to trace control registers from EL2.
+ * Reading these register will trap to EL3 and crash when EL3 has not
+ * allowed access.
+ */
+test_result_t test_trbe_enabled(void)
+{
+        SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+	SKIP_TEST_IF_TRBE_NOT_SUPPORTED();
+	read_trblimitr_el1();
+	read_trbptr_el1();
+	read_trbbaser_el1();
+	read_trbsr_el1();
+	read_trbmar_el1();
+	read_trbtrg_el1();
+	read_trbidr_el1();
+	return TEST_RESULT_SUCCESS;
+#endif  /* __aarch64__ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index fedf783..a4e5d11 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -1,18 +1,19 @@
 #
-# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2021, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 TESTS_SOURCES	+=	$(addprefix tftf/tests/,			\
 	extensions/amu/test_amu.c					\
+	extensions/ecv/test_ecv.c					\
+	extensions/fgt/test_fgt.c					\
 	extensions/mte/test_mte.c					\
+	extensions/pauth/test_pauth.c					\
 	extensions/sve/sve_operations.S					\
 	extensions/sve/test_sve.c					\
-	extensions/fgt/test_fgt.c					\
-	extensions/ecv/test_ecv.c					\
+	extensions/trbe/test_trbe.c					\
+	runtime_services/arm_arch_svc/smccc_arch_soc_id.c		\
 	runtime_services/arm_arch_svc/smccc_arch_workaround_1.c		\
 	runtime_services/arm_arch_svc/smccc_arch_workaround_2.c		\
-	runtime_services/arm_arch_svc/smccc_arch_soc_id.c		\
-	extensions/pauth/test_pauth.c					\
 )
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 08a65c7..d6b3d00 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 
 <!--
-  Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+  Copyright (c) 2018-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-3-Clause
 -->
@@ -20,6 +20,7 @@
     <testcase name="Check for MTE register leakage" function="test_mte_leakage" />
     <testcase name="Use FGT Registers" function="test_fgt_enabled" />
     <testcase name="Use ECV Registers" function="test_ecv_enabled" />
+    <testcase name="Use trace buffer control Registers" function="test_trbe_enabled" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">