diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 0881f00..05ecbb8 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -273,6 +273,14 @@
 		}								\
 	} while (false)
 
+#define SKIP_TEST_IF_AFP_NOT_SUPPORTED()					\
+	do {									\
+		if (!get_feat_afp_present()) {					\
+			tftf_testcase_printf("ARMv8.7-afp not supported");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
 /* Helper macro to verify if system suspend API is supported */
 #define is_psci_sys_susp_supported()	\
 		(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND)		\
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 75fdfcf..7596026 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -254,6 +254,9 @@
 #define ID_AA64MMFR1_EL1_HCX_MASK		ULL(0xf)
 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED		ULL(0x1)
 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED	ULL(0x0)
+#define ID_AA64MMFR1_EL1_AFP_SHIFT		U(44)
+#define ID_AA64MMFR1_EL1_AFP_MASK		ULL(0xf)
+#define ID_AA64MMFR1_EL1_AFP_SUPPORTED		ULL(0x1)
 
 /* ID_AA64MMFR2_EL1 definitions */
 #define ID_AA64MMFR2_EL1		S3_0_C0_C7_2
@@ -641,6 +644,13 @@
 
 #define MAX_CACHE_LINE_SIZE	U(0x800) /* 2KB */
 
+/*
+ * FPCR definitions
+ */
+#define FPCR_FIZ_BIT		(ULL(1) << 0)
+#define FPCR_AH_BIT		(ULL(1) << 1)
+#define FPCR_NEP_BIT		(ULL(1) << 2)
+
 /* Physical timer control register bit fields shifts and masks */
 #define CNTP_CTL_ENABLE_SHIFT   U(0)
 #define CNTP_CTL_IMASK_SHIFT    U(1)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index a111c2c..b0ec17a 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -142,4 +142,10 @@
 		ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
 }
 
+static inline bool get_feat_afp_present(void)
+{
+	return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_AFP_SHIFT) &
+		  ID_AA64MMFR1_EL1_AFP_MASK) == ID_AA64MMFR1_EL1_AFP_SUPPORTED);
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index f42f2f8..eac8b7c 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -544,6 +544,9 @@
 /* FEAT_HCX HCRX_EL2 */
 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
 
+/* Control floating point behaviour */
+DEFINE_RENAME_SYSREG_RW_FUNCS(fpcr, FPCR)
+
 #define IS_IN_EL(x) \
 	(GET_EL(read_CurrentEl()) == MODE_EL##x)
 
diff --git a/tftf/tests/extensions/afp/test_afp.c b/tftf/tests/extensions/afp/test_afp.c
new file mode 100644
index 0000000..625d9cf
--- /dev/null
+++ b/tftf/tests/extensions/afp/test_afp.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+
+test_result_t test_afp_support(void)
+{
+	SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+	test_result_t ret;
+	uint64_t saved_fpcr, fpcr;
+
+	SKIP_TEST_IF_AFP_NOT_SUPPORTED();
+
+	saved_fpcr = read_fpcr();
+	/* Write advanced floating point controlling bits */
+	write_fpcr(saved_fpcr | FPCR_FIZ_BIT | FPCR_AH_BIT | FPCR_NEP_BIT);
+
+	fpcr = read_fpcr();
+	/* Check if all bits got written successfully */
+	if ((fpcr | ~(FPCR_FIZ_BIT | FPCR_AH_BIT | FPCR_NEP_BIT)) == ~0ULL) {
+		ret = TEST_RESULT_SUCCESS;
+	} else {
+		ret = TEST_RESULT_FAIL;
+	}
+
+	write_fpcr(saved_fpcr);
+
+	return ret;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 5845212..4600e7f 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -5,6 +5,7 @@
 #
 
 TESTS_SOURCES	+=	$(addprefix tftf/tests/,			\
+	extensions/afp/test_afp.c					\
 	extensions/amu/test_amu.c					\
 	extensions/ecv/test_ecv.c					\
 	extensions/fgt/test_fgt.c					\
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 3d18f84..97826cc 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -25,6 +25,7 @@
     <testcase name="Use trace system Registers" function="test_sys_reg_trace_enabled" />
     <testcase name="SME support" function="test_sme_support" />
     <testcase name="SPE support" function="test_spe_support" />
+    <testcase name="AFP support" function="test_afp_support" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">