feat(afp): add a test for Advanced floating-point
This test is to ensure that TFTF is allowed to write the FPCR register
bits to control the floating-point operation when FEAT_AFP is
implemented.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I21ea288e698bbe706aac55740e28d5f6ccb700dc
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index a111c2c..b0ec17a 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,4 +142,10 @@
ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
}
+static inline bool get_feat_afp_present(void)
+{
+ return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_AFP_SHIFT) &
+ ID_AA64MMFR1_EL1_AFP_MASK) == ID_AA64MMFR1_EL1_AFP_SUPPORTED);
+}
+
#endif /* ARCH_FEATURES_H */