feat(ls64): add LS64_ACCDATA test
FEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value
replacing the first four bytes of the data provided to an ST64BV0
instruction. As this system register would need context switching
between non-secure and secure worlds, there is an SCR_EL3 bit to allow
trapping accesses from lower ELs into EL3.
Introduce a check to verify that accesses to this system register do not
trap into EL3, if the CPUID registers advertise this feature.
Bits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits
when comparing the read-back values with the written one.
Change-Id: Ia32bcf7187356c701470a1757708b3d554e88629
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/tftf/tests/extensions/ls64/test_ls64.c b/tftf/tests/extensions/ls64/test_ls64.c
index b7074ab..1f2fad7 100644
--- a/tftf/tests/extensions/ls64/test_ls64.c
+++ b/tftf/tests/extensions/ls64/test_ls64.c
@@ -64,7 +64,6 @@
return TEST_RESULT_SUCCESS;
#else
- /* Skip test if AArch32 */
SKIP_TEST_IF_AARCH32();
#endif /* __aarch64_ */
#else
@@ -73,3 +72,28 @@
#endif /* PLAT_fvp */
}
+
+/*
+ * @brief Test LS64_ACCDATA feature support when the extension is enabled.
+ *
+ * Write to the ACCDATA_EL1 system register, and read it back. This is
+ * primarily to see if accesses to this register trap to EL3 (they should not).
+ *
+ * @return test_result_t
+ */
+test_result_t test_ls64_accdata_sysreg(void)
+{
+#ifdef __aarch64__
+ SKIP_TEST_IF_LS64_ACCDATA_NOT_SUPPORTED();
+
+ write_sys_accdata_el1(0x1234567890);
+ if ((read_sys_accdata_el1() & 0xffffffff) != 0x34567890) {
+ NOTICE("SYS_ACCDATA_EL1: 0x%lx\n", read_sys_accdata_el1());
+ return TEST_RESULT_FAIL;
+ }
+
+ return TEST_RESULT_SUCCESS;
+#else
+ SKIP_TEST_IF_AARCH32();
+#endif /* __aarch64_ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 62bb9ea..34ac0b6 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -38,6 +38,7 @@
<testcase name="PMUv3 event counter functional in NS" function="test_pmuv3_event_works_ns" />
<testcase name="PMUv3 SMC counter preservation" function="test_pmuv3_el3_preserves" />
<testcase name="LS64 support" function="test_ls64_instructions" />
+ <testcase name="LS64-ACCDATA support" function="test_ls64_accdata_sysreg" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">