Merge changes from topic "el3_direct_msg"
* changes:
feat: use x0-x17 for ff-a calls
test: add discovery of el3 spmd logical partitions
feat(ff-a): partition information via registers
diff --git a/Makefile b/Makefile
index 0a1ae9e..97afc34 100644
--- a/Makefile
+++ b/Makefile
@@ -234,7 +234,7 @@
# the options defined in the Makefile
COMMON_CFLAGS += ${CFLAGS} ${INCLUDES}
-COMMON_LDFLAGS += --fatal-warnings -O1 --gc-sections --build-id=none
+COMMON_LDFLAGS += ${LDFLAGS} --fatal-warnings -O1 --gc-sections --build-id=none
CC := ${CROSS_COMPILE}gcc
CPP := ${CROSS_COMPILE}cpp
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 2d85f65..f7cf3de 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -22,4 +22,26 @@
--------------
+Code owners
+-----------
+
+Platform Ports
+~~~~~~~~~~~~~~
+
+Xilinx platform port
+^^^^^^^^^^^^^^^^^^^^
+:|M|: Michal Simek <michal.simek@amd.com>
+:|G|: `michalsimek`_
+:|M|: Amit Nagal <amit.nagal@amd.com>
+:|G|: `amit-nagal`_
+:|M|: Akshay Belsare <akshay.belsare@amd.com>
+:|G|: `Akshay-Belsare`_
+:|F|: plat/xilinx\*
+:|F|: tftf/tests/plat/xilinx\*
+:|F|: docs/plat/xilinx-\*
+:|F|: tftf/tests/tests-versal.mk
+:|F|: tftf/tests/tests-versal.xml
+
+--------------
+
*Copyright (c) 2018-2020, Arm Limited. All rights reserved.*
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
new file mode 100644
index 0000000..1fff22f
--- /dev/null
+++ b/docs/plat/xilinx-versal.rst
@@ -0,0 +1,53 @@
+..
+ Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. !
+
+ SPDX-License-Identifier: BSD-3-Clause !
+
+
+Xilinx Versal
+=============
+
+- The TF-A Tests on Xilinx Versal platfrom runs from DDR.
+- Logs are available only on console and not saved in memory(No NVM support).
+- Versal Platform uses TTC Timer
+
+
+Build Command
+-------------
+For individual tests/test suite:
+
+.. code-block:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=versal TESTS=<required tests> tftf
+
+For Versal Specific tests (includes AMD-Xilinx Tests cases + Standard Test Suite)
+
+.. code-block:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=versal TESTS=versal tftf
+
+Execution on Target
+-------------------
+
+- The TF-A Tests uses the memory location of U-boot.
+- To package the tftf.elf in BOOT.BIN, the u-boot entry in bootgen.bif needs to be replaced with following
+
+.. code-block:: shell
+
+ the_ROM_image:
+ {
+ image {
+ { type=bootimage, file=project-spec/hw-description/vpl_gen_fixed.pdi }
+ { type=bootloader, file=plm.elf }
+ { core=psm, file=psmfw.elf }
+ }
+ image {
+ id = 0x1c000000, name=apu_subsystem
+ { type=raw, load=0x00001000, file=system-default.dtb }
+ { core=a72-0, exception_level=el-3, trustzone, file=bl31.elf }
+ { core=a72-0, file=tftf.elf }
+ }
+ }
+
+- The BOOT.BIN with TF-A Tests can now be used to run on the target.
+- The TF-A Tests will be executed after TF-A and the tests report will be available on the console.
diff --git a/plat/xilinx/versal/aarch64/plat_helpers.S b/plat/xilinx/versal/aarch64/plat_helpers.S
new file mode 100644
index 0000000..b8f1109
--- /dev/null
+++ b/plat/xilinx/versal/aarch64/plat_helpers.S
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .global platform_get_core_pos
+ .global plat_crash_console_init
+ .global plat_crash_console_flush
+ .global plat_crash_console_putc
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(u_register_t mpid)
+ *
+ * Function to calculate the core position.
+ *
+ * clobbers: x0 - x3
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+ /* x1 = core-id inside cluster */
+ ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ /* x2 = cluster-id */
+ ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* core-position = cluster-id * cores per cluster + core-id */
+ mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER
+ madd x0, x2, x3, x1
+ ret
+endfunc platform_get_core_pos
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, CRASH_CONSOLE_BASE
+ mov_imm x1, PL011_UART_CLK_IN_HZ
+ mov_imm x2, PL011_BAUDRATE
+ b console_core_init
+endfunc plat_crash_console_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, CRASH_CONSOLE_BASE
+ b console_core_putc
+endfunc plat_crash_console_putc
+
+ /* ---------------------------------------------
+ * int plat_crash_console_flush()
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0 - r1
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+ mov_imm x1, CRASH_CONSOLE_BASE
+ b console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
new file mode 100644
index 0000000..dbc6845
--- /dev/null
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define TFTF_BASE U(0x8000000)
+
+#define CACHE_WRITEBACK_GRANULE U(0x40)
+
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CORE_COUNT_PER_CLUSTER 2
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
+ PLATFORM_CORE_COUNT_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \
+ PLATFORM_CLUSTER_COUNT + 1)
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_STATES_PER_LVL 2
+
+
+#define PLATFORM_STACK_SIZE U(0x880)
+#define PCPU_DV_MEM_STACK_SIZE U(0x440)
+
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_XLAT_TABLES U(8)
+#define MAX_MMAP_REGIONS U(16)
+
+#define DRAM_BASE U(0x0)
+#define DRAM_SIZE U(0x80000000)
+
+/*
+ * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition
+ * table
+ */
+#define TFTF_NVM_SIZE U(0x600000)
+#define TFTF_NVM_OFFSET U(0x20000000)
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH U(4)
+
+/* GIC-400 related addresses from datasheet */
+#define GICD_REG_BASE U(0xf9000000)
+#define GICC_REG_BASE U(0xf9040000)
+#define GICR_REG_BASE U(0xf9080000)
+
+/*
+ * Memory mapped devices that we must create MMU mappings for them
+ */
+#define GIC_BASE GICD_REG_BASE
+#define GIC_SIZE U(0x01000000)
+
+#define TTC_BASE U(0xff0e0000)
+#define TTC_SIZE U(0x00010000)
+
+#define SYS_CNT_BASE1 TTC_BASE
+#define SYS_CNT_SIZE TTC_SIZE
+
+#define LPD_IOU_SLCR U(0xff080000)
+#define LPD_IOU_SLCR_SIZE U(0x00010000)
+
+/* ARM PL011 UART */
+#define PL011_UART0_BASE U(0xff000000)
+#define PL011_BAUDRATE U(115200)
+#define PL011_UART_CLK_IN_HZ U(100000000)
+
+#define PLAT_ARM_UART_BASE PL011_UART0_BASE
+#define PLAT_ARM_UART_SIZE U(0x1000)
+
+#define CRASH_CONSOLE_BASE PL011_UART0_BASE
+#define CRASH_CONSOLE_SIZE PLAT_ARM_UART_SIZE
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interrupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0 0
+#define IRQ_NS_SGI_1 1
+#define IRQ_NS_SGI_2 2
+#define IRQ_NS_SGI_3 3
+#define IRQ_NS_SGI_4 4
+#define IRQ_NS_SGI_5 5
+#define IRQ_NS_SGI_6 6
+#define IRQ_NS_SGI_7 7
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER U(29)
+/* Datasheet: TIME00 event*/
+#define IRQ_CNTPSIRQ1 U(29)
+
+/* Refer to AM011(v1.5), Chapter 50, Page 430 */
+#define PLAT_MAX_SPI_OFFSET_ID U(223)
+
+/*
+ * Times(in ms) used by test code for completion of different events.
+ */
+#define PLAT_SUSPEND_ENTRY_TIME U(15)
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30)
+
+/*
+ * Dummy definitions that we need just to compile...
+ */
+#define ARM_SECURE_SERVICE_BUFFER_BASE U(0)
+#define ARM_SECURE_SERVICE_BUFFER_SIZE U(100)
+
+/* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */
+#define IRQ_TWDOG_INTID U(0x51)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
new file mode 100644
index 0000000..264ed3c
--- /dev/null
+++ b/plat/xilinx/versal/platform.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+VERSAL_PATH := plat/xilinx/versal
+
+PLAT_INCLUDES := -I${VERSAL_PATH}/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
+ drivers/arm/gic/gic_common.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S \
+ drivers/arm/timer/private_timer.c \
+ drivers/console/console.c \
+ ${VERSAL_PATH}/versal_setup.c \
+ ${VERSAL_PATH}/versal_pwr_state.c \
+ ${VERSAL_PATH}/aarch64/plat_helpers.S \
+ ${VERSAL_PATH}/timers.c
+
+PLAT_TESTS_SKIP_LIST := ${VERSAL_PATH}/tests_to_skip.txt
+
+ifeq ($(USE_NVM),1)
+$(error "Versal port of TFTF doesn't currently support USE_NVM=1")
+endif
diff --git a/plat/xilinx/versal/tests_to_skip.txt b/plat/xilinx/versal/tests_to_skip.txt
new file mode 100644
index 0000000..8d8bc7c
--- /dev/null
+++ b/plat/xilinx/versal/tests_to_skip.txt
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+################################################################################
+# Disable the listed tests for Versal Platform.
+################################################################################
+
+#TESTS: tftf-validation
+Framework Validation/Events API
+Timer framework Validation/Target timer to a power down cpu
+Timer framework Validation/Test scenario where multiple CPUs call same timeout
+
+#TESTS: psci
+PSCI Affinity Info/Affinity info level0 powerdown
+PSCI CPU Suspend/CPU suspend to powerdown at level 0
+PSCI CPU Suspend/CPU suspend to powerdown at level 1
+PSCI CPU Suspend/CPU suspend to powerdown at level 2
+PSCI CPU Suspend/CPU suspend to standby at level 0
+PSCI CPU Suspend/CPU suspend to standby at level 1
+PSCI CPU Suspend/CPU suspend to standby at level 2
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+CPU Hotplug/Invalid entry point
+PSCI System Suspend Validation/System suspend multiple times
+PSCI System Suspend Validation/system suspend from all cores
+PSCI System Suspend Validation/Validate suspend to RAM functionality
+
+#TESTS: el3-power-state
+EL3 power state parser validation/Create all power states and validate EL3 power state parsing
+EL3 power state parser validation/Create invalid local power state at all levels and validate EL3 power state parsing
+EL3 power state parser validation/Create invalid power state type and validate EL3 power state parsing
+EL3 power state parser validation/Create a power state with valid and invalid local state ID at different levels and validate power state parsing
+
+#TESTS: psci-extensive
+PSCI CPU ON OFF Stress Tests/PSCI CPU ON OFF stress test
+PSCI CPU ON OFF Stress Tests/Repeated hotplug of all cores to stress test CPU_ON and CPU_OFF
+PSCI CPU ON OFF Stress Tests/Random hotplug cores in a large iteration to stress boot path code
diff --git a/plat/xilinx/versal/timers.c b/plat/xilinx/versal/timers.c
new file mode 100644
index 0000000..5c1e8f5
--- /dev/null
+++ b/plat/xilinx/versal/timers.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+
+#include <debug.h>
+#include <mmio.h>
+#include <platform.h>
+#include <tftf_lib.h>
+#include <timer.h>
+#include <utils_def.h>
+
+#define TTC_OFFSET_TMR_0 U(0)
+#define TTC_OFFSET_TMR_1 U(4)
+#define TTC_OFFSET_TMR_2 U(8)
+
+#define TTC_CLK_CNTRL_OFFSET U(0x00) /* Clock Control Reg, RW */
+#define TTC_CNT_CNTRL_OFFSET U(0x0C) /* Counter Control Reg, RW */
+#define TTC_COUNT_VAL_OFFSET U(0x18) /* Counter Value Reg, RO */
+#define TTC_INTR_VAL_OFFSET U(0x24) /* Interval Count Reg, RW */
+#define TTC_ISR_OFFSET U(0x54) /* Interrupt Status Reg, RO */
+#define TTC_IER_OFFSET U(0x60) /* Interrupt Enable Reg, RW */
+
+#define TTC_CNT_CNTRL_DISABLE_MASK BIT(0)
+
+#define TTC_CLK_SEL_OFFSET U(0x360)
+#define TTC_CLK_SEL_MASK GENMASK(1, 0)
+
+#define TTC_CLK_SEL_PS_REF BIT(0)
+#define TTC_CLK_SEL_RPU_REF BIT(4)
+
+#define TIMER_IRQ U(69)
+
+#define RET_SUCCESS U(0)
+
+/*
+ * Setup the timers to use pre-scaling, using a fixed value for now that will
+ * work across most input frequency, but it may need to be more dynamic
+ */
+#define PRESCALE_EXPONENT U(16) /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
+#define PRESCALE U(65536) /* The exponent must match this */
+#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1U)
+#define CLK_CNTRL_PRESCALE_EN BIT(0)
+#define CNT_CNTRL_RESET BIT(4)
+
+/* Resolution obtained as per the input clock and Prescale value
+ * Clock Selected : PS_REF_CLK
+ * Clock Value : 33333333Hz (33.33MHz)
+ * Prescalar for TTC, N : 15 (highest)
+ * Prescalar Applied 2^(N+1) : 65536
+ * Input clock : (PS_REF_CLK)/Prescalar) : 508.6263Hz
+ * Resolution (1/InputClock) : 1.966miliseconds ~2ms
+ */
+const unsigned long INTERVAL = 2;
+
+static void timer_write_32(uint32_t offset, uint32_t val)
+{
+ /* actual write */
+ mmio_write_32(SYS_CNT_BASE1 + offset, val);
+}
+
+static uint32_t timer_read_32(uint32_t offset)
+{
+ /* actual read */
+ return mmio_read_32(SYS_CNT_BASE1 + offset);
+}
+
+static int cancel_timer(void)
+{
+ /* Disable Interrupt */
+ timer_write_32(TTC_IER_OFFSET, 0);
+
+ /* Disable Counter */
+ timer_write_32(TTC_CLK_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
+
+ return RET_SUCCESS;
+}
+
+static void clocksetup(void)
+{
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CLK_CNTRL_OFFSET, 0x0);
+
+ mmio_write_32(LPD_IOU_SLCR + TTC_CLK_SEL_OFFSET, TTC_CLK_SEL_PS_REF);
+
+ VERBOSE("%s TTC_CLK_SEL = 0x%x\n", __func__,
+ mmio_read_32(LPD_IOU_SLCR + TTC_CLK_SEL_OFFSET));
+}
+
+static void setcounts(unsigned long time_out_ms)
+{
+ unsigned long intrvl = (time_out_ms / INTERVAL) + (time_out_ms % INTERVAL);
+
+ timer_write_32(TTC_INTR_VAL_OFFSET, intrvl);
+}
+
+static int program_timer(unsigned long time_out_ms)
+{
+ uint32_t reg;
+
+ /* Disable and program the counter */
+ reg = timer_read_32(TTC_CNT_CNTRL_OFFSET);
+ reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, reg);
+
+ setcounts(time_out_ms);
+
+ /* Enable the interrupt */
+ timer_write_32(TTC_IER_OFFSET, 0x01);
+
+ /* Enable the counter */
+ reg |= CNT_CNTRL_RESET;
+ reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, reg);
+
+ return RET_SUCCESS;
+}
+
+static int handler_timer(void)
+{
+ uint32_t status;
+
+ /* Disable the interrupts */
+ timer_write_32(TTC_IER_OFFSET, 0x00);
+
+ status = timer_read_32(TTC_ISR_OFFSET);
+ if (status & 0x1)
+ INFO("Timer Event! %x\n", status);
+ else
+ ERROR("Its not a Timer Event %d\n", status);
+
+ return RET_SUCCESS;
+}
+
+static const plat_timer_t versal_timers = {
+ .program = program_timer,
+ .cancel = cancel_timer,
+ .handler = handler_timer,
+ .timer_step_value = INTERVAL,
+ .timer_irq = TIMER_IRQ
+};
+
+int plat_initialise_timer_ops(const plat_timer_t **timer_ops)
+{
+ assert(timer_ops != NULL);
+
+ /* Disable all Interrupts on the TTC */
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_IER_OFFSET, 0);
+ timer_write_32(TTC_OFFSET_TMR_1 + TTC_IER_OFFSET, 0);
+ timer_write_32(TTC_OFFSET_TMR_2 + TTC_IER_OFFSET, 0);
+
+ clocksetup();
+
+ /*
+ * Setup the clock event timer to be an interval timer which
+ * is prescaled by 32 using the interval interrupt. Leave it
+ * disabled for now.
+ */
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CNT_CNTRL_OFFSET, 0x23);
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CLK_CNTRL_OFFSET,
+ CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN);
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_IER_OFFSET, 0x01);
+
+ *timer_ops = &versal_timers;
+
+ return RET_SUCCESS;
+}
diff --git a/plat/xilinx/versal/versal_pwr_state.c b/plat/xilinx/versal/versal_pwr_state.c
new file mode 100644
index 0000000..74c43c0
--- /dev/null
+++ b/plat/xilinx/versal/versal_pwr_state.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+
+/*
+ * State IDs for local power states.
+ */
+#define VERSAL_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define VERSAL_OFF_STATE_ID 0 /* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+ VERSAL_RUN_DEPTH = 0,
+ VERSAL_RETENTION_DEPTH,
+ VERSAL_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {VERSAL_RETENTION_DEPTH, VERSAL_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+ {VERSAL_OFF_DEPTH, VERSAL_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+ {VERSAL_OFF_DEPTH, VERSAL_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the system level */
+static const plat_state_prop_t system_state_prop[] = {
+ {VERSAL_OFF_DEPTH, VERSAL_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return cluster_state_prop;
+ case MPIDR_AFFLVL2:
+ return system_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/xilinx/versal/versal_setup.c b/plat/xilinx/versal/versal_setup.c
new file mode 100644
index 0000000..35589ab
--- /dev/null
+++ b/plat/xilinx/versal/versal_setup.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <drivers/arm/arm_gic.h>
+#include <drivers/console.h>
+#include <platform.h>
+#include <tftf_lib.h>
+
+#include <platform_def.h>
+
+static const struct {
+ unsigned int cluster_id;
+ unsigned int cpu_id;
+} versal_cores[PLATFORM_CORE_COUNT] = {
+ { 0, 0 },
+ { 0, 1 }
+};
+
+static const mmap_region_t mmap[] = {
+ MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(CRASH_CONSOLE_BASE, CRASH_CONSOLE_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(TTC_BASE, TTC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(LPD_IOU_SLCR, LPD_IOU_SLCR_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ {0}
+};
+
+/* Power Domain Tree Descriptor array */
+const unsigned char versal_pwr_tree_desc[] = {
+ /* Number of root nodes */
+ 1,
+ /* Number of clusters */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER
+};
+
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return versal_pwr_tree_desc;
+}
+
+/*
+ * Generate the MPID from the core position.
+ */
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ return (uint64_t)make_mpid(versal_cores[core_pos].cluster_id,
+ versal_cores[core_pos].cpu_id);
+}
+
+void tftf_plat_arch_setup(void)
+{
+ tftf_plat_configure_mmu();
+}
+
+void tftf_early_platform_setup(void)
+{
+ console_init(CRASH_CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
+}
+
+void tftf_platform_setup(void)
+{
+ arm_gic_init(GICC_REG_BASE, GICD_REG_BASE, GICR_REG_BASE);
+ arm_gic_setup_global();
+ arm_gic_setup_local();
+}
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+ return mmap;
+}
diff --git a/tftf/tests/plat/xilinx/common/plat_pm.c b/tftf/tests/plat/xilinx/common/plat_pm.c
new file mode 100644
index 0000000..7f43824
--- /dev/null
+++ b/tftf/tests/plat/xilinx/common/plat_pm.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <smccc.h>
+#include <tftf_lib.h>
+
+#include <platform_def.h>
+
+/* Number of 32bits values in payload */
+#define PAYLOAD_ARG_CNT 4U
+
+#define upper_32_bits(n) ((uint32_t)(((n) >> 32)))
+#define lower_32_bits(n) ((uint32_t)((n) & 0xffffffff))
+
+
+#define PM_GET_API_VERSION 0xC2000001
+#define PM_GET_CHIPID 0xC2000018
+
+
+/*
+ * @Test_Aim@ Test to read the PM-API version from AMD-Xilinx platform
+ * This test run on lead CPU and issues PM_GET_API_VERSION SMC call to read the
+ * supported PM-API version on the platform.
+ * Return vslues are packed as
+ * ret.ret0(31:0) : actual return value
+ * ret.ret0(63:32) : Return arg1
+ * ret.ret1(31:0) : Return arg2
+ * ret.ret1(63:32) : Return arg3 and so on.
+ */
+test_result_t test_pmapi_version(void)
+{
+ smc_args args = { PM_GET_API_VERSION };
+ smc_ret_values ret;
+ uint32_t major, minor, status;
+
+ ret = tftf_smc(&args);
+ status = lower_32_bits(ret.ret0);
+ if (status) {
+ tftf_testcase_printf("%s ERROR Reading PM-API Version\n",
+ __func__);
+ return TEST_RESULT_FAIL;
+ }
+
+ major = upper_32_bits(ret.ret0) >> 16;
+ minor = upper_32_bits(ret.ret0) & 0xFFFF;
+
+ tftf_testcase_printf("%s PM-API Version : %d.%d\n", __func__,
+ major, minor);
+ return TEST_RESULT_SUCCESS;
+}
+
+/*
+ * @Test_Aim@ Test to read the Chip ID of AMD-Xilinx platforms.
+ * This test runs on Lead CPU and issues PM_GET_CHIPID SMC call to read ChipID
+ * The IDcode and version is printed
+ * Return vslues are packed as
+ * ret.ret0(31:0) : actual return value
+ * ret.ret0(63:32) : Return arg1
+ * ret.ret1(31:0) : Return arg2
+ * ret.ret1(63:32) : Return arg3 and so on.
+ */
+test_result_t test_get_chipid(void)
+{
+ smc_args args = { PM_GET_CHIPID };
+ smc_ret_values ret;
+ uint32_t idcode, version, status;
+
+ ret = tftf_smc(&args);
+ status = lower_32_bits(ret.ret0);
+ if (status) {
+ tftf_testcase_printf("%s ERROR Reading Chip ID\n", __func__);
+ return TEST_RESULT_FAIL;
+ }
+
+ idcode = upper_32_bits(ret.ret0);
+ version = lower_32_bits(ret.ret1);
+
+ tftf_testcase_printf("%s Idcode = 0x%x Version = 0x%x\n", __func__,
+ idcode, version);
+
+ return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/tests-versal.mk b/tftf/tests/tests-versal.mk
new file mode 100644
index 0000000..6717ee5
--- /dev/null
+++ b/tftf/tests/tests-versal.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+TESTS_SOURCES += $(addprefix tftf/tests/plat/xilinx/common/, \
+ plat_pm.c \
+)
+
+
+include tftf/tests/tests-standard.mk
+TESTS_SOURCES += $(sort ${TESTS_SOURCES})
diff --git a/tftf/tests/tests-versal.xml b/tftf/tests/tests-versal.xml
new file mode 100644
index 0000000..6c8f519
--- /dev/null
+++ b/tftf/tests/tests-versal.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+ Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+
+ SPDX-License-Identifier: BSD-3-Clause
+-->
+
+<document>
+ <!-- External reference to standard tests files. -->
+ <xi:include xmlns:xi="http://www.w3.org/2001/XInclude" href="tests-standard.xml" />
+ <testsuites>
+
+ <testsuite name="AMD-Xilinx tests" description="AMD-Xilinx common platform tests" >
+ <testcase name="Read PM API Version" function="test_pmapi_version" />
+ <testcase name="Get Platform Chip ID" function="test_get_chipid" />
+ </testsuite>
+
+ </testsuites>
+</document>
diff --git a/tools/generate_json/generate_json.sh b/tools/generate_json/generate_json.sh
index 9ac13ec..5867700 100755
--- a/tools/generate_json/generate_json.sh
+++ b/tools/generate_json/generate_json.sh
@@ -25,69 +25,83 @@
IVY_PRESENT=false
IVY_SHIM_PRESENT=false
-for target in "$@"
-do
+for target in "$@"; do
case $target in
- cactus)
- CACTUS_PRESENT=true
- ;;
- ivy)
- IVY_PRESENT=true
- ;;
- ivy_shim)
- IVY_SHIM_PRESENT=true
- ;;
- *)
- echo "Invalid target $target"
- exit 1
- ;;
+ cactus) CACTUS_PRESENT=true ;;
+ ivy) IVY_PRESENT=true ;;
+ ivy_shim) IVY_SHIM_PRESENT=true ;;
+ *) echo "Invalid target $target"; exit 1 ;;
esac
done
-echo -e "{" > $GENERATED_JSON
+echo -e "{" > "$GENERATED_JSON"
# To demonstrate communication between SP's, two cactus S-EL1 instances used.
# To also test mapping of the RXTX region a third cactus S-EL1 instance is used.
# cactus-primary, cactus-secondary and cactus-tertiary have same binary but
# different partition manifests.
if [ $CACTUS_PRESENT == "true" ]; then
- echo -ne "\t\"cactus-primary\" : {\n \
- \t\"image\": {\n \
- \t\t\"file\": \"cactus.bin\",\n \
- \t\t\"offset\":\"0x2000\"\n\
- \t},\n \
- \t\"pm\": {\n \
- \t\t\"file\": \"cactus.dts\",\n \
- \t\t\"offset\":\"0x1000\"\n\
- \t},\n
- \t\"owner\": \"SiP\"\n\t},\n\n\t\"cactus-secondary\" : {\n \
- \t\"image\": \"cactus.bin\",\n \
- \t\"pm\": \"cactus-secondary.dts\",\n \
- \t\"owner\": \"Plat\"\n\t},\n\n\t\"cactus-tertiary\" : {\n \
- \t\"image\": \"cactus.bin\",\n \
- \t\"pm\": \"cactus-tertiary.dts\",\n \
- \t\"owner\": \"Plat\"\n\t}" \
- >> "$GENERATED_JSON"
+ cat >> "$GENERATED_JSON" << EOF
+"cactus-primary" : {
+ "image": {
+ "file": "cactus.bin",
+ "offset":"0x2000"
+ },
+ "pm": {
+ "file": "cactus.dts",
+ "offset": "0x1000"
+ },
+ "physical-load-address": "0x7000000",
+ "owner": "SiP"
+},
+
+"cactus-secondary" : {
+ "image": "cactus.bin",
+ "pm": "cactus-secondary.dts",
+ "physical-load-address": "0x7100000",
+ "owner": "Plat"
+},
+
+"cactus-tertiary" : {
+ "image": "cactus.bin",
+ "pm": "cactus-tertiary.dts",
+ "physical-load-address": "0x7200000",
+ "owner": "Plat"
+EOF
PARTITION_ALREADY_PRESENT=true
fi
+
if [ $IVY_PRESENT == "true" ]; then
if [ $PARTITION_ALREADY_PRESENT == "true" ]; then
- echo -ne ",\n\n" >> $GENERATED_JSON
+ echo -ne "\t},\n\n" >> "$GENERATED_JSON"
fi
- echo -ne "\t\"ivy\" : {\n \
- \t\"image\": \"ivy.bin\",\n \
- \t\"pm\": \"ivy-sel0.dts\",\n \
- \t\"owner\": \"Plat\"\n\t}" >> "$GENERATED_JSON"
+
+ cat >> "$GENERATED_JSON" << EOF
+"ivy" : {
+ "image": "ivy.bin",
+ "pm": "ivy-sel0.dts",
+ "physical-load-address": "0x7600000",
+ "owner": "Plat"
+}
+EOF
+
PARTITION_ALREADY_PRESENT=true
elif [ $IVY_SHIM_PRESENT == "true" ]; then
if [ $PARTITION_ALREADY_PRESENT == "true" ]; then
- echo -ne ",\n\n" >> $GENERATED_JSON
+ echo -ne "\t},\n\n" >> "$GENERATED_JSON"
fi
- echo -ne "\t\"ivy\" : {\n \
- \t\"image\": \"ivy.bin\",\n \
- \t\"pm\": \"ivy-sel1.dts\",\n \
- \t\"owner\": \"Plat\"\n\t}" >> "$GENERATED_JSON"
+cat >> "$GENERATED_JSON" << EOF
+"ivy" : {
+ "image": "ivy.bin",
+ "pm": "ivy-sel1.dts",
+ "physical-load-address": "0x7600000",
+ "owner": "Plat"
+}
+EOF
+
PARTITION_ALREADY_PRESENT=true
+else
+ echo -ne "\t},\n" >> "$GENERATED_JSON"
fi
echo -e "\n}" >> "$GENERATED_JSON"