diff --git a/include/runtime_services/errata_abi.h b/include/runtime_services/errata_abi.h
index dc50113..78c739f 100644
--- a/include/runtime_services/errata_abi.h
+++ b/include/runtime_services/errata_abi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -49,6 +49,7 @@
 	int em_errata_id;
 	unsigned int rxpx_low;
 	unsigned int rxpx_high;
+	unsigned int split_wa;
 } em_cpu_errata_t;
 
 typedef struct em_cpu{
diff --git a/include/runtime_services/host_realm_managment/host_realm_helper.h b/include/runtime_services/host_realm_managment/host_realm_helper.h
index e27cfd5..af8f834 100644
--- a/include/runtime_services/host_realm_managment/host_realm_helper.h
+++ b/include/runtime_services/host_realm_managment/host_realm_helper.h
@@ -61,8 +61,29 @@
  * This functions sets the shared data args needed for entering aux plane,
  * using REALM_ENTER_PLANE_N_CMD
  */
-void host_realm_set_aux_plane_args(struct realm *realm_ptr, unsigned int plane_num);
+void host_realm_set_aux_plane_args(struct realm *realm_ptr,
+		unsigned int plane_num, unsigned int rec_num);
 
+
+/* Function to check if Planes feature is supoprted */
+static inline bool are_planes_supported(void)
+{
+	u_register_t feature_flag;
+
+	/* Read Realm Feature Reg 0 */
+	if (host_rmi_features(0UL, &feature_flag) != REALM_SUCCESS) {
+		ERROR("%s() failed\n", "host_rmi_features");
+		return false;
+	}
+
+	if (EXTRACT(RMI_FEATURE_REGISTER_0_MAX_NUM_AUX_PLANES, feature_flag) > 0UL) {
+		return true;
+	}
+
+	return false;
+}
+
+/* Function to check if S2POE feature/ Single RTT is supported for multiple planes */
 static inline bool is_single_rtt_supported(void)
 {
 	u_register_t feature_flag;
diff --git a/include/runtime_services/host_realm_managment/host_shared_data.h b/include/runtime_services/host_realm_managment/host_shared_data.h
index 763306f..ead84f5 100644
--- a/include/runtime_services/host_realm_managment/host_shared_data.h
+++ b/include/runtime_services/host_realm_managment/host_shared_data.h
@@ -45,13 +45,16 @@
 enum realm_cmd {
 	REALM_SLEEP_CMD = 1U,
 	REALM_LOOP_CMD,
+	REALM_S2POE_ACCESS,
 	REALM_MPAM_ACCESS,
 	REALM_MPAM_PRESENT,
 	REALM_MULTIPLE_REC_PSCI_DENIED_CMD,
 	REALM_MULTIPLE_REC_MULTIPLE_CPU_CMD,
+	REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD,
 	REALM_GET_RSI_VERSION,
 	REALM_INSTR_FETCH_CMD,
 	REALM_DATA_ACCESS_CMD,
+	REALM_PLANE_N_EXCEPTION_CMD,
 	REALM_PMU_CYCLE,
 	REALM_PMU_COUNTER,
 	REALM_PMU_EVENT,
diff --git a/realm/include/realm_rsi.h b/realm/include/realm_rsi.h
index 06f857f..7139023 100644
--- a/realm/include/realm_rsi.h
+++ b/realm/include/realm_rsi.h
@@ -65,6 +65,8 @@
 	RSI_ERROR_COUNT
 } rsi_status_t;
 
+#define RSI_EXIT_SYNC	0U
+
 /* Size of Realm Personalization Value */
 #define RSI_RPV_SIZE			64U
 
diff --git a/realm/include/realm_tests.h b/realm/include/realm_tests.h
index 6c1e6c3..6f457e5 100644
--- a/realm/include/realm_tests.h
+++ b/realm/include/realm_tests.h
@@ -25,6 +25,7 @@
 bool test_realm_sve_undef_abort(void);
 bool test_realm_multiple_rec_psci_denied_cmd(void);
 bool test_realm_multiple_rec_multiple_cpu_cmd(void);
+bool test_realm_multiple_plane_multiple_rec_multiple_cpu_cmd(void);
 bool test_realm_sme_read_id_registers(void);
 bool test_realm_sme_undef_abort(void);
 bool test_realm_sctlr2_ease(void);
diff --git a/realm/realm_multiple_rec.c b/realm/realm_multiple_rec.c
index c584cd4..95bb6f1 100644
--- a/realm/realm_multiple_rec.c
+++ b/realm/realm_multiple_rec.c
@@ -15,18 +15,26 @@
 #include <host_shared_data.h>
 #include <psci.h>
 #include "realm_def.h"
+#include <realm_helpers.h>
+#include <realm_psi.h>
 #include <realm_rsi.h>
 #include <realm_tests.h>
 #include <realm_psci.h>
 #include <tftf_lib.h>
 
-#define CXT_ID_MAGIC 0x100
+#define CXT_ID_MAGIC	0x100
+#define P1_CXT_ID_MAGIC	0x200
+
 static uint64_t is_secondary_cpu_booted;
 static spinlock_t lock;
+static rsi_plane_run run[MAX_REC_COUNT] __aligned(PAGE_SIZE);
+static u_register_t base, plane_index, perm_index;
 
-static void rec1_handler(u_register_t cxt_id)
+static void plane0_recn_handler(u_register_t cxt_id)
 {
-	realm_printf("running on CPU = 0x%lx cxt_id= 0x%lx\n",
+	uint64_t rec = 0U;
+
+	realm_printf("running on Rec= 0x%lx cxt_id= 0x%lx\n",
 			read_mpidr_el1() & MPID_MASK, cxt_id);
 	if (cxt_id < CXT_ID_MAGIC || cxt_id > CXT_ID_MAGIC + MAX_REC_COUNT) {
 		realm_printf("Wrong cxt_id\n");
@@ -34,6 +42,35 @@
 	}
 	spin_lock(&lock);
 	is_secondary_cpu_booted++;
+	rec =  read_mpidr_el1() & MPID_MASK;
+	spin_unlock(&lock);
+
+	/* enter plane */
+	u_register_t flags = 0U;
+
+	/* Use Base adr, plane_index, perm_index programmed by P0 rec0 */
+	run[rec].enter.pc = base;
+	realm_printf("Entering plane %ld, ep=0x%lx rec=0x%lx\n", plane_index, base, rec);
+	realm_plane_enter(plane_index, perm_index, base, flags, &run[rec]);
+
+	if (run[rec].exit.gprs[0] == SMC_PSCI_CPU_OFF) {
+		realm_printf("Plane N did not request CPU OFF\n");
+		rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
+	}
+	realm_cpu_off();
+}
+
+static void recn_handler(u_register_t cxt_id)
+{
+	realm_printf("running on Rec= 0x%lx cxt_id= 0x%lx\n",
+			read_mpidr_el1() & MPID_MASK, cxt_id);
+
+	if (cxt_id < P1_CXT_ID_MAGIC || cxt_id > P1_CXT_ID_MAGIC + MAX_REC_COUNT) {
+		realm_printf("Wrong cxt_id\n");
+		rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
+	}
+	spin_lock(&lock);
+	is_secondary_cpu_booted++;
 	spin_unlock(&lock);
 	realm_cpu_off();
 }
@@ -48,7 +85,7 @@
 	u_register_t ret;
 
 	is_secondary_cpu_booted = 0U;
-	ret = realm_cpu_on(1U, (uintptr_t)rec1_handler, 0x100);
+	ret = realm_cpu_on(1U, (uintptr_t)recn_handler, 0x100);
 	if (ret != PSCI_E_DENIED) {
 		return false;
 	}
@@ -71,12 +108,106 @@
 	return true;
 }
 
+/*
+ * All Planes enter this test function.
+ * P0 Rec0 Enters Plane N
+ * Plane N rec 0 requests CPU ON for all other rec
+ * P0 Rec0 requests CPU ON to host
+ * Host enters P0 RecN from different CPU
+ * P0 RecN enters PlaneN RecN
+ * Rec N requests CPU OFF, exits to P0
+ * P0 requests CPU OFF to host.
+ * P0 verifies all other CPU are off.
+ */
+bool test_realm_multiple_plane_multiple_rec_multiple_cpu_cmd(void)
+{
+	unsigned int i = 1U, rec_count;
+	u_register_t ret;
+	bool ret1;
+
+	realm_printf("Realm: running on Rec= 0x%lx\n", read_mpidr_el1() & MPID_MASK);
+	rec_count = realm_shared_data_get_my_host_val(HOST_ARG3_INDEX);
+
+	/* Check CPU_ON is supported */
+	ret = realm_psci_features(SMC_PSCI_CPU_ON);
+	if (ret != PSCI_E_SUCCESS) {
+		realm_printf("SMC_PSCI_CPU_ON not supported\n");
+		return false;
+	}
+
+	if (realm_is_plane0()) {
+		/* Plane 0 all rec */
+		u_register_t flags = 0U;
+
+		plane_index = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
+		base = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
+		perm_index = plane_index + 1U;
+
+		plane_common_init(plane_index, perm_index, base, &run[0U]);
+
+		ret1 = realm_plane_enter(plane_index, perm_index, base, flags, &run[0U]);
+		while (ret1 && run->exit.gprs[0] == SMC_PSCI_CPU_ON_AARCH64) {
+			realm_printf("Plane N requested CPU on Rec=0x%lx\n", run[0].exit.gprs[1]);
+
+			/* Pass context tp RecN - CXT + rec idx */
+			run[0].enter.gprs[0] = realm_cpu_on(run[0].exit.gprs[1],
+						(uintptr_t)plane0_recn_handler,
+						CXT_ID_MAGIC + run[0].exit.gprs[1]);
+
+			/* re-enter plane N 1 to complete cpu on */
+			ret1 = realm_plane_enter(plane_index, perm_index, base, flags, &run[0U]);
+			if (!ret1) {
+				realm_printf("PlaneN CPU on complete failed\n");
+				rsi_exit_to_host(HOST_CALL_EXIT_FAILED_CMD);
+			}
+		}
+
+		/* wait for all CPUs to come up */
+		while (is_secondary_cpu_booted != rec_count - 1U) {
+			waitms(200);
+		}
+
+		/* wait for all CPUs to turn off */
+		while (i < rec_count) {
+			ret = realm_psci_affinity_info(i, MPIDR_AFFLVL0);
+			if (ret != PSCI_STATE_OFF) {
+				/* wait and query again */
+				realm_printf(" CPU %d is not off\n", i);
+				waitms(200);
+				continue;
+			}
+			i++;
+		}
+		realm_printf("All CPU are off\n");
+		return true;
+	} else {
+		/* Plane 1 Rec 0 */
+		for (unsigned int j = 1U; j < rec_count; j++) {
+			realm_printf("CPU ON Rec=%u\n", j);
+			ret = realm_cpu_on(j, (uintptr_t)recn_handler, P1_CXT_ID_MAGIC + j);
+			if (ret != PSCI_E_SUCCESS) {
+				realm_printf("SMC_PSCI_CPU_ON failed %d.\n", j);
+				return false;
+			}
+		}
+		/* Exit to Host to allow host to run all CPUs */
+		rsi_exit_to_host(HOST_CALL_EXIT_SUCCESS_CMD);
+
+		/* wait for all CPUs to come up */
+		while (is_secondary_cpu_booted != rec_count - 1U) {
+			waitms(200);
+		}
+		return true;
+	}
+	return true;
+}
+
 bool test_realm_multiple_rec_multiple_cpu_cmd(void)
 {
 	unsigned int i = 1U, rec_count;
 	u_register_t ret;
 
-	realm_printf("Realm: running on CPU = 0x%lx\n", read_mpidr_el1() & MPID_MASK);
+	realm_printf("Realm: running on Rec= 0x%lx\n", read_mpidr_el1() & MPID_MASK);
 	rec_count = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
 
 	/* Check CPU_ON is supported */
@@ -87,7 +218,7 @@
 	}
 
 	for (unsigned int j = 1U; j < rec_count; j++) {
-		ret = realm_cpu_on(j, (uintptr_t)rec1_handler, CXT_ID_MAGIC + j);
+		ret = realm_cpu_on(j, (uintptr_t)recn_handler, P1_CXT_ID_MAGIC + j);
 		if (ret != PSCI_E_SUCCESS) {
 			realm_printf("SMC_PSCI_CPU_ON failed %d.\n", j);
 			return false;
diff --git a/realm/realm_payload_main.c b/realm/realm_payload_main.c
index d364aa0..4ebdb90 100644
--- a/realm/realm_payload_main.c
+++ b/realm/realm_payload_main.c
@@ -144,6 +144,18 @@
 	}
 }
 
+static bool test_realm_s2poe_undef_abort(void)
+{
+	realm_reset_undef_abort_count();
+
+	/* Install exception handler to catch undefined abort */
+	register_custom_sync_exception_handler(realm_sync_exception_handler);
+	write_s2por_el1(0UL);
+	unregister_custom_sync_exception_handler();
+
+	return (realm_get_undef_abort_count() != 0UL);
+}
+
 /*
  * This function requests RSI/ABI version from RMM.
  */
@@ -253,17 +265,57 @@
 	return false;
 }
 
+static bool test_plane_exception_cmd(void)
+{
+	u_register_t base, plane_index, perm_index, flags = 0U;
+	bool ret1;
+
+	plane_index = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
+	base = realm_shared_data_get_my_host_val(HOST_ARG2_INDEX);
+	perm_index = plane_index + 1U;
+
+	ret1 = plane_common_init(plane_index, perm_index, base, &run);
+	if (!ret1) {
+		return ret1;
+	}
+
+	realm_printf("Entering plane %ld, ep=0x%lx run=0x%lx\n", plane_index, base, &run);
+	ret1 = realm_plane_enter(plane_index, perm_index, base, flags, &run);
+
+	realm_printf("Plane exit reason=0x%lx\n", run.exit.exit_reason);
+
+	/*
+	 * @TODO- P0 can inject SEA back to PN,
+	 * if capability is added in future.
+	 */
+	if (ret1 && (run.exit.exit_reason == RSI_EXIT_SYNC)) {
+		u_register_t far, esr, elr;
+
+		far = run.exit.far;
+		esr = run.exit.esr;
+		elr = run.exit.elr;
+
+		/* Return ESR FAR to Host */
+		realm_shared_data_set_my_realm_val(HOST_ARG2_INDEX, esr);
+		realm_shared_data_set_my_realm_val(HOST_ARG3_INDEX, far);
+		realm_printf("Plane exit FAR=0x%lx ESR=0x%lx ELR=0x%lx\n",
+			far, esr, elr);
+		rsi_exit_to_host(HOST_CALL_EXIT_SUCCESS_CMD);
+	}
+	return false;
+}
+
 static bool test_realm_instr_fetch_cmd(void)
 {
 	u_register_t base, new_top;
 	void (*func_ptr)(void);
 	rsi_ripas_type ripas;
 
-	base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
+	base = realm_shared_data_get_my_host_val(HOST_ARG3_INDEX);
 	rsi_ipa_state_get(base, base + PAGE_SIZE, &new_top, &ripas);
 	realm_printf("Initial ripas=%u\n", ripas);
 	/* Causes instruction abort */
-	realm_printf("Generate Instruction Abort\n");
+	realm_printf("Generate Instruction Abort base=0x%lx\n", base);
 	func_ptr = (void (*)(void))base;
 	func_ptr();
 	/* Should not return */
@@ -274,11 +326,11 @@
 {
 	u_register_t base, new_top;
 	rsi_ripas_type ripas;
-	base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
+	base = realm_shared_data_get_my_host_val(HOST_ARG3_INDEX);
 	rsi_ipa_state_get(base, base + PAGE_SIZE, &new_top, &ripas);
 	realm_printf("Initial ripas=%u\n", ripas);
 	/* Causes data abort */
-	realm_printf("Generate Data Abort\n");
+	realm_printf("Generate Data Abort base=0x%lx\n", base);
 	*((volatile uint64_t *)base);
 
 	return false;
@@ -288,7 +340,7 @@
 {
 	u_register_t base, far, esr, elr;
 
-	base = realm_shared_data_get_my_host_val(HOST_ARG1_INDEX);
+	base = realm_shared_data_get_my_host_val(HOST_ARG3_INDEX);
 	far = read_far_el1();
 	esr = read_esr_el1();
 	elr = read_elr_el1();
@@ -390,6 +442,9 @@
 		case REALM_PLANE_N_REG_RW_CMD:
 			test_succeed = test_realm_enter_plane_n_reg_rw();
 			break;
+		case REALM_S2POE_ACCESS:
+			test_succeed = test_realm_s2poe_undef_abort();
+			break;
 		case REALM_MPAM_ACCESS:
 			test_succeed = test_realm_mpam_undef_abort();
 			break;
@@ -403,6 +458,9 @@
 		case REALM_MULTIPLE_REC_MULTIPLE_CPU_CMD:
 			test_succeed = test_realm_multiple_rec_multiple_cpu_cmd();
 			break;
+		case REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD:
+			test_succeed = test_realm_multiple_plane_multiple_rec_multiple_cpu_cmd();
+			break;
 		case REALM_FEAT_DOUBLEFAULT2_TEST:
 			test_realm_feat_doublefault2();
 			test_succeed = true;
@@ -413,6 +471,9 @@
 		case REALM_DATA_ACCESS_CMD:
 			test_succeed = test_realm_data_access_cmd();
 			break;
+		case REALM_PLANE_N_EXCEPTION_CMD:
+			test_succeed = test_plane_exception_cmd();
+			break;
 		case REALM_PAUTH_SET_CMD:
 			test_succeed = test_realm_pauth_set_cmd();
 			break;
diff --git a/realm/realm_plane.c b/realm/realm_plane.c
index c7225ed..656c688 100644
--- a/realm/realm_plane.c
+++ b/realm/realm_plane.c
@@ -11,12 +11,15 @@
 #include <debug.h>
 
 #include <host_realm_helper.h>
+#include <psci.h>
+#include <realm_psci.h>
 #include <realm_psi.h>
 #include <realm_rsi.h>
 #include <sync.h>
 
 static bool is_plane0;
 static unsigned int plane_num;
+static bool plane_init[MAX_PLANE_COUNT];
 
 bool realm_is_plane0(void)
 {
@@ -102,10 +105,30 @@
 
 	/* Disallow SMC from Plane N */
 	if (ec == EC_AARCH64_SMC) {
-		/* TODO Support PSCI in future */
+		u_register_t smc_id = run->exit.gprs[0];
+
 		restore_plane_context(run);
-		run->enter.gprs[0] = RSI_ERROR_STATE;
-		return PSI_RETURN_TO_PN;
+		switch (smc_id) {
+		case SMC_PSCI_CPU_ON_AARCH64:
+			assert(run->exit.gprs[1] < MAX_REC_COUNT);
+			assert(run->exit.gprs[1] != 0U);
+			/* Let P0 handle CPU ON */
+			return PSI_RETURN_TO_P0;
+		case SMC_PSCI_CPU_OFF:
+			realm_cpu_off();
+			/* Does not return. */
+			return PSI_RETURN_TO_PN;
+		case SMC_PSCI_FEATURES:
+			run->enter.gprs[0] = realm_psci_features(run->exit.gprs[1U]);
+			return PSI_RETURN_TO_PN;
+		case SMC_PSCI_AFFINITY_INFO:
+			run->enter.gprs[0] = realm_psci_affinity_info(run->exit.gprs[1U],
+					run->exit.gprs[2U]);
+			return PSI_RETURN_TO_PN;
+		default:
+			run->enter.gprs[0] = RSI_ERROR_STATE;
+			return PSI_RETURN_TO_PN;
+		}
 	}
 
 	/* Handle PSI HVC call from Plane N */
@@ -146,11 +169,16 @@
 	run->enter.pc = base;
 
 	/* Perm init */
+	if (plane_init[plane_index]) {
+		return true;
+	}
+
 	ret = rsi_mem_set_perm_value(plane_index, perm_index, PERM_LABEL_RW_upX);
 	if (ret != RSI_SUCCESS) {
 		ERROR("rsi_mem_set_perm_value failed %u\n", plane_index);
 		return false;
 	}
+	plane_init[plane_index] = true;
 	return true;
 }
 
diff --git a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
index 72065c1..d677ac2 100644
--- a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
+++ b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
@@ -507,12 +507,13 @@
  * Entrypoint for aux plane = realm.par_base + (plane_num * realm..par_size)
  */
 void host_realm_set_aux_plane_args(struct realm *realm_ptr,
-		unsigned int plane_num)
+		unsigned int plane_num, unsigned int rec_num)
 {
 	/* Plane Index */
-	host_shared_data_set_host_val(realm_ptr, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, plane_num);
+	host_shared_data_set_host_val(realm_ptr, PRIMARY_PLANE_ID, rec_num,
+			HOST_ARG1_INDEX, plane_num);
 
 	/* Plane entrypoint */
-	host_shared_data_set_host_val(realm_ptr, PRIMARY_PLANE_ID, 0U, HOST_ARG2_INDEX,
+	host_shared_data_set_host_val(realm_ptr, PRIMARY_PLANE_ID, rec_num, HOST_ARG2_INDEX,
 			realm_ptr->par_base + (plane_num * realm_ptr->par_size));
 }
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c b/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
index e6a9cd5..951a1f6 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_payload_multiple_rec_tests.c
@@ -301,6 +301,206 @@
 	return host_cmp_result();
 }
 
+static test_result_t plane_cpu_on_handler(void)
+{
+	bool ret;
+	struct rmi_rec_run *run;
+	unsigned int i;
+
+	spin_lock(&secondary_cpu_lock);
+	i = ++is_secondary_cpu_on;
+	spin_unlock(&secondary_cpu_lock);
+
+	/* Args for plane 0 to enter plane 1 on rec i */
+	host_realm_set_aux_plane_args(&realm, 1U, i);
+
+	/* CMD for Plane 1 Rec i */
+	host_shared_data_set_realm_cmd(&realm, REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD, 1U, i);
+
+	run = (struct rmi_rec_run *)realm.run[i];
+
+	/* Enter P0 and then P1 */
+	ret = host_enter_realm_execute(&realm, REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD,
+			RMI_EXIT_PSCI, i);
+	if (ret) {
+		if (run->exit.gprs[0] == SMC_PSCI_CPU_OFF) {
+			return TEST_RESULT_SUCCESS;
+		}
+	}
+	ERROR("Rec %d failed", i);
+	return TEST_RESULT_FAIL;
+}
+
+/*
+ * The test creates a realm with 2 planes and MAX recs
+ * Host enters P0 and then PN
+ * P1 issues PSCI_CPU_ON SMC, returns back to P0
+ * P0 forwards PSCI_CPU_ON to Host
+ * On receiving PSCI_CPU_ON call from P0 REC0 for all other recs,
+ * the test completes the PSCI call and re-enters P0 REC0 - followed by P1 REC0.
+ * Turn ON secondary CPUs upto a max of MAX_REC_COUNT.
+ * Each of the secondary then enters Realm (P0 followed by P1) with a different REC
+ * It is expected that the REC will exit with PSCI_CPU_OFF as the exit reason.
+ * P0 REC0 checks if all other CPUs are off, via PSCI_AFFINITY_INFO.
+ * Host completes the PSCI requests.
+ */
+test_result_t host_realm_multi_planes_multi_rec_multiple_cpu(void)
+{
+	bool ret1, ret2;
+	test_result_t ret3 = TEST_RESULT_FAIL;
+	int ret = RMI_ERROR_INPUT;
+	u_register_t rec_num;
+	u_register_t other_mpidr, my_mpidr;
+	struct rmi_rec_run *run;
+	unsigned int host_call_result, i;
+	u_register_t rec_flag[MAX_REC_COUNT] = {RMI_RUNNABLE};
+	u_register_t exit_reason;
+	unsigned int cpu_node, rec_count, num_aux_planes = 1U;
+	u_register_t feature_flag0 = 0U, feature_flag1 = 0U;
+	long sl = RTT_MIN_LEVEL;
+
+	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
+
+	rec_count = tftf_get_total_cpus_count();
+	assert(rec_count <= MAX_REC_COUNT);
+
+	if (is_feat_52b_on_4k_2_supported()) {
+		feature_flag0 = RMI_FEATURE_REGISTER_0_LPA2;
+		sl = RTT_MIN_LEVEL_LPA2;
+	}
+
+	if (!are_planes_supported()) {
+		return TEST_RESULT_SKIPPED;
+	}
+
+	if (is_single_rtt_supported()) {
+		/* Use single RTT with S2AP Indirect */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+				RMI_PLANE_RTT_SINGLE);
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
+	for (i = 1U; i < rec_count; i++) {
+		rec_flag[i] = RMI_NOT_RUNNABLE;
+	}
+
+	if (!host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
+			feature_flag0, feature_flag1, sl, rec_flag, rec_count, num_aux_planes)) {
+		return TEST_RESULT_FAIL;
+	}
+
+	is_secondary_cpu_on = 0U;
+	init_spinlock(&secondary_cpu_lock);
+	my_mpidr = read_mpidr_el1() & MPID_MASK;
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, rec_count);
+	host_shared_data_set_host_val(&realm, 1U, 0U, HOST_ARG3_INDEX, rec_count);
+
+	/* Set args for entering Plane 1 Rec0 */
+	host_realm_set_aux_plane_args(&realm, 1U, 0U);
+
+	/* CMD for Plane 1 */
+	host_shared_data_set_realm_cmd(&realm, REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD, 1U, 0U);
+
+	/* Enter P0, and then PN */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANES_MULTIPLE_REC_MULTIPLE_CPU_CMD,
+			RMI_EXIT_PSCI, 0U);
+
+	if (!ret1) {
+		ERROR("Host did not receive CPU ON request\n");
+
+		goto destroy_realm;
+	}
+	while (true) {
+		run = (struct rmi_rec_run *)realm.run[0];
+		if (run->exit.gprs[0] != SMC_PSCI_CPU_ON_AARCH64) {
+			ERROR("Host did not receive CPU ON request\n");
+			goto destroy_realm;
+		}
+		rec_num = host_realm_find_rec_by_mpidr(run->exit.gprs[1], &realm);
+		if (rec_num >= MAX_REC_COUNT) {
+			ERROR("Invalid mpidr requested\n");
+			goto destroy_realm;
+		}
+		ret = host_rmi_psci_complete(realm.rec[0], realm.rec[rec_num],
+				(unsigned long)PSCI_E_SUCCESS);
+		if (ret == RMI_SUCCESS) {
+			/* Re-enter REC0 complete CPU_ON */
+			ret = host_realm_rec_enter(&realm, &exit_reason,
+				&host_call_result, 0U);
+			if (ret != RMI_SUCCESS || exit_reason != RMI_EXIT_PSCI) {
+				break;
+			}
+		} else {
+			ERROR("host_rmi_psci_complete failed\n");
+			goto destroy_realm;
+		}
+	}
+	if (exit_reason != RMI_EXIT_HOST_CALL || host_call_result != TEST_RESULT_SUCCESS) {
+		ERROR("Realm failed\n");
+		goto destroy_realm;
+	}
+
+	i = 0U;
+
+	/* Turn on all CPUs */
+	for_each_cpu(cpu_node) {
+		if (i == (rec_count - 1U)) {
+			break;
+		}
+		other_mpidr = tftf_get_mpidr_from_node(cpu_node);
+		if (other_mpidr == my_mpidr) {
+			continue;
+		}
+
+		/* Power on the other CPU */
+		ret = tftf_try_cpu_on(other_mpidr, (uintptr_t)plane_cpu_on_handler, 0);
+		if (ret != PSCI_E_SUCCESS) {
+			ERROR("TFTF CPU ON failed\n");
+			goto destroy_realm;
+		}
+		i++;
+	}
+
+	while (true) {
+		/* Re-enter REC0 complete PSCI_AFFINITY_INFO */
+		ret = host_realm_rec_enter(&realm, &exit_reason, &host_call_result, 0U);
+		if (ret != RMI_SUCCESS) {
+			ERROR("Rec0 re-enter failed\n");
+			goto destroy_realm;
+		}
+		if (run->exit.gprs[0] != SMC_PSCI_AFFINITY_INFO_AARCH64) {
+			break;
+		}
+		rec_num = host_realm_find_rec_by_mpidr(run->exit.gprs[1], &realm);
+		if (rec_num >= rec_count) {
+			ERROR("Invalid mpidr requested\n");
+			goto destroy_realm;
+		}
+		ret = host_rmi_psci_complete(realm.rec[0], realm.rec[rec_num],
+				(unsigned long)PSCI_E_SUCCESS);
+
+		if (ret != RMI_SUCCESS) {
+			ERROR("host_rmi_psci_complete failed\n");
+			goto destroy_realm;
+		}
+	}
+
+	if (ret == RMI_SUCCESS && exit_reason == RMI_EXIT_HOST_CALL) {
+		ret3 = host_call_result;
+	}
+destroy_realm:
+	waitms(100U);
+	ret2 = host_destroy_realm(&realm);
+
+	if ((ret != RMI_SUCCESS) || !ret2) {
+		ERROR("%s(): enter=%d destroy=%d\n",
+		__func__, ret, ret2);
+		return TEST_RESULT_FAIL;
+	}
+
+	return ret3;
+}
+
 static test_result_t cpu_on_handler(void)
 {
 	bool ret;
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
index 06e6475..51dc94b 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
@@ -13,6 +13,8 @@
 #include <drivers/arm/arm_gic.h>
 #include <drivers/arm/gic_v3.h>
 #include <heap/page_alloc.h>
+#include <lib/context_mgmt/context_el1.h>
+#include <lib/context_mgmt/context_el2.h>
 #include <pauth.h>
 #include <test_helpers.h>
 
@@ -27,29 +29,16 @@
 
 static struct realm realm[MAX_REALM_COUNT];
 static struct pmu_registers pmu_state;
+static el1_ctx_regs_t el1_ctx_before = {0};
+static el1_ctx_regs_t el1_ctx_after = {0};
+static el2_sysregs_t el2_ctx_before = {0};
+static el2_sysregs_t el2_ctx_after = {0};
 
 #if ENABLE_PAUTH
 static uint128_t pauth_keys_before[NUM_KEYS];
 static uint128_t pauth_keys_after[NUM_KEYS];
 #endif
 
-bool are_planes_supported(void)
-{
-	u_register_t feature_flag;
-
-	/* Read Realm Feature Reg 0 */
-	if (host_rmi_features(0UL, &feature_flag) != REALM_SUCCESS) {
-		ERROR("%s() failed\n", "host_rmi_features");
-		return false;
-	}
-
-	if (EXTRACT(RMI_FEATURE_REGISTER_0_MAX_NUM_AUX_PLANES, feature_flag) > 0UL) {
-		return true;
-	}
-
-	return false;
-}
-
 /*
  * @Test_Aim@ Test RSI_PLANE_REG_READ/WRITE
  */
@@ -87,7 +76,7 @@
 
 	run = (struct rmi_rec_run *)realm.run[0U];
 
-	host_realm_set_aux_plane_args(&realm, 1U);
+	host_realm_set_aux_plane_args(&realm, 1U, 0U);
 	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_REG_RW_CMD,
 			RMI_EXIT_HOST_CALL, 0U);
 
@@ -148,6 +137,14 @@
 		return TEST_RESULT_FAIL;
 	}
 
+	/* save EL1 registers */
+	save_el1_sysregs_context(&el1_ctx_before);
+	modify_el1_context_sysregs(&el1_ctx_before, NS_CORRUPT_EL1_REGS);
+	save_el1_sysregs_context(&el1_ctx_before);
+
+	/* save EL2 registers */
+	el2_save_registers(&el2_ctx_before);
+
 	/* CMD for Plane N */
 	for (unsigned int j = 1U; j <= MAX_AUX_PLANE_COUNT; j++) {
 		host_shared_data_set_realm_cmd(&realm, REALM_SLEEP_CMD, j, 0U);
@@ -158,7 +155,7 @@
 	for (unsigned int j = 1U; j <= MAX_AUX_PLANE_COUNT; j++) {
 		run = (struct rmi_rec_run *)realm.run[0U];
 
-		host_realm_set_aux_plane_args(&realm, j);
+		host_realm_set_aux_plane_args(&realm, j, 0U);
 		ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
 				RMI_EXIT_HOST_CALL, 0U);
 
@@ -171,6 +168,28 @@
 					run->exit.esr, run->exit.far);
 		}
 	}
+
+	/* save EL1 registers */
+	save_el1_sysregs_context(&el1_ctx_after);
+
+	INFO("Comparing EL1 registers\n");
+	ret2 = compare_el1_contexts(&el1_ctx_before, &el1_ctx_after);
+	if (!ret2) {
+		ERROR("NS EL1 registers corrupted\n");
+		host_destroy_realm(&realm);
+		return TEST_RESULT_FAIL;
+	}
+
+	/* save EL2 registers */
+	el2_save_registers(&el2_ctx_after);
+
+	INFO("Comparing EL2 registers\n");
+	if (memcmp(&el2_ctx_before, &el2_ctx_after, sizeof(el2_sysregs_t))) {
+		ERROR("NS EL2 registers corrupted\n");
+		host_destroy_realm(&realm);
+		return TEST_RESULT_FAIL;
+	}
+
 	ret2 = host_destroy_realm(&realm);
 
 	if (!ret1 || !ret2) {
@@ -185,7 +204,9 @@
 /*
  * @Test_Aim@ Test realm payload creation with 3 Aux Planes, enter all Planes
  * Host cannot enter Aux Planes directly,
- * Host will enter P0, P0 will enter aux plane
+ * Host will enter P0, P0 will enter aux plane.
+ * This test also validates that NS EL1 and NS EL2 registers are preserved by RMM.
+ * This test also validates that s2por_el1 register is not accessible in realm.
  */
 test_result_t host_test_realm_create_planes_enter_single_rtt(void)
 {
@@ -225,21 +246,56 @@
 			HOST_ARG1_INDEX, SLEEP_TIME_MS);
 	}
 
+	save_el1_sysregs_context(&el1_ctx_before);
+	modify_el1_context_sysregs(&el1_ctx_before, NS_CORRUPT_EL1_REGS);
+	save_el1_sysregs_context(&el1_ctx_before);
+
+	el2_save_registers(&el2_ctx_before);
+
 	for (unsigned int j = 1U; j <= MAX_AUX_PLANE_COUNT; j++) {
 		run = (struct rmi_rec_run *)realm.run[0U];
 
-		host_realm_set_aux_plane_args(&realm, j);
+		host_realm_set_aux_plane_args(&realm, j, 0U);
 		ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
 				RMI_EXIT_HOST_CALL, 0U);
 
-		if (run->exit.exit_reason != RMI_EXIT_HOST_CALL) {
+		if (!ret1) {
 			ERROR("Rec0 error exit=0x%lx ret1=%d HPFAR=0x%lx \
 				esr=0x%lx far=0x%lx\n",
 				run->exit.exit_reason, ret1,
 				run->exit.hpfar,
 				run->exit.esr, run->exit.far);
+			goto destroy_realm;
 		}
 	}
+
+	save_el1_sysregs_context(&el1_ctx_before);
+
+	INFO("Comparing EL1 registers\n");
+	ret1 = compare_el1_contexts(&el1_ctx_before, &el1_ctx_after);
+
+	if (!ret1) {
+		ERROR("NS EL1 registers corrupted\n");
+		goto destroy_realm;
+	}
+
+	el2_save_registers(&el2_ctx_after);
+
+	INFO("Comparing EL2 registers\n");
+	if (memcmp(&el2_ctx_before, &el2_ctx_after, sizeof(el2_sysregs_t))) {
+		ERROR("NS EL2 registers corrupted\n");
+		goto destroy_realm;
+	}
+
+	/* Test that realm cannot modify s2por_el1 */
+	ret1 = host_enter_realm_execute(&realm, REALM_S2POE_ACCESS,
+			RMI_EXIT_HOST_CALL, 0U);
+
+	if (!ret1) {
+		ERROR("S2POR_EL1 reg access test failed\n");
+	}
+
+destroy_realm:
 	ret2 = host_destroy_realm(&realm);
 
 	if (!ret1 || !ret2) {
@@ -896,19 +952,20 @@
  * Host calls data_destroy, new state HIPAS=UNASSIGNED RIPAS=DESTROYED
  * Enter Realm, Rec0 executes from page, and Rec1 reads the page
  * Realm should trigger an Instr/Data abort, and will exit to Host.
- * The Host verifies exit reason is Instr/Data abort
+ * The Host verifies exit reason is Instr/Data abort.
+ * Repeat the test for Plane N.
  */
 test_result_t host_realm_abort_unassigned_destroyed(void)
 {
 	bool ret1, ret2;
 	test_result_t res = TEST_RESULT_FAIL;
-	u_register_t ret, data, top;
+	u_register_t ret, data, top, num_aux_planes = 0UL;
 	struct realm realm;
 	struct rmi_rec_run *run;
 	struct rtt_entry rtt;
-	u_register_t feature_flag0 = 0UL;
+	u_register_t feature_flag0 = 0UL, feature_flag1 = 0UL;
 	long sl = RTT_MIN_LEVEL;
-	u_register_t rec_flag[2U] = {RMI_RUNNABLE, RMI_RUNNABLE}, base;
+	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE}, base;
 
 	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
 
@@ -917,8 +974,19 @@
 		sl = RTT_MIN_LEVEL_LPA2;
 	}
 
+	/* This test is skipped if S2POE is not supported to keep test simple */
+	if (are_planes_supported() && is_single_rtt_supported()) {
+		num_aux_planes = 1UL;
+
+		/* use single RTT for all planes */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+			RMI_PLANE_RTT_SINGLE);
+
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
 	if (!host_create_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
-			feature_flag0, 0U, sl, rec_flag, 2U, 0U)) {
+			feature_flag0, feature_flag1, sl, rec_flag, 4U, num_aux_planes)) {
 		return TEST_RESULT_FAIL;
 	}
 
@@ -943,8 +1011,8 @@
 	}
 	INFO("Initial state base = 0x%lx rtt.state=0x%lx rtt.ripas=0x%lx\n",
 			base, rtt.state, rtt.ripas);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base);
 
 	ret = host_rmi_data_destroy(realm.rd, base, &data, &top);
 	if (ret != RMI_SUCCESS || data != base) {
@@ -999,6 +1067,65 @@
 	}
 	INFO("DA FAR=0x%lx, HPFAR=0x%lx ESR= 0x%lx\n", run->exit.far, run->exit.hpfar,
 			run->exit.esr);
+
+	if (num_aux_planes == 0U) {
+		res = TEST_RESULT_SUCCESS;
+		goto undelegate_destroy;
+	}
+
+	INFO("Running test on Plane 1\n");
+
+	/*
+	 * Arg used by Plane 1 Rec 2/3
+	 * Plane 1 will fetch base, access it and get an abort causing rec exit
+	 */
+	host_shared_data_set_host_val(&realm, 1U, 2U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 3U, HOST_ARG3_INDEX, base);
+
+	/* Arg for Plane0 instruction to enter Plane1 on Rec 2,3 */
+	host_realm_set_aux_plane_args(&realm, 1U, 2U);
+	host_realm_set_aux_plane_args(&realm, 1U, 3U);
+
+	/* Test cmd for Plane 1 Rec 2/3 */
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 2U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 3U);
+
+
+	run = (struct rmi_rec_run *)realm.run[2];
+
+	/* Rec2 expect rec exit due to Instr Abort unassigned destroyed page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+		RMI_EXIT_SYNC, 2U);
+
+	/* ESR.EC == 0b100000 Instruction Abort from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+			|| (EC_BITS(run->exit.esr) != EC_IABORT_LOWER_EL)
+			|| ((run->exit.esr & ISS_IFSC_MASK) < FSC_L0_TRANS_FAULT)
+			|| ((run->exit.esr & ISS_IFSC_MASK) > FSC_L3_TRANS_FAULT)
+			|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		ERROR("Plane1 Rec2 did not fault ESR=0x%lx\n", run->exit.esr);
+		goto undelegate_destroy;
+	}
+	INFO("Plane1 IA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
+			run->exit.esr);
+
+	run = (struct rmi_rec_run *)realm.run[3];
+
+	/* Rec3 expect rec exit due to Data Abort unassigned destroyed page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+			RMI_EXIT_SYNC, 3U);
+
+	/* ESR.EC == 0b100100 Data Abort exception from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+		|| (EC_BITS(run->exit.esr) != EC_DABORT_LOWER_EL)
+		|| ((run->exit.esr & ISS_DFSC_MASK) < FSC_L0_TRANS_FAULT)
+		|| ((run->exit.esr & ISS_DFSC_MASK) > FSC_L3_TRANS_FAULT)
+		|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		ERROR("Plane1 Rec3 did not fault\n");
+		goto undelegate_destroy;
+	}
+	INFO("Plane1 DA FAR=0x%lx, HPFAR=0x%lx ESR= 0x%lx\n", run->exit.far, run->exit.hpfar,
+			run->exit.esr);
 	res = TEST_RESULT_SUCCESS;
 
 undelegate_destroy:
@@ -1023,18 +1150,19 @@
  * Enter Realm, REC0 executes from page, and REC1 reads the page
  * Realm should trigger an Instr/Data abort, and will exit to Host.
  * Host verifies exit reason is Instr/Data abort.
+ * Repeat the test for Plane N.
  */
 test_result_t host_realm_abort_unassigned_ram(void)
 {
 	bool ret1, ret2;
-	u_register_t ret, top;
+	u_register_t ret, top, num_aux_planes = 0UL;
 	struct realm realm;
 	struct rmi_rec_run *run;
 	struct rtt_entry rtt;
-	u_register_t feature_flag0 = 0UL;
+	u_register_t feature_flag0 = 0UL, feature_flag1 = 0UL;
 	long sl = RTT_MIN_LEVEL;
 	test_result_t res = TEST_RESULT_FAIL;
-	u_register_t rec_flag[2U] = {RMI_RUNNABLE, RMI_RUNNABLE}, base;
+	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE}, base;
 
 	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
 
@@ -1043,8 +1171,19 @@
 		sl = RTT_MIN_LEVEL_LPA2;
 	}
 
+	/* Test is skipped if S2POE is not supported to keep test simple */
+	if (are_planes_supported() && is_single_rtt_supported()) {
+		num_aux_planes = 1UL;
+
+		/* use single RTT for all planes */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+			RMI_PLANE_RTT_SINGLE);
+
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
 	if (!host_create_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
-			feature_flag0, 0U, sl, rec_flag, 2U, 0U)) {
+			feature_flag0, feature_flag1, sl, rec_flag, 4U, num_aux_planes)) {
 		return TEST_RESULT_FAIL;
 	}
 
@@ -1055,6 +1194,20 @@
 
 	/* Set RIPAS of PAGE to RAM */
 	ret = host_rmi_rtt_init_ripas(realm.rd, base, base + PAGE_SIZE, &top);
+	if (RMI_RETURN_STATUS(ret) == RMI_ERROR_RTT) {
+		/* Create missing RTTs till L3 and retry */
+		int8_t level = RMI_RETURN_INDEX(ret);
+
+		ret = host_rmi_create_rtt_levels(&realm, base,
+				(u_register_t)level, 3U);
+		if (ret != RMI_SUCCESS) {
+			ERROR("host_rmi_create_rtt_levels failed\n");
+			goto destroy_realm;
+		}
+
+		ret = host_rmi_rtt_init_ripas(realm.rd, base, base + PAGE_SIZE, &top);
+	}
+
 	if (ret != RMI_SUCCESS) {
 		ERROR("%s() failed, ret=0x%lx line=%u\n",
 			"host_rmi_rtt_init_ripas", ret, __LINE__);
@@ -1073,8 +1226,8 @@
 	}
 	INFO("Initial state base = 0x%lx rtt.state=0x%lx rtt.ripas=0x%lx\n",
 			base, rtt.state, rtt.ripas);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base);
 
 	/* Rec0 expect rec exit due to Instr Abort unassigned ram page */
 	ret1 = host_enter_realm_execute(&realm, REALM_INSTR_FETCH_CMD,
@@ -1108,6 +1261,65 @@
 	}
 	INFO("DA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
 			run->exit.esr);
+
+	if (num_aux_planes == 0U) {
+		res = TEST_RESULT_SUCCESS;
+		goto destroy_realm;
+	}
+
+	INFO("Running test on Plane 1\n");
+
+	/*
+	 * Arg used by Plane 1 Rec 2/3
+	 * Plane 1 will access the base, causing rec exit due to abort
+	 */
+	host_shared_data_set_host_val(&realm, 1U, 2U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 3U, HOST_ARG3_INDEX, base);
+
+	/* Arg for Plane0 to enter Plane1 on Rec 2,3 */
+	host_realm_set_aux_plane_args(&realm, 1U, 2U);
+	host_realm_set_aux_plane_args(&realm, 1U, 3U);
+
+	/* Test cmd for Plane 1 Rec 2/3 */
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 2U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 3U);
+
+	/* Rec2 expect rec exit due to Instr Abort unassigned ram page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+			RMI_EXIT_SYNC, 2U);
+
+	run = (struct rmi_rec_run *)realm.run[2];
+
+	/* ESR.EC == 0b100000 Instruction Abort from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+			|| (EC_BITS(run->exit.esr) != EC_IABORT_LOWER_EL)
+			|| ((run->exit.esr & ISS_IFSC_MASK) < FSC_L0_TRANS_FAULT)
+			|| ((run->exit.esr & ISS_IFSC_MASK) > FSC_L3_TRANS_FAULT)
+			|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		INFO("Plane1 Rec2 did not fault FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n",
+				run->exit.far, run->exit.hpfar,	run->exit.esr);
+		goto destroy_realm;
+	}
+	INFO("Plane1 IA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
+			run->exit.esr);
+
+	run = (struct rmi_rec_run *)realm.run[3];
+
+	/* Rec3 expect rec exit due to Data Abort unassigned ram page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+			RMI_EXIT_SYNC, 3U);
+
+	/* ESR.EC == 0b100100 Data Abort exception from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+		|| (EC_BITS(run->exit.esr) != EC_DABORT_LOWER_EL)
+		|| ((run->exit.esr & ISS_DFSC_MASK) < FSC_L0_TRANS_FAULT)
+		|| ((run->exit.esr & ISS_DFSC_MASK) > FSC_L3_TRANS_FAULT)
+		|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		ERROR("Plane1 Rec3 did not fault ESR=0x%lx\n", run->exit.esr);
+		goto destroy_realm;
+	}
+	INFO("Plane1 DA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
+			run->exit.esr);
 	res = TEST_RESULT_SUCCESS;
 
 destroy_realm:
@@ -1131,7 +1343,8 @@
  * Host calls data_create_unknown, new state HIPAS=ASSIGNED RIPAS=DESTROYED
  * Enter Realm, REC0 executes from page, and REC1 reads the page
  * Realm should trigger an Instr/Data abort, and will exit to Host.
- * The Host verifies exit reason is Instr/Data abort
+ * The Host verifies exit reason is Instr/Data abort.
+ * Repeat the test for Plane N.
  */
 test_result_t host_realm_abort_assigned_destroyed(void)
 {
@@ -1141,9 +1354,10 @@
 	struct realm realm;
 	struct rmi_rec_run *run;
 	struct rtt_entry rtt;
-	u_register_t feature_flag0 = 0UL;
+	u_register_t feature_flag0 = 0UL, num_aux_planes = 0UL;
+	u_register_t feature_flag1 = 0UL;
 	long sl = RTT_MIN_LEVEL;
-	u_register_t rec_flag[2U] = {RMI_RUNNABLE, RMI_RUNNABLE}, base;
+	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE}, base;
 
 	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
 
@@ -1152,8 +1366,19 @@
 		sl = RTT_MIN_LEVEL_LPA2;
 	}
 
+	/* Test is skipped if S2POE is not supported to keep test simple */
+	if (are_planes_supported() && is_single_rtt_supported()) {
+		num_aux_planes = 1UL;
+
+		/* use single RTT for all planes */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+			RMI_PLANE_RTT_SINGLE);
+
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
 	if (!host_create_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
-			feature_flag0, 0U, sl, rec_flag, 2U, 0U)) {
+			feature_flag0, feature_flag1, sl, rec_flag, 4U, num_aux_planes)) {
 		return TEST_RESULT_FAIL;
 	}
 
@@ -1175,8 +1400,8 @@
 	}
 	INFO("Initial state base = 0x%lx rtt.state=0x%lx rtt.ripas=0x%lx\n",
 			base, rtt.state, rtt.ripas);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base);
 
 	if (host_realm_activate(&realm) != REALM_SUCCESS) {
 		ERROR("%s() failed\n", "host_realm_activate");
@@ -1241,6 +1466,63 @@
 	}
 	INFO("DA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
 				run->exit.esr);
+
+	if (num_aux_planes == 0U) {
+		res = TEST_RESULT_SUCCESS;
+		goto destroy_data;
+	}
+
+	INFO("Running test on Plane 1\n");
+
+	/*
+	 * Args used by Plane 1, Rec 2/3
+	 * Plane1 accesses base, causes rec exit due to abort
+	 */
+	host_shared_data_set_host_val(&realm, 1U, 2U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 3U, HOST_ARG3_INDEX, base);
+
+	/* Arg for Plane0 to enter Plane1 on Rec 2,3 */
+	host_realm_set_aux_plane_args(&realm, 1U, 2U);
+	host_realm_set_aux_plane_args(&realm, 1U, 3U);
+
+	/* Test cmd for Plane 1, Rec 2/3 */
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 2U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 3U);
+
+	run = (struct rmi_rec_run *)realm.run[2];
+
+	/* Rec2, expect rec exit due to Instr Abort assigned destroyed page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+		RMI_EXIT_SYNC, 2U);
+
+	/* ESR.EC == 0b100000 Instruction Abort from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+		|| (EC_BITS(run->exit.esr) != EC_IABORT_LOWER_EL)
+		|| ((run->exit.esr & ISS_IFSC_MASK) < FSC_L0_TRANS_FAULT)
+		|| ((run->exit.esr & ISS_IFSC_MASK) > FSC_L3_TRANS_FAULT)
+		|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		ERROR("Plane1 Rec2 did not fault ESR=0x%lx\n", run->exit.esr);
+		goto destroy_data;
+	}
+	INFO("Plane1 IA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
+				run->exit.esr);
+	run = (struct rmi_rec_run *)realm.run[3];
+
+	/* Rec3  expect rec exit due to Data Abort  assigned destroyed page */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+			RMI_EXIT_SYNC, 3U);
+
+	/* ESR.EC == 0b100100 Data Abort exception from a lower Exception level */
+	if (!ret1 || ((run->exit.hpfar >> 4U) != (base >> PAGE_SIZE_SHIFT)
+		|| (EC_BITS(run->exit.esr) != EC_DABORT_LOWER_EL)
+		|| ((run->exit.esr & ISS_DFSC_MASK) < FSC_L0_TRANS_FAULT)
+		|| ((run->exit.esr & ISS_DFSC_MASK) > FSC_L3_TRANS_FAULT)
+		|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U))) {
+		ERROR("Plane1 Rec3 did not fault ESR=0x%lx\n", run->exit.esr);
+		goto destroy_data;
+	}
+	INFO("Plane1 DA FAR=0x%lx, HPFAR=0x%lx ESR=0x%lx\n", run->exit.far, run->exit.hpfar,
+				run->exit.esr);
 	res = TEST_RESULT_SUCCESS;
 
 destroy_data:
@@ -1268,17 +1550,21 @@
  * Rec1 generated DA unassigned empty
  * Rec2 generated IA for assigned empty
  * Rec3 generated DA for assigned empty
+ * Repeat the test for Plane1.
+ * Accessing RIPAS=EMPTY causes plane exit to P0
  */
 test_result_t host_realm_sea_empty(void)
 {
 	bool ret1, ret2;
 	test_result_t res = TEST_RESULT_FAIL;
-	u_register_t ret, base, esr;
+	u_register_t ret, base, esr, num_aux_planes = 0UL, far;
+	u_register_t feature_flag1 = 0UL;
 	struct realm realm;
 	struct rtt_entry rtt;
 	u_register_t feature_flag0 = 0UL;
 	long sl = RTT_MIN_LEVEL;
-	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE};
+	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE,
+				   RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE};
 
 	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
 
@@ -1287,23 +1573,56 @@
 		sl = RTT_MIN_LEVEL_LPA2;
 	}
 
+	/* Test are skipped if S2POE is not supported to keep test simple */
+	if (are_planes_supported() && is_single_rtt_supported()) {
+		num_aux_planes = 1UL;
+
+		/* use single RTT for all planes */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+			RMI_PLANE_RTT_SINGLE);
+
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
 	if (!host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
-			feature_flag0, 0U, sl, rec_flag, 4U, 0U)) {
+			feature_flag0, feature_flag1, sl, rec_flag, 8U, num_aux_planes)) {
 		return TEST_RESULT_FAIL;
 	}
 
-	base = (u_register_t)page_alloc(PAGE_SIZE);
+	base = (u_register_t)page_alloc(PAGE_SIZE * 2U);
+
+	ret = host_rmi_rtt_readentry(realm.rd, base, 3L, &rtt);
+	if (rtt.walk_level != 3U) {
+		/* Create L3 RTT */
+		host_rmi_create_rtt_levels(&realm, base, rtt.walk_level, 3U);
+	}
 
 	ret = host_rmi_rtt_readentry(realm.rd, base, 3L, &rtt);
 	if (rtt.state != RMI_UNASSIGNED ||
-			(rtt.ripas != RMI_EMPTY)) {
+			(rtt.ripas != RMI_EMPTY) ||
+			(rtt.walk_level != 3U)) {
 		ERROR("wrong initial state\n");
 		goto destroy_realm;
 	}
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 2U, HOST_ARG1_INDEX, base);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 3U, HOST_ARG1_INDEX, base);
+
+	ret = host_rmi_rtt_readentry(realm.rd, base + PAGE_SIZE, 3L, &rtt);
+	if (rtt.walk_level != 3U) {
+		/* Create L3 RTT */
+		host_rmi_create_rtt_levels(&realm, base + PAGE_SIZE, rtt.walk_level, 3U);
+	}
+
+	ret = host_rmi_rtt_readentry(realm.rd, base + PAGE_SIZE, 3L, &rtt);
+	if (rtt.state != RMI_UNASSIGNED ||
+			(rtt.ripas != RMI_EMPTY) ||
+			(rtt.walk_level != 3U)) {
+		ERROR("wrong initial state\n");
+		goto destroy_realm;
+	}
+
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 2U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 3U, HOST_ARG3_INDEX, base);
 
 	/* Rec0 expect IA due to SEA unassigned empty page */
 	ret1 = host_enter_realm_execute(&realm, REALM_INSTR_FETCH_CMD,
@@ -1383,6 +1702,124 @@
 		ERROR("Rec3 incorrect ESR=0x%lx\n", esr);
 	}
 	INFO("Rec3 ESR=0x%lx\n", esr);
+
+	if (num_aux_planes == 0U) {
+		res = TEST_RESULT_SUCCESS;
+		goto undelegate_destroy;
+	}
+
+	host_rmi_granule_undelegate(base);
+
+	INFO("Running test on Plane 1\n");
+	base += PAGE_SIZE;
+
+	/*
+	 * Args used by Plane 1, Rec 4/5/6/7
+	 * Plane1 will access base, causing Plane exit to P0
+	 * P0 will return ESR?FAR back to Host
+	 */
+	host_shared_data_set_host_val(&realm, 1U, 4U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 5U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 6U, HOST_ARG3_INDEX, base);
+	host_shared_data_set_host_val(&realm, 1U, 7U, HOST_ARG3_INDEX, base);
+
+	/* Arg for Plane0 to enter Plane1 on Rec4,5,6,7 */
+	host_realm_set_aux_plane_args(&realm, 1U, 4U);
+	host_realm_set_aux_plane_args(&realm, 1U, 5U);
+	host_realm_set_aux_plane_args(&realm, 1U, 6U);
+	host_realm_set_aux_plane_args(&realm, 1U, 7U);
+
+	/* Test cmd for Plane 1, Rec 4/5/6/7 */
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 4U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 5U);
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 6U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 7U);
+
+	/* Rec4 expect IA due to unassigned empty page */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_EXCEPTION_CMD,
+			RMI_EXIT_HOST_CALL, 4U);
+	if (!ret1) {
+		ERROR("Rec4 did not fault\n");
+		goto destroy_realm;
+	}
+
+	/* get ESR FAR set by P0 */
+	esr = host_shared_data_get_realm_val(&realm, 0U, 4U, HOST_ARG2_INDEX);
+	far = host_shared_data_get_realm_val(&realm, 0U, 4U, HOST_ARG3_INDEX);
+	if ((EC_BITS(esr) != EC_IABORT_LOWER_EL) || (far != base)) {
+		ERROR("Rec4 incorrect ESR=0x%lx FAR=0x%lx\n", esr, far);
+		goto destroy_realm;
+	}
+	INFO("Rec4 ESR=0x%lx\n", esr);
+
+	/* Rec5 expect DA due to unassigned empty page */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_EXCEPTION_CMD,
+			RMI_EXIT_HOST_CALL, 5U);
+	if (!ret1) {
+		ERROR("Rec5 did not fault\n");
+		goto destroy_realm;
+	}
+
+	/* get ESR FAR set by P0 */
+	esr = host_shared_data_get_realm_val(&realm, 0U, 5U, HOST_ARG2_INDEX);
+	far = host_shared_data_get_realm_val(&realm, 0U, 5U, HOST_ARG3_INDEX);
+	if ((EC_BITS(esr) != EC_DABORT_LOWER_EL) || (far != base)) {
+		ERROR("Rec5 incorrect ESR=0x%lx\n", esr);
+		goto destroy_realm;
+	}
+	INFO("Rec5 ESR=0x%lx\n", esr);
+
+	/* DATA_CREATE_UNKNOWN */
+	ret = host_realm_delegate_map_protected_data(true, &realm, base, PAGE_SIZE, 0U);
+	if (ret != RMI_SUCCESS) {
+		ERROR("host_realm_delegate_map_protected_data failed\n");
+		goto destroy_realm;
+	}
+	ret = host_rmi_rtt_readentry(realm.rd, base, 3L, &rtt);
+	if (rtt.state != RMI_ASSIGNED ||
+			(rtt.ripas != RMI_EMPTY)) {
+		ERROR("wrong state after DATA_CRATE_UNKNOWN\n");
+		goto undelegate_destroy;
+	}
+	INFO("final state base = 0x%lx rtt.state=0x%lx rtt.ripas=0x%lx level=0x%lx\n",
+			base, rtt.state, rtt.ripas, rtt.walk_level);
+
+	/* Rec6 expect IA due to assigned empty page */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_EXCEPTION_CMD,
+		RMI_EXIT_HOST_CALL, 6U);
+
+	if (!ret1) {
+		ERROR("Rec6 did not fault\n");
+		goto undelegate_destroy;
+	}
+
+	/* get ESR FAR set by P0 */
+	esr = host_shared_data_get_realm_val(&realm, 0U, 6U, HOST_ARG2_INDEX);
+	far = host_shared_data_get_realm_val(&realm, 0U, 6U, HOST_ARG3_INDEX);
+
+	if ((EC_BITS(esr) != EC_IABORT_LOWER_EL) || (far != base)) {
+		ERROR("Rec6 incorrect ESR=0x%lx\n", esr);
+		goto undelegate_destroy;
+	}
+	INFO("Rec6 ESR=0x%lx\n", esr);
+
+	/* Rec7 expect DA due to unassigned empty page */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_EXCEPTION_CMD,
+			RMI_EXIT_HOST_CALL, 7U);
+	if (!ret1) {
+		ERROR("Rec7 did not fault\n");
+		goto undelegate_destroy;
+	}
+
+	/* get ESR FAR set by P0 */
+	esr = host_shared_data_get_realm_val(&realm, 0U, 7U, HOST_ARG2_INDEX);
+	far = host_shared_data_get_realm_val(&realm, 0U, 7U, HOST_ARG3_INDEX);
+
+	if ((EC_BITS(esr) != EC_DABORT_LOWER_EL) || (far != base)) {
+		ERROR("Rec7 incorrect ESR=0x%lx\n", esr);
+		goto undelegate_destroy;
+	}
+	INFO("Rec7 ESR=0x%lx\n", esr);
 	res = TEST_RESULT_SUCCESS;
 
 undelegate_destroy:
@@ -1406,21 +1843,25 @@
  * Then Host will inject SEA to realm.
  * Realm exception handler runs and returns ESR back to Host
  * Host validates ESR
+ * Repeat the test for Plane 1
+ * executing instructions in unprotected IPA causes plane exit to P0
+ * data access in unprotected IPA causes rec exit
+ * Host injects SEA to Plane N
  */
 test_result_t host_realm_sea_unprotected(void)
 {
 
 	bool ret1, ret2;
 	test_result_t res = TEST_RESULT_FAIL;
-	u_register_t ret, base, base_ipa, esr;
+	u_register_t ret, base, base_ipa, esr, far;
 	unsigned int host_call_result;
 	u_register_t exit_reason;
 	struct realm realm;
 	struct rtt_entry rtt;
 	struct rmi_rec_run *run;
-	u_register_t feature_flag0 = 0UL;
+	u_register_t feature_flag0 = 0UL, feature_flag1 = 0UL, num_aux_planes = 0U;
 	long sl = RTT_MIN_LEVEL;
-	u_register_t rec_flag[2U] = {RMI_RUNNABLE, RMI_RUNNABLE};
+	u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE};
 
 	SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
 
@@ -1429,8 +1870,19 @@
 		sl = RTT_MIN_LEVEL_LPA2;
 	}
 
+	/* Test are skipped if S2POE is not supported to keep test simple */
+	if (are_planes_supported() && is_single_rtt_supported()) {
+		num_aux_planes = 1UL;
+
+		/* use single RTT for all planes */
+		feature_flag0 |= INPLACE(RMI_FEATURE_REGISTER_0_PLANE_RTT,
+			RMI_PLANE_RTT_SINGLE);
+
+		feature_flag1 = RMI_REALM_FLAGS1_RTT_S2AP_ENCODING_INDIRECT;
+	}
+
 	if (!host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
-			feature_flag0, 0U, sl, rec_flag, 2U, 0U)) {
+			feature_flag0, feature_flag1, sl, rec_flag, 4U, num_aux_planes)) {
 		return TEST_RESULT_FAIL;
 	}
 
@@ -1447,8 +1899,8 @@
 	}
 
 	run = (struct rmi_rec_run *)realm.run[0];
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base_ipa);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base_ipa);
 
 	/* Rec0 expect SEA in realm due to IA unprotected IPA page */
 	ret1 = host_enter_realm_execute(&realm, REALM_INSTR_FETCH_CMD,
@@ -1503,6 +1955,88 @@
 	INFO("Rec1 ESR=0x%lx\n", esr);
 	res = host_call_result;
 
+	if (num_aux_planes == 0U) {
+		goto destroy_realm;
+	}
+
+	INFO("Running test on Plane 1\n");
+
+	run = (struct rmi_rec_run *)realm.run[2U];
+
+	/*
+	 * Arg for Plane0 instruction to enter Plane1 on Rec 2,3
+	 */
+	host_realm_set_aux_plane_args(&realm, 1U, 2U);
+	host_realm_set_aux_plane_args(&realm, 1U, 3U);
+
+
+	/* Test cmd for Plane 1 Rec 2/3 */
+	host_shared_data_set_realm_cmd(&realm, REALM_INSTR_FETCH_CMD, 1U, 2U);
+	host_shared_data_set_realm_cmd(&realm, REALM_DATA_ACCESS_CMD, 1U, 3U);
+
+	/*
+	 * Args for Plane1, Rec 2/3
+	 * Executing base_ipa from plane 1 rec 2, causes plane exit to P0
+	 * Data access from plane 1 rec 3, causes rec exit, host injects SEA
+	 */
+	host_shared_data_set_host_val(&realm, 1U, 2U, HOST_ARG3_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, 1U, 3U, HOST_ARG3_INDEX, base_ipa);
+
+	/* Rec2 expect plane exit to P0 due to IA unprotected IPA page */
+	ret1 = host_enter_realm_execute(&realm, REALM_PLANE_N_EXCEPTION_CMD,
+			RMI_EXIT_HOST_CALL, 2U);
+	if (!ret1) {
+		ERROR("Rec2 did not fault\n");
+		goto destroy_realm;
+	}
+
+	/* get ESR/FAR set by P0 */
+	esr = host_shared_data_get_realm_val(&realm, 0U, 2U, HOST_ARG2_INDEX);
+	far = host_shared_data_get_realm_val(&realm, 0U, 2U, HOST_ARG3_INDEX);
+
+	if (((EC_BITS(esr) != EC_IABORT_LOWER_EL) || (far != base_ipa))) {
+		ERROR("Rec2 incorrect ESR=0x%lx far=0x%lx\n", esr, far);
+		goto destroy_realm;
+	}
+	INFO("Rec2 ESR=0x%lx\n", esr);
+
+	run = (struct rmi_rec_run *)realm.run[3U];
+
+	/* Rec3 expect rec exit due to DA unprotected IPA page when HIPAS is UNASSIGNED_NS */
+	ret1 = host_enter_realm_execute(&realm, REALM_ENTER_PLANE_N_CMD,
+			RMI_EXIT_SYNC, 3U);
+
+	if (!ret1 || (run->exit.hpfar >> 4U) != (base_ipa >> PAGE_SIZE_SHIFT)
+		|| (EC_BITS(run->exit.esr) != EC_DABORT_LOWER_EL)
+		|| ((run->exit.esr & ISS_DFSC_MASK) < FSC_L0_TRANS_FAULT)
+		|| ((run->exit.esr & ISS_DFSC_MASK) > FSC_L3_TRANS_FAULT)
+		|| ((run->exit.esr & (1UL << ESR_ISS_EABORT_EA_BIT)) != 0U)) {
+		ERROR("Rec3 did not fault exit=0x%lx ret1=%d HPFAR=0x%lx esr=0x%lx\n",
+				run->exit.exit_reason, ret1, run->exit.hpfar, run->exit.esr);
+		goto destroy_realm;
+	}
+	INFO("Host DA FAR=0x%lx, HPFAR=0x%lx\n", run->exit.far, run->exit.hpfar);
+	INFO("Injecting SEA to Realm PN Rec3\n");
+
+	/* Inject SEA back to Realm P1 Rec3 */
+	run->entry.flags = REC_ENTRY_FLAG_INJECT_SEA;
+
+	/* Rec1 re-entry expect exception handler to run, return ESR */
+	ret = host_realm_rec_enter(&realm, &exit_reason, &host_call_result, 3U);
+	if (ret != RMI_SUCCESS || exit_reason != RMI_EXIT_HOST_CALL) {
+		ERROR("rec3 failed ret=0x%lx exit_reason=0x%lx", ret, run->exit.exit_reason);
+		goto destroy_realm;
+	}
+
+	/* get ESR/FAR set by Realm PN exception handler */
+	esr = host_shared_data_get_realm_val(&realm, 1U, 3U, HOST_ARG2_INDEX);
+	if (((esr & ISS_DFSC_MASK) != DFSC_NO_WALK_SEA) || (EC_BITS(esr) != EC_DABORT_CUR_EL)) {
+		ERROR("Rec3 incorrect ESR=0x%lx\n", esr);
+		goto destroy_realm;
+	}
+	INFO("Rec3 ESR=0x%lx\n", esr);
+	res = host_call_result;
+
 destroy_realm:
 	ret2 = host_destroy_realm(&realm);
 
@@ -2009,8 +2543,8 @@
 	/* IPA outside Realm space */
 	base_ipa = base | (1UL << (EXTRACT(RMI_FEATURE_REGISTER_0_S2SZ,
 					realm.rmm_feat_reg0) + 1U));
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG1_INDEX, base_ipa);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG1_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG3_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 1U, HOST_ARG3_INDEX, base_ipa);
 
 	INFO("base_ipa=0x%lx\n", base_ipa);
 
@@ -2061,8 +2595,8 @@
 
 	INFO("base_ipa=0x%lx\n", base_ipa);
 
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 2U, HOST_ARG1_INDEX, base_ipa);
-	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 3U, HOST_ARG1_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 2U, HOST_ARG3_INDEX, base_ipa);
+	host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 3U, HOST_ARG3_INDEX, base_ipa);
 
 	run = (struct rmi_rec_run *)realm.run[2];
 
@@ -2843,7 +3377,7 @@
 		return TEST_RESULT_FAIL;
 	}
 
-	host_shared_data_set_host_val(&realm, 0U, 0U, HOST_ARG1_INDEX, base);
+	host_shared_data_set_host_val(&realm, 0U, 0U, HOST_ARG3_INDEX, base);
 
 	for (unsigned int i = 0U; i < 2U; i++) {
 		host_shared_data_set_host_val(&realm, PRIMARY_PLANE_ID, 0U, HOST_ARG2_INDEX,
diff --git a/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c b/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
index 91e5307..98c567d 100644
--- a/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
+++ b/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
@@ -44,8 +44,8 @@
 em_cpu_t cortex_A15_errata_list = {
 	.cpu_pn = 0xC0F,
 	.cpu_errata = {
-		{816470, 0x30, 0xFF},
-		{827671, 0x30, 0xFF},
+		{816470, 0x30, 0xFF, 0x00},
+		{827671, 0x30, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -53,8 +53,8 @@
 em_cpu_t cortex_A17_errata_list = {
 	.cpu_pn = 0xC0E,
 	.cpu_errata = {
-		{852421, 0x00, 0x12},
-		{852423, 0x00, 0x12},
+		{852421, 0x00, 0x12, 0x00},
+		{852423, 0x00, 0x12, 0x00},
 		{-1}
 	},
 };
@@ -62,7 +62,7 @@
 em_cpu_t cortex_A9_errata_list = {
 	.cpu_pn = 0xC09,
 	.cpu_errata = {
-		{790473, 0x00, 0xFF},
+		{790473, 0x00, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -70,8 +70,8 @@
 em_cpu_t cortex_A35_errata_list = {
 	.cpu_pn = 0xD04,
 	.cpu_errata = {
-		{855472, 0x00, 0x00},
-		{1234567, 0x00, 0x00},
+		{855472, 0x00, 0x00, 0x00},
+		{1234567, 0x00, 0x00, 0x00},
 		{-1}
 	},
 };
@@ -79,15 +79,15 @@
 em_cpu_t cortex_A53_errata_list = {
 	.cpu_pn = 0xD03,
 	.cpu_errata = {
-		{819472, 0x00, 0x01},
-		{824069, 0x00, 0x02},
-		{826319, 0x00, 0x02},
-		{827319, 0x00, 0x02},
-		{835769, 0x00, 0x04},
-		{836870, 0x00, 0x03},
-		{843419, 0x00, 0x04},
-		{855873, 0x03, 0xFF},
-		{1530924, 0x00, 0xFF},
+		{819472, 0x00, 0x01, 0x00},
+		{824069, 0x00, 0x02, 0x00},
+		{826319, 0x00, 0x02, 0x00},
+		{827319, 0x00, 0x02, 0x00},
+		{835769, 0x00, 0x04, 0x00},
+		{836870, 0x00, 0x03, 0x00},
+		{843419, 0x00, 0x04, 0x00},
+		{855873, 0x03, 0xFF, 0x00},
+		{1530924, 0x00, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -95,13 +95,13 @@
 em_cpu_t cortex_A55_errata_list = {
 	.cpu_pn = 0xD05,
 	.cpu_errata = {
-		{768277, 0x00, 0x00},
-		{778703, 0x00, 0x00},
-		{798797, 0x00, 0x00},
-		{846532, 0x00, 0x01},
-		{903758, 0x00, 0x01},
-		{1221012, 0x00, 0x10},
-		{1530923, 0x00, 0xFF},
+		{768277, 0x00, 0x00, 0x00},
+		{778703, 0x00, 0x00, 0x00},
+		{798797, 0x00, 0x00, 0x00},
+		{846532, 0x00, 0x01, 0x00},
+		{903758, 0x00, 0x01, 0x00},
+		{1221012, 0x00, 0x10, 0x00},
+		{1530923, 0x00, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -109,18 +109,18 @@
 em_cpu_t cortex_A57_errata_list = {
 	.cpu_pn = 0xD07,
 	.cpu_errata = {
-		{806969, 0x00, 0x00},
-		{813419, 0x00, 0x00},
-		{813420, 0x00, 0x00},
-		{814670, 0x00, 0x00},
-		{817169, 0x00, 0x01},
-		{826974, 0x00, 0x11},
-		{826977, 0x00, 0x11},
-		{828024, 0x00, 0x11},
-		{829520, 0x00, 0x12},
-		{833471, 0x00, 0x12},
-		{859972, 0x00, 0x13},
-		{1319537, 0x00, 0xFF},
+		{806969, 0x00, 0x00, 0x00},
+		{813419, 0x00, 0x00, 0x00},
+		{813420, 0x00, 0x00, 0x00},
+		{814670, 0x00, 0x00, 0x00},
+		{817169, 0x00, 0x01, 0x00},
+		{826974, 0x00, 0x11, 0x00},
+		{826977, 0x00, 0x11, 0x00},
+		{828024, 0x00, 0x11, 0x00},
+		{829520, 0x00, 0x12, 0x00},
+		{833471, 0x00, 0x12, 0x00},
+		{859972, 0x00, 0x13, 0x00},
+		{1319537, 0x00, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -128,10 +128,10 @@
 em_cpu_t cortex_A72_errata_list = {
 	.cpu_pn = 0xD08,
 	.cpu_errata = {
-		{859971, 0x00, 0x03},
-		{1234567, 0x00, 0xFF},
-		{1319367, 0x00, 0xFF},
-		{9876543, 0x00, 0xFF},
+		{859971, 0x00, 0x03, 0x00},
+		{1234567, 0x00, 0xFF, 0x00},
+		{1319367, 0x00, 0xFF, 0x00},
+		{9876543, 0x00, 0xFF, 0x00},
 		{-1}
 	},
 };
@@ -139,8 +139,8 @@
 em_cpu_t cortex_A73_errata_list = {
 	.cpu_pn = 0xD09,
 	.cpu_errata = {
-		{852427, 0x00, 0x00},
-		{855423, 0x00, 0x01},
+		{852427, 0x00, 0x00, 0x00},
+		{855423, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -148,8 +148,8 @@
 em_cpu_t cortex_A75_errata_list = {
 	.cpu_pn = 0xD0A,
 	.cpu_errata = {
-		{764081, 0x00, 0x00},
-		{790748, 0x00, 0x00},
+		{764081, 0x00, 0x00, 0x00},
+		{790748, 0x00, 0x00, 0x00},
 		{-1}
 	},
 };
@@ -157,19 +157,19 @@
 em_cpu_t cortex_A76_errata_list = {
 	.cpu_pn = 0xD0B,
 	.cpu_errata = {
-		{1073348, 0x00, 0x10},
-		{1130799, 0x00, 0x20},
-		{1165522, 0x00, 0xFF},
-		{1220197, 0x00, 0x20},
-		{1257314, 0x00, 0x30},
-		{1262606, 0x00, 0x30},
-		{1262888, 0x00, 0x30},
-		{1275112, 0x00, 0x30},
-		{1286807, 0x00, 0x30},
-		{1791580, 0x00, 0x40},
-		{1868343, 0x00, 0x40},
-		{1946160, 0x30, 0x41},
-		{2743102, 0x00, 0x41},
+		{1073348, 0x00, 0x10, 0x00},
+		{1130799, 0x00, 0x20, 0x00},
+		{1165522, 0x00, 0xFF, 0x00},
+		{1220197, 0x00, 0x20, 0x00},
+		{1257314, 0x00, 0x30, 0x00},
+		{1262606, 0x00, 0x30, 0x00},
+		{1262888, 0x00, 0x30, 0x00},
+		{1275112, 0x00, 0x30, 0x00},
+		{1286807, 0x00, 0x30, 0x00},
+		{1791580, 0x00, 0x40, 0x00},
+		{1868343, 0x00, 0x40, 0x00},
+		{1946160, 0x30, 0x41, 0x00},
+		{2743102, 0x00, 0x41, 0x00},
 		{-1}
 	},
 };
@@ -177,13 +177,13 @@
 em_cpu_t cortex_A77_errata_list = {
 	.cpu_pn = 0xD0D,
 	.cpu_errata = {
-		{1508412, 0x00, 0x10},
-		{1791578, 0x00, 0x11},
-		{1800714, 0x00, 0x11},
-		{1925769, 0x00, 0x11},
-		{1946167, 0x00, 0x11},
-		{2356587, 0x00, 0x11},
-		{2743100, 0x00, 0x11},
+		{1508412, 0x00, 0x10, 0x00},
+		{1791578, 0x00, 0x11, 0x00},
+		{1800714, 0x00, 0x11, 0x00},
+		{1925769, 0x00, 0x11, 0x00},
+		{1946167, 0x00, 0x11, 0x00},
+		{2356587, 0x00, 0x11, 0x00},
+		{2743100, 0x00, 0x11, 0x00},
 		{-1}
 	},
 };
@@ -191,11 +191,11 @@
 em_cpu_t cortex_A78_AE_errata_list = {
 	.cpu_pn = 0xD42,
 	.cpu_errata = {
-		{1941500, 0x00, 0x01},
-		{1951502, 0x00, 0x01},
-		{2376748, 0x00, 0x01},
-		{2712574, 0x00, 0x02},
-		{2395408, 0x00, 0x01},
+		{1941500, 0x00, 0x01, 0x00},
+		{1951502, 0x00, 0x01, 0x00},
+		{2376748, 0x00, 0x01, 0x00},
+		{2712574, 0x00, 0x02, 0x00},
+		{2395408, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -203,19 +203,19 @@
 em_cpu_t cortex_A78_errata_list = {
 	.cpu_pn = 0xD41,
 	.cpu_errata = {
-		{1688305, 0x00, 0x10},
-		{1821534, 0x00, 0x10},
-		{1941498, 0x00, 0x11},
-		{1951500, 0x10, 0x11},
-		{1952683, 0x00, 0x00},
-		{2132060, 0x00, 0x12},
-		{2242635, 0x10, 0x12},
-		{2376745, 0x00, 0x12},
-		{2395406, 0x00, 0x12},
-		{2712571, 0x00, 0x12},
-		{2742426, 0x00, 0x12},
-		{2772019, 0x00, 0x12},
-		{2779479, 0x00, 0x12},
+		{1688305, 0x00, 0x10, 0x00},
+		{1821534, 0x00, 0x10, 0x00},
+		{1941498, 0x00, 0x11, 0x00},
+		{1951500, 0x10, 0x11, 0x00},
+		{1952683, 0x00, 0x00, 0x00},
+		{2132060, 0x00, 0x12, 0x00},
+		{2242635, 0x10, 0x12, 0x00},
+		{2376745, 0x00, 0x12, 0x00},
+		{2395406, 0x00, 0x12, 0x00},
+		{2712571, 0x00, 0x12, 0x00},
+		{2742426, 0x00, 0x12, 0x00},
+		{2772019, 0x00, 0x12, 0x00},
+		{2779479, 0x00, 0x12, 0x00},
 		{-1}
 	},
 };
@@ -223,17 +223,17 @@
 em_cpu_t cortex_A78C_errata_list = {
 	.cpu_pn = 0xD4B,
 	.cpu_errata = {
-		{1827430, 0x00, 0x00},
-		{1827440, 0x00, 0x00},
-		{2132064, 0x01, 0x02},
-		{2242638, 0x01, 0x02},
-		{2376749, 0x01, 0x02},
-		{2395411, 0x01, 0x02},
-		{2683027, 0x01, 0x02},
-		{2712575, 0x01, 0x02},
-		{2743232, 0x01, 0x02},
-		{2772121, 0x00, 0x02},
-		{2779484, 0x01, 0x02},
+		{1827430, 0x00, 0x00, 0x00},
+		{1827440, 0x00, 0x00, 0x00},
+		{2132064, 0x01, 0x02, 0x00},
+		{2242638, 0x01, 0x02, 0x00},
+		{2376749, 0x01, 0x02, 0x00},
+		{2395411, 0x01, 0x02, 0x00},
+		{2683027, 0x01, 0x02, 0x00},
+		{2712575, 0x01, 0x02, 0x00},
+		{2743232, 0x01, 0x02, 0x00},
+		{2772121, 0x00, 0x02, 0x00},
+		{2779484, 0x01, 0x02, 0x00},
 		{-1}
 	},
 };
@@ -242,9 +242,9 @@
 em_cpu_t cortex_X1_errata_list = {
 	.cpu_pn = 0xD44,
 	.cpu_errata = {
-		{1688305, 0x00, 0x10},
-		{1821534, 0x00, 0x10},
-		{1827429, 0x00, 0x10},
+		{1688305, 0x00, 0x10, 0x00},
+		{1821534, 0x00, 0x10, 0x00},
+		{1827429, 0x00, 0x10, 0x00},
 		{-1}
 	},
 
@@ -253,21 +253,21 @@
 em_cpu_t neoverse_N1_errata_list = {
 	.cpu_pn = 0xD0C,
 	.cpu_errata = {
-		{1043202, 0x00, 0x10},
-		{1073348, 0x00, 0x10},
-		{1130799, 0x00, 0x20},
-		{1165347, 0x00, 0x20},
-		{1207823, 0x00, 0x20},
-		{1220197, 0x00, 0x20},
-		{1257314, 0x00, 0x30},
-		{1262606, 0x00, 0x30},
-		{1262888, 0x00, 0x30},
-		{1275112, 0x00, 0x30},
-		{1315703, 0x00, 0x30},
-		{1542419, 0x30, 0x40},
-		{1868343, 0x00, 0x40},
-		{1946160, 0x30, 0x41},
-		{2743102, 0x00, 0x41},
+		{1043202, 0x00, 0x10, 0x00},
+		{1073348, 0x00, 0x10, 0x00},
+		{1130799, 0x00, 0x20, 0x00},
+		{1165347, 0x00, 0x20, 0x00},
+		{1207823, 0x00, 0x20, 0x00},
+		{1220197, 0x00, 0x20, 0x00},
+		{1257314, 0x00, 0x30, 0x00},
+		{1262606, 0x00, 0x30, 0x00},
+		{1262888, 0x00, 0x30, 0x00},
+		{1275112, 0x00, 0x30, 0x00},
+		{1315703, 0x00, 0x30, 0x00},
+		{1542419, 0x30, 0x40, 0x01},
+		{1868343, 0x00, 0x40, 0x00},
+		{1946160, 0x30, 0x41, 0x00},
+		{2743102, 0x00, 0x41, 0x00},
 		{-1}
 	},
 };
@@ -275,23 +275,23 @@
 em_cpu_t neoverse_V1_errata_list = {
 	.cpu_pn = 0xD40,
 	.cpu_errata = {
-		{1618635, 0x00, 0x0F},
-		{1774420, 0x00, 0x10},
-		{1791573, 0x00, 0x10},
-		{1852267, 0x00, 0x10},
-		{1925756, 0x00, 0x11},
-		{1940577, 0x10, 0x11},
-		{1966096, 0x10, 0x11},
-		{2108267, 0x00, 0x11},
-		{2139242, 0x00, 0x11},
-		{2216392, 0x10, 0x11},
-		{2294912, 0x00, 0x11},
-		{2348377, 0x00, 0x11},
-		{2372203, 0x00, 0x11},
-		{2701953, 0x00, 0x11},
-		{2743093, 0x00, 0x12},
-		{2743233, 0x00, 0x12},
-		{2779461, 0x00, 0x12},
+		{1618635, 0x00, 0x0F, 0x00},
+		{1774420, 0x00, 0x10, 0x00},
+		{1791573, 0x00, 0x10, 0x00},
+		{1852267, 0x00, 0x10, 0x00},
+		{1925756, 0x00, 0x11, 0x00},
+		{1940577, 0x10, 0x11, 0x00},
+		{1966096, 0x10, 0x11, 0x00},
+		{2108267, 0x00, 0x11, 0x00},
+		{2139242, 0x00, 0x11, 0x00},
+		{2216392, 0x10, 0x11, 0x00},
+		{2294912, 0x00, 0x11, 0x00},
+		{2348377, 0x00, 0x11, 0x00},
+		{2372203, 0x00, 0x11, 0x00},
+		{2701953, 0x00, 0x11, 0x00},
+		{2743093, 0x00, 0x12, 0x00},
+		{2743233, 0x00, 0x12, 0x00},
+		{2779461, 0x00, 0x12, 0x00},
 		{-1}
 	},
 };
@@ -299,24 +299,24 @@
 em_cpu_t cortex_A710_errata_list = {
 	.cpu_pn = 0xD47,
 	.cpu_errata = {
-		{1987031, 0x00, 0x20},
-		{2008768, 0x00, 0x20},
-		{2017096, 0x00, 0x20},
-		{2055002, 0x10, 0x20},
-		{2058056, 0x00, 0x10},
-		{2081180, 0x00, 0x20},
-		{2083908, 0x20, 0x20},
-		{2136059, 0x00, 0x20},
-		{2147715, 0x20, 0x20},
-		{2216384, 0x00, 0x20},
-		{2267065, 0x00, 0x20},
-		{2282622, 0x00, 0x21},
-		{2291219, 0x00, 0x20},
-		{2371105, 0x00, 0x20},
-		{2701952, 0x00, 0x21},
-		{2742423, 0x00, 0x21},
-		{2768515, 0x00, 0x21},
-		{2778471, 0x00, 0x21},
+		{1987031, 0x00, 0x20, 0x00},
+		{2008768, 0x00, 0x20, 0x00},
+		{2017096, 0x00, 0x20, 0x00},
+		{2055002, 0x10, 0x20, 0x00},
+		{2058056, 0x00, 0x10, 0x00},
+		{2081180, 0x00, 0x20, 0x00},
+		{2083908, 0x20, 0x20, 0x00},
+		{2136059, 0x00, 0x20, 0x00},
+		{2147715, 0x20, 0x20, 0x00},
+		{2216384, 0x00, 0x20, 0x00},
+		{2267065, 0x00, 0x20, 0x00},
+		{2282622, 0x00, 0x21, 0x00},
+		{2291219, 0x00, 0x20, 0x00},
+		{2371105, 0x00, 0x20, 0x00},
+		{2701952, 0x00, 0x21, 0x00},
+		{2742423, 0x00, 0x21, 0x00},
+		{2768515, 0x00, 0x21, 0x00},
+		{2778471, 0x00, 0x21, 0x00},
 		{-1}
 	},
 };
@@ -324,22 +324,22 @@
 em_cpu_t neoverse_N2_errata_list = {
 	.cpu_pn = 0xD49,
 	.cpu_errata = {
-		{2002655, 0x00, 0x00},
-		{2025414, 0x00, 0x00},
-		{2067956, 0x00, 0x00},
-		{2138953, 0x00, 0x00},
-		{2138956, 0x00, 0x00},
-		{2138958, 0x00, 0x00},
-		{2189731, 0x00, 0x00},
-		{2242400, 0x00, 0x00},
-		{2242415, 0x00, 0x00},
-		{2280757, 0x00, 0x00},
-		{2326639, 0x00, 0x00},
-		{2376738, 0x00, 0x00},
-		{2388450, 0x00, 0x00},
-		{2728475, 0x00, 0x02},
-		{2743089, 0x00, 0x02},
-		{2779511, 0x00, 0x02},
+		{2002655, 0x00, 0x00, 0x00},
+		{2025414, 0x00, 0x00, 0x00},
+		{2067956, 0x00, 0x00, 0x00},
+		{2138953, 0x00, 0x00, 0x00},
+		{2138956, 0x00, 0x00, 0x00},
+		{2138958, 0x00, 0x00, 0x00},
+		{2189731, 0x00, 0x00, 0x00},
+		{2242400, 0x00, 0x00, 0x00},
+		{2242415, 0x00, 0x00, 0x00},
+		{2280757, 0x00, 0x00, 0x00},
+		{2326639, 0x00, 0x00, 0x00},
+		{2376738, 0x00, 0x00, 0x00},
+		{2388450, 0x00, 0x00, 0x00},
+		{2728475, 0x00, 0x02, 0x00},
+		{2743089, 0x00, 0x02, 0x00},
+		{2779511, 0x00, 0x02, 0x00},
 		{-1}
 	},
 };
@@ -347,19 +347,19 @@
 em_cpu_t cortex_X2_errata_list = {
 	.cpu_pn = 0xD48,
 	.cpu_errata = {
-		{2002765, 0x00, 0x20},
-		{2017096, 0x00, 0x20},
-		{2058056, 0x00, 0x20},
-		{2081180, 0x00, 0x20},
-		{2083908, 0x00, 0x20},
-		{2147715, 0x20, 0x20},
-		{2216384, 0x00, 0x20},
-		{2282622, 0x00, 0x21},
-		{2371105, 0x00, 0x21},
-		{2701952, 0x00, 0x21},
-		{2742423, 0x00, 0x21},
-		{2768515, 0x00, 0x21},
-		{2778471, 0x00, 0x21},
+		{2002765, 0x00, 0x20, 0x00},
+		{2017096, 0x00, 0x20, 0x00},
+		{2058056, 0x00, 0x20, 0x00},
+		{2081180, 0x00, 0x20, 0x00},
+		{2083908, 0x00, 0x20, 0x00},
+		{2147715, 0x20, 0x20, 0x00},
+		{2216384, 0x00, 0x20, 0x00},
+		{2282622, 0x00, 0x21, 0x00},
+		{2371105, 0x00, 0x21, 0x00},
+		{2701952, 0x00, 0x21, 0x00},
+		{2742423, 0x00, 0x21, 0x00},
+		{2768515, 0x00, 0x21, 0x00},
+		{2778471, 0x00, 0x21, 0x00},
 		{-1}
 	},
 };
@@ -367,19 +367,19 @@
 em_cpu_t cortex_A510_errata_list = {
 	.cpu_pn = 0xD46,
 	.cpu_errata = {
-		{1922240, 0x00, 0x00},
-		{2041909, 0x02, 0x02},
-		{2042739, 0x00, 0x02},
-		{2080326, 0x02, 0x02},
-		{2172148, 0x00, 0x10},
-		{2218950, 0x00, 0x10},
-		{2250311, 0x00, 0x10},
-		{2288014, 0x00, 0x10},
-		{2347730, 0x00, 0x11},
-		{2371937, 0x00, 0x11},
-		{2666669, 0x00, 0x11},
-		{2684597, 0x00, 0x12},
-		{1234567, 0x00, 0x12},
+		{1922240, 0x00, 0x00, 0x00},
+		{2041909, 0x02, 0x02, 0x00},
+		{2042739, 0x00, 0x02, 0x00},
+		{2080326, 0x02, 0x02, 0x00},
+		{2172148, 0x00, 0x10, 0x00},
+		{2218950, 0x00, 0x10, 0x00},
+		{2250311, 0x00, 0x10, 0x00},
+		{2288014, 0x00, 0x10, 0x00},
+		{2347730, 0x00, 0x11, 0x00},
+		{2371937, 0x00, 0x11, 0x00},
+		{2666669, 0x00, 0x11, 0x00},
+		{2684597, 0x00, 0x12, 0x00},
+		{1234567, 0x00, 0x12, 0x00},
 		{-1}
 	},
 };
@@ -387,14 +387,14 @@
 em_cpu_t cortex_X4_errata_list = {
 	.cpu_pn = 0xD82,
 	.cpu_errata = {
-		{2726228, 0x00, 0x01},
-		{2740089, 0x00, 0x01},
-		{2763018, 0x00, 0x01},
-		{2816013, 0x00, 0x01},
-		{2897503, 0x00, 0x01},
-		{2923985, 0x00, 0x01},
-		{2957258, 0x00, 0x01},
-		{3076789, 0x00, 0x01},
+		{2726228, 0x00, 0x01, 0x00},
+		{2740089, 0x00, 0x01, 0x00},
+		{2763018, 0x00, 0x01, 0x00},
+		{2816013, 0x00, 0x01, 0x00},
+		{2897503, 0x00, 0x01, 0x00},
+		{2923985, 0x00, 0x01, 0x00},
+		{2957258, 0x00, 0x01, 0x00},
+		{3076789, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -402,8 +402,8 @@
 em_cpu_t cortex_X925_errata_list = {
 	.cpu_pn = 0xD85,
 	.cpu_errata = {
-		{2963999, 0x00, 0x00},
-		{3701747, 0x00, 0x01},
+		{2963999, 0x00, 0x00, 0x00},
+		{3701747, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -411,7 +411,7 @@
 em_cpu_t cortex_A715_errata_list = {
 	.cpu_pn = 0xD4D,
 	.cpu_errata = {
-		{2561034, 0x10, 0x10},
+		{2561034, 0x10, 0x10, 0x00},
 		{-1}
 	},
 };
@@ -419,15 +419,15 @@
 em_cpu_t neoverse_V2_errata_list = {
 	.cpu_pn = 0xD4F,
 	.cpu_errata = {
-		{2331132, 0x00, 0x02},
-		{2618597, 0x00, 0x01},
-		{2662553, 0x00, 0x01},
-		{2719103, 0x00, 0x01},
-		{2719103, 0x00, 0x01},
-		{2719105, 0x00, 0x01},
-		{2743011, 0x00, 0x01},
-		{2779510, 0x00, 0x01},
-		{2801372, 0x00, 0x01},
+		{2331132, 0x00, 0x02, 0x00},
+		{2618597, 0x00, 0x01, 0x00},
+		{2662553, 0x00, 0x01, 0x00},
+		{2719103, 0x00, 0x01, 0x00},
+		{2719103, 0x00, 0x01, 0x00},
+		{2719105, 0x00, 0x01, 0x00},
+		{2743011, 0x00, 0x01, 0x00},
+		{2779510, 0x00, 0x01, 0x00},
+		{2801372, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -435,16 +435,16 @@
 em_cpu_t cortex_X3_errata_list = {
 	.cpu_pn = 0xD4E,
 	.cpu_errata = {
-		{2070301, 0x00, 0x12},
-		{2266875, 0x00, 0x10},
-		{2302506, 0x00, 0x11},
-		{2313909, 0x00, 0x10},
-		{2615812, 0x00, 0x11},
-		{2641945, 0x00, 0x10},
-		{2701951, 0x00, 0x11},
-		{2742421, 0x00, 0x11},
-		{2743088, 0x00, 0x11},
-		{2779509, 0x00, 0x11},
+		{2070301, 0x00, 0x12, 0x00},
+		{2266875, 0x00, 0x10, 0x00},
+		{2302506, 0x00, 0x11, 0x00},
+		{2313909, 0x00, 0x10, 0x00},
+		{2615812, 0x00, 0x11, 0x00},
+		{2641945, 0x00, 0x10, 0x00},
+		{2701951, 0x00, 0x11, 0x00},
+		{2742421, 0x00, 0x11, 0x00},
+		{2743088, 0x00, 0x11, 0x00},
+		{2779509, 0x00, 0x11, 0x00},
 		{-1}
 	},
 };
@@ -452,8 +452,8 @@
 em_cpu_t cortex_A520_errata_list = {
 	.cpu_pn = 0xD80,
 	.cpu_errata = {
-		{2630792, 0x00, 0x01},
-		{2858100, 0x00, 0x01},
+		{2630792, 0x00, 0x01, 0x00},
+		{2858100, 0x00, 0x01, 0x00},
 		{-1}
 	},
 };
@@ -514,6 +514,10 @@
 
 	INFO("Partnum extracted = %x and rxpx extracted val = %x\n\n", midr_val, \
 							rxpx_val_extracted);
+
+	/* Signal to the lead CPU that the calling CPU has entered the test */
+	tftf_send_event(&cpu_has_entered_test[core_pos]);
+
 	switch (midr_val) {
 	case 0xD09:
 	{
@@ -695,9 +699,11 @@
 		}
 		case EM_HIGHER_EL_MITIGATION:
 		{
-			return_val = (RXPX_RANGE(rxpx_val_extracted, \
+			return_val = ((RXPX_RANGE(rxpx_val_extracted, \
 			cpu_ptr->cpu_errata[i].rxpx_low, cpu_ptr->cpu_errata[i].rxpx_high) \
-				== true) ? TEST_RESULT_SUCCESS : TEST_RESULT_FAIL;
+				== true) && (!cpu_ptr->cpu_errata[i].split_wa)) ? \
+				     TEST_RESULT_SUCCESS : TEST_RESULT_FAIL;
+
 			break;
 		}
 		case EM_UNKNOWN_ERRATUM:
@@ -714,9 +720,11 @@
 		}
 		INFO("errata_id = %d and test_em_cpu_erratum_features = %ld\n",\
 			cpu_ptr->cpu_errata[i].em_errata_id, ret_val.ret0);
+
+		if(return_val == TEST_RESULT_FAIL)
+			return TEST_RESULT_FAIL;
 	}
-	/* Signal to the lead CPU that the calling CPU has entered the test */
-	tftf_send_event(&cpu_has_entered_test[core_pos]);
+
 	return return_val;
 }
 
@@ -728,6 +736,8 @@
 
 	int32_t version_return = tftf_em_abi_version();
 
+	test_result_t return_val = TEST_RESULT_FAIL;
+
 	SKIP_TEST_IF_LESS_THAN_N_CPUS(1);
 
 	if (version_return == EM_NOT_SUPPORTED) {
@@ -738,6 +748,9 @@
 		return TEST_RESULT_FAIL;
 	}
 
+	/* Run test on lead cpu */
+	return_val = test_em_cpu_features();
+
 	lead_mpid = read_mpidr_el1() & MPID_MASK;
 	/* Power on all CPUs */
 	for_each_cpu(cpu_node) {
@@ -757,5 +770,5 @@
 		core_pos = platform_get_core_pos(cpu_mpid);
 		tftf_wait_for_event(&cpu_has_entered_test[core_pos]);
 	}
-	return TEST_RESULT_SUCCESS;
+	return return_val;
 }
diff --git a/tftf/tests/tests-realm-payload.xml b/tftf/tests/tests-realm-payload.xml
index 277e6db..92eaf5a 100644
--- a/tftf/tests/tests-realm-payload.xml
+++ b/tftf/tests/tests-realm-payload.xml
@@ -14,6 +14,8 @@
 	  function="host_test_realm_create_planes_enter_single_rtt" />
 	  <testcase name="Realm Planes register read/write test"
 	  function="host_test_realm_create_planes_register_rw" />
+	  <testcase name="Realm payload Planes multi rec multiple cpu"
+	  function="host_realm_multi_planes_multi_rec_multiple_cpu" />
 	  <testcase name="Realm EL1 creation and execution test"
 	  function="host_test_realm_create_enter" />
 	  <testcase name="Realm RTT fold unfold test Unassigned Empty"