refactor(tftf): move SIMD/FPU save/restore routine to common lib
- Move FPU routines to common lib
- FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers
- Test that FPU/SIMD state are preserved during a context switch
between secure/non-secure.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I88f0a9f716aafdd634c4eae5b885f839bb3deb00
diff --git a/include/runtime_services/spm_common.h b/include/runtime_services/spm_common.h
index 6fe445a..7f47dc7 100644
--- a/include/runtime_services/spm_common.h
+++ b/include/runtime_services/spm_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,27 +97,15 @@
void dump_ffa_value(struct ffa_value ret);
/*
- * Max. vector length:
- * SIMD: 128 bits = 16 bytes
- */
-#define SIMD_VECTOR_LEN_BYTES 16
-
-#define SIMD_NUM_VECTORS 32
-
-typedef uint8_t simd_vector_t[SIMD_VECTOR_LEN_BYTES];
-
-/*
* Fills SIMD/SVE registers with the content of the container v.
* Number of vectors is assumed to be SIMD/SVE_NUM_VECTORS.
*/
-void fill_simd_vector_regs(const simd_vector_t v[SIMD_NUM_VECTORS]);
void fill_sve_vector_regs(const sve_vector_t v[SVE_NUM_VECTORS]);
/*
* Reads contents of SIMD/SVE registers into the provided container v.
* Number of vectors is assumed to be SIMD/SVE_NUM_VECTORS.
*/
-void read_simd_vector_regs(simd_vector_t v[SIMD_NUM_VECTORS]);
void read_sve_vector_regs(sve_vector_t v[SVE_NUM_VECTORS]);
bool check_spmc_execution_level(void);