Infineon: Add support for the CYW89829 B1 revision and the GCC 14 compiler
diff --git a/boot/bootutil/src/loader.c b/boot/bootutil/src/loader.c
index e441b56..8abb037 100644
--- a/boot/bootutil/src/loader.c
+++ b/boot/bootutil/src/loader.c
@@ -4351,7 +4351,33 @@
boot_get_slot_state(uint32_t image_id, uint32_t slot_id, boot_slot_state_t* state)
{
int rc = 0;
+ const struct flash_area *fap = NULL;
+ struct image_header hdr;
+ int area_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ /* Read the image header */
+ rc = flash_area_open(area_id, &fap);
+ if (rc != 0) {
+ rc = -1;
+ *state = MCUBOOT_SLOT_STATE_NO_IMAGE;
+ goto out;
+ }
+
+ rc = flash_area_read(fap, 0, &hdr, sizeof(hdr));
+ if (rc != 0) {
+ rc = -1;
+ *state = MCUBOOT_SLOT_STATE_NO_IMAGE;
+ goto out;
+ }
+
+ /* Verify ih_magic */
+ if (!boot_is_header_valid(&hdr, fap)) {
+ rc = -1;
+ *state = MCUBOOT_SLOT_STATE_NO_IMAGE;
+ goto out;
+ }
+
+ /* Header is valid, proceed with normal state checking */
if (boot_is_slot_inactive(image_id, slot_id) == 1)
{
*state = MCUBOOT_SLOT_STATE_INACTIVE;
@@ -4369,6 +4395,12 @@
*state = MCUBOOT_SLOT_STATE_ACTIVE;
}
+ rc = 0;
+
+out:
+ if (fap != NULL) {
+ flash_area_close(fap);
+ }
return rc;
}
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index 7fec277..796f49a 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -57,9 +57,9 @@
Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE**:
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1
The supported platforms:
@@ -131,7 +131,7 @@
make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single_smif.json IMG_ID=1
-`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20829` default value is `0xff` since it only uses an external flash.
+`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For CYW20829/CYW89829 default value is `0xff` since it only uses an external flash.
In the multi-image configuration, an upgrade image for the second application is built using the command:
@@ -174,7 +174,7 @@
- `0xff` - External memory.
- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for the build.
- Example: TOOLCHAIN_PATH=/opt/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
- - Example: TOOLCHAIN_PATH=C:/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ - Example: TOOLCHAIN_PATH=C:/Infineon/Tools/mtb-gcc-arm-eabi/14.2.1/gcc
Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/memorymap.mk`.
@@ -194,7 +194,7 @@
Flags passed to `imgtool` for a signature are defined in the `SIGN_ARGS` variable in BlinkyApp.mk.
-For `CYWxx829` and `XMC7x00` platforms, `edgeprotecttools` is used for the image signing.
+For CYW20829/CYW89829 and XMC7100/XMC7200 platforms, `edgeprotecttools` is used for the image signing.
### How to program an application
@@ -204,11 +204,11 @@
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.5\openocd` folder.
Open the terminal application and execute the following commands:
- export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
index 2a450fa..96eda68 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
@@ -1,5 +1,5 @@
/***************************************************************************//**
-* \file xmc7200d_x8384_cm7.ld
+* \file xmc7100d_x4160_cm7.ld
* \version 1.0.0
*
* Linker file for the GNU C compiler.
@@ -50,16 +50,18 @@
sram_start_reserve = 0;
-sram_total_size = 0x00100000; /* SRAM0 + SRAM1 */
+sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */
sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
-cm0plus_sram_reserve = 0x00020000; /* cm0 sram size */
-cm7_0_sram_reserve = 0x00060000; /* cm7_0 sram size */
+cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+cm7_1_sram_reserve = 0x00010000; /* 64K : cm7_1 sram size */
+cm7_sram_non_cache_reserve = 0x00020000; /* 128K : non-cacheable sram size */
+cm7_0_sram_reserve = sram_total_size - cm0plus_sram_reserve - cm7_1_sram_reserve - cm7_sram_non_cache_reserve; /* 560k : cm7_0 sram size */
-code_flash_total_size = 0x00830000;
-cm0plus_code_flash_reserve = 0x00080000;
-cm7_0_code_flash_reserve = 0x00200000;
+code_flash_total_size = 0x00410000; /* 4160K: total flash size */
+cm0plus_code_flash_reserve = 0x00020000; /* 128K : cm0 flash size */
+cm7_0_code_flash_reserve = 0x00200000; /* 2048K: cm7_0 flash size */
code_flash_base_address = 0x10000000;
sram_base_address = 0x28000000;
@@ -69,7 +71,10 @@
_size_SRAM_CM7_0 = cm7_0_sram_reserve;
/* In case of single CM7 device CM7_1 values should not be used */
_base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
-_size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+_size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve - cm7_sram_non_cache_reserve; /* 64K: cm7_1 sram size */
+
+_base_SRAM_NON_CACHE = _base_SRAM_CM7_1 + _size_SRAM_CM7_1;
+_size_SRAM_NON_CACHE = cm7_sram_non_cache_reserve;
/* Code flash reservations */
_base_CODE_FLASH_CM0P = code_flash_base_address;
@@ -82,13 +87,13 @@
/* Fixed Addresses */
_base_WORK_FLASH = 0x14000000;
_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
-_base_CM7_0_ITCM = 0xA0000000;
+_base_CM7_0_ITCM = 0x00000000;
_size_CM7_0_ITCM = 0x00004000;
-_base_CM7_0_DTCM = 0xA0010000;
+_base_CM7_0_DTCM = 0x20000000;
_size_CM7_0_DTCM = 0x00004000;
-_base_CM7_1_ITCM = 0xA0100000;
+_base_CM7_1_ITCM = 0x00000000;
_size_CM7_1_ITCM = 0x00004000;
-_base_CM7_1_DTCM = 0xA0110000;
+_base_CM7_1_DTCM = 0x20000000;
_size_CM7_1_DTCM = 0x00004000;
/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
@@ -130,9 +135,10 @@
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
- ram (rxw) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE /* SRAM */
- flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
- flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE /* CODE flash CM7_0/1 */
+ ram (rxw) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE /* SRAM values will be set by a pre-build script */
+ ram_noncache (rxw) : ORIGIN = _base_SRAM_NON_CACHE, LENGTH = _size_SRAM_NON_CACHE /* Non-Cacheable SRAM */
+ flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
+ flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE /* CODE flash CM7_0/1 values will be set by a pre-build script */
/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
@@ -230,6 +236,21 @@
LONG (__data_start__) /* To */
LONG ((__data_end__ - __data_start__)/4) /* Size */
+ /* Copy data section to noncache RAM */
+ LONG (__noncache_ramdata_lma_start__) /* From */
+ LONG (__noncacheable_ram_start__) /* To */
+ LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4) /* Size */
+
+ /* Copy code to ITCM */
+ LONG (__zero_table_end__) /* From */
+ LONG (__itcm_start__) /* To */
+ LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
+
+ /* Copy data to DTCM */
+ LONG (__itcm_flash_end__) /* From */
+ LONG (__dtcm_start__) /* To */
+ LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
+
__copy_table_end__ = .;
} > flash
@@ -243,7 +264,25 @@
__zero_table_end__ = .;
} > flash
- __etext = . ;
+ /* itcm */
+ .cy_itcm ORIGIN(itcm):
+ {
+ __itcm_start__ = .;
+ KEEP(*(.cy_itcm))
+ __itcm_end__ = .;
+ } > itcm AT>flash
+
+ __itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
+
+ /* dtcm */
+ .cy_dtcm ORIGIN(dtcm):
+ {
+ __dtcm_start__ = .;
+ KEEP(*(.cy_dtcm))
+ __dtcm_end__ = .;
+ } > dtcm AT>flash
+
+ __etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
.ramVectors (NOLOAD) :
@@ -289,13 +328,21 @@
KEEP(*(.cy_ramfunc*))
. = ALIGN(32);
- KEEP(*(cy_sharedmem*))
- . = ALIGN(4);
-
__data_end__ = .;
} > ram AT>flash
+ __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+ .ram_noncache :
+ {
+ . = ALIGN(32);
+ __noncacheable_ram_start__ = .;
+ *(.cy_sharedmem)
+ . = ALIGN(4);
+ __noncacheable_ram_end__ = .;
+ } > ram_noncache AT>flash
+
/* Place variables in the section that should not be initialized during the
* device startup.
@@ -352,7 +399,7 @@
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ __StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
@@ -409,18 +456,6 @@
{
KEEP(*(.cy_efuse))
} > efuse
-
- /* itcm */
- .cy_itcm :
- {
- KEEP(*(.cy_itcm))
- } > itcm
-
- /* dtcm */
- .cy_dtcm :
- {
- KEEP(*(.cy_dtcm))
- } > dtcm
}
diff --git a/boot/cypress/Changelog.md b/boot/cypress/Changelog.md
new file mode 100644
index 0000000..33a475c
--- /dev/null
+++ b/boot/cypress/Changelog.md
@@ -0,0 +1,19 @@
+# Changelog
+This document provides a record of the most recent principal changes to the Infineon MCUBoot project.
+
+## 1.9.7
+- Added support for CYW89829 B1 silicon.
+- Added support for the GCC 14 compiler.
+
+## 1.9.6
+- Implemented the Direct-XIP feature for CYW20829 devices.
+- Added APIs for Direct-XIP mode.
+
+## 1.9.5
+- Added support for the PSOC C3 family.
+- Fixed a hang in MCUBoot for images with an invalid header.
+
+## 1.9.4
+- Added support for SMIF encryption in Secure Mode for CYW20829 devices.
+- Improved the MCUBoot application's boot time.
+
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index 72e435f..cb82814 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -100,7 +100,7 @@
The MCUBootApp can be programmed similarly to described in the [MCUBootApp.md](MCUBootApp.md) file:
- export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index 883b8a3..256d0ff 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -2,7 +2,7 @@
### Solution description
-This solution demonstrates the operation of MCUboot on Cypress PSoC™ 6 and CYWxx829 devices.
+This solution demonstrates the operation of MCUboot on PSOC™ 6, CYW20829/CYW89829 and XMC7100/XMC7200 devices.
* Single-/Multi-image operation modes
* Overwrite/Swap upgrade modes
@@ -399,7 +399,7 @@
#### External flash
-Some Cypress devices, for example, `CYW20829`, only have an external flash, so all memory areas are located in an external flash.
+Some devices, such as CYW20829/CYW89829, only have an external flash, so all memory areas are located in an external flash.
However, PSoC™ 6 chips have internal flash and, additionally, support the external memory connection. Thus, it is possible to place secondary (upgrade) slots in the external memory module and use most of the internal flash for the primary image.
For more details on External Memory usage, refer to the [ExternalMemory.md](ExternalMemory.md) file.
@@ -643,7 +643,7 @@
Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ Programming Tools**:
- make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
* Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
@@ -720,7 +720,7 @@
`MCUBOOT_LOG_LEVEL` - Can be set at `MCUBOOT_LOG_LEVEL_DEBUG` to enable the verbose output of MCUBootApp.
`ENC_IMG` - When set to `1`, it enables the encrypted image support in MCUBootApp.
-`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYWxx829 platforms.
+`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYW20829/CYW89829 platforms.
`USE_BOOTSTRAP` - When set to `1` and Swap mode is enabled, the application in the secondary slot will overwrite the primary slot if the primary slot application is invalid.
`USE_CRYPTO_HW` - When set to `1`, uses the hardware-accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20829/CYW89829 platforms.
`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829/CYW89829 chips only).
@@ -741,7 +741,7 @@
1. The direct usage of OpenOCD.
-The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder. Commands for programming images are provided in the corresponding platform readme files.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.5\openocd` folder. Commands for programming images are provided in the corresponding platform readme files.
2. Using the GUI tool `Cypress Programmer`
diff --git a/boot/cypress/MCUBootApp/README.md b/boot/cypress/MCUBootApp/README.md
index 59e6e87..f074c9e 100644
--- a/boot/cypress/MCUBootApp/README.md
+++ b/boot/cypress/MCUBootApp/README.md
@@ -175,11 +175,11 @@
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
-The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.5\openocd` folder.
Open the terminal application and execute the following commands:
- export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index 9c78f6b..1b9f42a 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -64,10 +64,14 @@
The default installation folder is expected by the makefile build system.To use another installation folder, version of **ModusToolbox™ Programming Tools** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
-Below is an example on how to set toolchain path:
+Below is an example on how to set toolchain path using GCC 11 on Windows:
make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+or GCC 14 on Ubuntu Linux:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=/opt/Tools/mtb-gcc-arm-eabi/14.2.1/gcc
+
### Build environment troubleshooting
Following CLI / IDE are supported for project build:
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index 5abd167..f12629f 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -33,6 +33,7 @@
# Collect common source files for PDL
C_FILES += $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/*.c)
C_FILES += $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/*.c)
+C_FILES += $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/utils/TOOLCHAIN_GCC_ARM/*.c)
COMPONENT_CORE_PATH := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)
@@ -42,7 +43,7 @@
C_FILES += $(wildcard (COMPONENT_CORE_PATH)/$(PLATFORM_SOURCES_PDL_STARTUP))
# Collect source files for Retarget-io
-C_FILES += $(wildcard $(PRJ_DIR)/libs/retarget-io/*.c)
+C_FILES += $(wildcard $(PRJ_DIR)/libs/retarget-io/source/*.c)
# HAL source files
C_FILES += $(wildcard $(CY_LIBS_PATH)/mtb-hal-cat1/source/*.c)
@@ -92,7 +93,7 @@
INCLUDE_DIRS += $(COMPONENT_CORE_PATH)/HEADER_FILES
# Retarget-io related include directories
-INCLUDE_DIRS += $(THIS_APP_PATH)/retarget-io
+INCLUDE_DIRS += $(THIS_APP_PATH)/retarget-io/include
# Include platforms folder
INCLUDE_DIRS += $(PRJ_DIR)/platforms/BSP/$(FAMILY)
@@ -117,3 +118,6 @@
DEFINES += -DCOMPONENT_CAT1
DEFINES += -DCOMPONENT_CAT$(PDL_CAT_SUFFIX)
+# Disable floating-point support in the retarget-io submodule to decrease MCUBootApp size
+DEFINES += -DCY_RETARGET_IO_NO_FLOAT
+DEFINES += -Dcy_char8_t=char_t
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index 6e1d7a3..92a009f 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit 6e1d7a397f61702aa1a56cb18750927e6a839528
+Subproject commit 92a009f42d50e75583a2384599bec925c00155ca
diff --git a/boot/cypress/libs/retarget-io b/boot/cypress/libs/retarget-io
new file mode 160000
index 0000000..d2b3b4e
--- /dev/null
+++ b/boot/cypress/libs/retarget-io
@@ -0,0 +1 @@
+Subproject commit d2b3b4e02b3af5ba5117e36f69d48b80b3462e99
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.c b/boot/cypress/libs/retarget-io/cy_retarget_io.c
deleted file mode 100644
index 4f2f8ff..0000000
--- a/boot/cypress/libs/retarget-io/cy_retarget_io.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/***************************************************************************//**
-* \file cy_retarget_io.c
-*
-* \brief
-* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
-* kits.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include "cy_retarget_io.h"
-#include "cyhal_hw_types.h"
-#include "cyhal_uart.h"
-#include "cy_utils.h"
-#include "cyhal_system.h"
-#include <stdbool.h>
-#include <stdlib.h>
-
-#if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) && \
- !defined(__ARMCC_VERSION) && !defined(__clang__)
-
-// The cyhal_uart driver is not necessarily thread-safe. To avoid concurrent
-// access, the ARM and IAR libraries use mutexes to control access to stdio
-// streams. For Newlib, the mutex must be implemented in _write(). For all
-// libraries, the program must start the RTOS kernel before calling any stdio
-// functions.
-
-#include "cyabs_rtos.h"
-
-static cy_mutex_t cy_retarget_io_mutex;
-static bool cy_retarget_io_mutex_initialized = false;
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_init
-//--------------------------------------------------------------------------------------------------
-static cy_rslt_t cy_retarget_io_mutex_init(void)
-{
- cy_rslt_t rslt;
- if (cy_retarget_io_mutex_initialized)
- {
- rslt = CY_RSLT_SUCCESS;
- }
- else if (CY_RSLT_SUCCESS == (rslt = cy_rtos_init_mutex(&cy_retarget_io_mutex)))
- {
- cy_retarget_io_mutex_initialized = true;
- }
- return rslt;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_acquire
-//--------------------------------------------------------------------------------------------------
-static void cy_retarget_io_mutex_acquire(void)
-{
- CY_ASSERT(cy_retarget_io_mutex_initialized);
- cy_rslt_t rslt = cy_rtos_get_mutex(&cy_retarget_io_mutex, CY_RTOS_NEVER_TIMEOUT);
- if (rslt != CY_RSLT_SUCCESS)
- {
- abort();
- }
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_release
-//--------------------------------------------------------------------------------------------------
-static void cy_retarget_io_mutex_release(void)
-{
- CY_ASSERT(cy_retarget_io_mutex_initialized);
- cy_rslt_t rslt = cy_rtos_set_mutex(&cy_retarget_io_mutex);
- if (rslt != CY_RSLT_SUCCESS)
- {
- abort();
- }
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_deinit
-//--------------------------------------------------------------------------------------------------
-static void cy_retarget_io_mutex_deinit(void)
-{
- CY_ASSERT(cy_retarget_io_mutex_initialized);
- cy_rslt_t rslt = cy_rtos_deinit_mutex(&cy_retarget_io_mutex);
- if (rslt != CY_RSLT_SUCCESS)
- {
- abort();
- }
- cy_retarget_io_mutex_initialized = false;
-}
-
-
-#else // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
-// !defined(__ARMCC_VERSION) && !defined(__clang__)
-#ifdef __ICCARM__
-// Ignore unused functions
-#pragma diag_suppress=Pe177
-#endif
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_init
-//--------------------------------------------------------------------------------------------------
-static inline cy_rslt_t cy_retarget_io_mutex_init(void)
-{
- return CY_RSLT_SUCCESS;
-}
-
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-__attribute__((unused))
-#endif
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_acquire
-//--------------------------------------------------------------------------------------------------
-static inline void cy_retarget_io_mutex_acquire(void)
-{
-}
-
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-__attribute__((unused))
-#endif
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_release
-//--------------------------------------------------------------------------------------------------
-static inline void cy_retarget_io_mutex_release(void)
-{
-}
-
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-__attribute__((unused))
-#endif
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_mutex_deinit
-//--------------------------------------------------------------------------------------------------
-static inline void cy_retarget_io_mutex_deinit(void)
-{
-}
-
-
-#endif // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
-// !defined(__ARMCC_VERSION) && !defined(__clang__)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-// UART HAL object used by BSP for Debug UART port
-cyhal_uart_t cy_retarget_io_uart_obj;
-
-// Tracks the previous character sent to output stream
-#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-static char cy_retarget_io_stdout_prev_char = 0;
-#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_getchar
-//--------------------------------------------------------------------------------------------------
-static inline cy_rslt_t cy_retarget_io_getchar(char* c)
-{
- return cyhal_uart_getc(&cy_retarget_io_uart_obj, (uint8_t*)c, 0);
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_putchar
-//--------------------------------------------------------------------------------------------------
-static inline cy_rslt_t cy_retarget_io_putchar(char c)
-{
- return cyhal_uart_putc(&cy_retarget_io_uart_obj, (uint8_t)c);
-}
-
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-//--------------------------------------------------------------------------------------------------
-// fputc
-//--------------------------------------------------------------------------------------------------
-__attribute__((weak)) int fputc(int ch, FILE* f)
-{
- (void)f;
- cy_rslt_t rslt = CY_RSLT_SUCCESS;
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if (((char)ch == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
- {
- rslt = cy_retarget_io_putchar('\r');
- }
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
- if (CY_RSLT_SUCCESS == rslt)
- {
- rslt = cy_retarget_io_putchar(ch);
- }
-
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if (CY_RSLT_SUCCESS == rslt)
- {
- cy_retarget_io_stdout_prev_char = (char)ch;
- }
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
- return (CY_RSLT_SUCCESS == rslt) ? ch : EOF;
-}
-
-
-#elif defined (__ICCARM__) // IAR
- #include <yfuns.h>
-
-//--------------------------------------------------------------------------------------------------
-// __write
-//--------------------------------------------------------------------------------------------------
-__weak size_t __write(int handle, const unsigned char* buffer, size_t size)
-{
- size_t nChars = 0;
- // This template only writes to "standard out", for all other file handles it returns failure.
- if (handle != _LLIO_STDOUT)
- {
- return (_LLIO_ERROR);
- }
- if (buffer != NULL)
- {
- cy_rslt_t rslt = CY_RSLT_SUCCESS;
- for (; nChars < size; ++nChars)
- {
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if ((*buffer == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
- {
- rslt = cy_retarget_io_putchar('\r');
- }
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
- if (rslt == CY_RSLT_SUCCESS)
- {
- rslt = cy_retarget_io_putchar(*buffer);
- }
-
- if (rslt != CY_RSLT_SUCCESS)
- {
- break;
- }
-
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- cy_retarget_io_stdout_prev_char = *buffer;
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- ++buffer;
- }
- }
- return (nChars);
-}
-
-
-#else // (__GNUC__) GCC
-// Add an explicit reference to the floating point printf library to allow the usage of floating
-// point conversion specifier.
-//__asm(".global _printf_float");
-//--------------------------------------------------------------------------------------------------
-// _write
-//--------------------------------------------------------------------------------------------------
-__attribute__((weak)) int _write(int fd, const char* ptr, int len)
-{
- int nChars = 0;
- (void)fd;
- if (ptr != NULL)
- {
- cy_rslt_t rslt = CY_RSLT_SUCCESS;
- cy_retarget_io_mutex_acquire();
- for (; nChars < len; ++nChars)
- {
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if ((*ptr == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
- {
- rslt = cy_retarget_io_putchar('\r');
- }
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
- if (CY_RSLT_SUCCESS == rslt)
- {
- rslt = cy_retarget_io_putchar((uint32_t)*ptr);
- }
-
- if (CY_RSLT_SUCCESS != rslt)
- {
- break;
- }
-
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- cy_retarget_io_stdout_prev_char = *ptr;
- #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- ++ptr;
- }
- cy_retarget_io_mutex_release();
- }
- return (nChars);
-}
-
-
-#endif // if defined(__ARMCC_VERSION)
-
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-//--------------------------------------------------------------------------------------------------
-// fgetc
-//--------------------------------------------------------------------------------------------------
-__attribute__((weak)) int fgetc(FILE* f)
-{
- (void)f;
- char c;
- cy_rslt_t rslt = cy_retarget_io_getchar(&c);
- return (CY_RSLT_SUCCESS == rslt) ? c : EOF;
-}
-
-
-#elif defined (__ICCARM__) // IAR
-//--------------------------------------------------------------------------------------------------
-// __read
-//--------------------------------------------------------------------------------------------------
-__weak size_t __read(int handle, unsigned char* buffer, size_t size)
-{
- // This template only reads from "standard in", for all other file handles it returns failure.
- if ((handle != _LLIO_STDIN) || (buffer == NULL))
- {
- return (_LLIO_ERROR);
- }
- else
- {
- cy_rslt_t rslt = cy_retarget_io_getchar((char*)buffer);
- return (CY_RSLT_SUCCESS == rslt) ? 1 : 0;
- }
-}
-
-
-#else // (__GNUC__) GCC
-// Add an explicit reference to the floating point scanf library to allow the usage of floating
-// point conversion specifier.
-//__asm(".global _scanf_float");
-//--------------------------------------------------------------------------------------------------
-// _read
-//--------------------------------------------------------------------------------------------------
-__attribute__((weak)) int _read(int fd, char* ptr, int len)
-{
- (void)fd;
-
- int nChars = 0;
- if (ptr != NULL)
- {
- cy_rslt_t rslt;
- do
- {
- rslt = cy_retarget_io_getchar(ptr);
- if (rslt == CY_RSLT_SUCCESS)
- {
- ++nChars;
- if ((*ptr == '\n') || (*ptr == '\r'))
- {
- break;
- }
- ptr++;
- }
- } while ((rslt == CY_RSLT_SUCCESS) && (nChars < len));
- }
-
- return (nChars);
-}
-
-
-#endif // if defined(__ARMCC_VERSION)
-
-#if defined(__ARMCC_VERSION) // ARM-MDK
-// Include _sys_* prototypes provided by ARM Compiler runtime library
- #include <rt_sys.h>
-
-// Prevent linkage of library functions that use semihosting calls
-__asm(".global __use_no_semihosting\n\t");
-
-// Enable the linker to select an optimized library that does not include code to handle input
-// arguments to main()
-__asm(".global __ARM_use_no_argv\n\t");
-
-//--------------------------------------------------------------------------------------------------
-// _sys_open
-//
-// Open a file: dummy implementation.
-// Everything goes to the same output, no need to translate the file names
-// (__stdin_name/__stdout_name/__stderr_name) to descriptor numbers
-//--------------------------------------------------------------------------------------------------
-FILEHANDLE __attribute__((weak)) _sys_open(const char* name, int openmode)
-{
- (void)name;
- (void)openmode;
- return 1;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_close
-//
-// Close a file: dummy implementation.
-//--------------------------------------------------------------------------------------------------
-int __attribute__((weak)) _sys_close(FILEHANDLE fh)
-{
- (void)fh;
- return 0;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_write
-//
-// Write to a file: dummy implementation.
-// The low-level function fputc retargets output to use UART TX
-//--------------------------------------------------------------------------------------------------
-int __attribute__((weak)) _sys_write(FILEHANDLE fh, const unsigned char* buf, unsigned len,
- int mode)
-{
- (void)fh;
- (void)buf;
- (void)len;
- (void)mode;
- return 0;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_read
-//
-// Read from a file: dummy implementation.
-// The low-level function fputc retargets input to use UART RX
-//--------------------------------------------------------------------------------------------------
-int __attribute__((weak)) _sys_read(FILEHANDLE fh, unsigned char* buf, unsigned len, int mode)
-{
- (void)fh;
- (void)buf;
- (void)len;
- (void)mode;
- return -1;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _ttywrch
-//
-// Write a character to the output channel: dummy implementation.
-//--------------------------------------------------------------------------------------------------
-void __attribute__((weak)) _ttywrch(int ch)
-{
- (void)ch;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_istty
-//
-// Check if the file is connected to a terminal: dummy implementation
-//--------------------------------------------------------------------------------------------------
-int __attribute__((weak)) _sys_istty(FILEHANDLE fh)
-{
- (void)fh;
- return 0;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_seek
-//
-// Move the file position to a given offset: dummy implementation
-//--------------------------------------------------------------------------------------------------
-int __attribute__((weak)) _sys_seek(FILEHANDLE fh, long pos)
-{
- (void)fh;
- (void)pos;
- return -1;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_flen
-// Return the current length of a file: dummy implementation
-//--------------------------------------------------------------------------------------------------
-long __attribute__((weak)) _sys_flen(FILEHANDLE fh)
-{
- (void)fh;
- return 0;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_exit
-//
-// Terminate the program: dummy implementation
-//--------------------------------------------------------------------------------------------------
-void __attribute__((weak)) _sys_exit(int returncode)
-{
- (void)returncode;
- for (;;)
- {
- // Halt here forever
- }
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// _sys_command_string
-//
-// Return a pointer to the command line: dummy implementation
-//--------------------------------------------------------------------------------------------------
-char __attribute__((weak)) *_sys_command_string(char* cmd, int len)
-{
- (void)cmd;
- (void)len;
- return NULL;
-}
-
-
-#endif // ARM-MDK
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_init_fc
-//
-// Enables user to provide flow control pins during initialization
-//--------------------------------------------------------------------------------------------------
-cy_rslt_t cy_retarget_io_init_fc(cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts,
- cyhal_gpio_t rts, uint32_t baudrate)
-{
- const cyhal_uart_cfg_t uart_config =
- {
- .data_bits = 8,
- .stop_bits = 1,
- .parity = CYHAL_UART_PARITY_NONE,
- .rx_buffer = NULL,
- .rx_buffer_size = 0
- };
-
- #if (CYHAL_API_VERSION >= 2)
- cy_rslt_t result = cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, cts, rts, NULL,
- &uart_config);
- #else // HAL API before version 2
- cy_rslt_t result = cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, NULL, &uart_config);
- if (result == CY_RSLT_SUCCESS)
- {
- result = cyhal_uart_set_flow_control(&cy_retarget_io_uart_obj, cts, rts);
- }
- #endif
-
- if (result == CY_RSLT_SUCCESS)
- {
- result = cyhal_uart_set_baud(&cy_retarget_io_uart_obj, baudrate, NULL);
- }
-
- if (result == CY_RSLT_SUCCESS)
- {
- result = cy_retarget_io_mutex_init();
- }
-
- return result;
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_is_tx_active
-//--------------------------------------------------------------------------------------------------
-bool cy_retarget_io_is_tx_active(void)
-{
- return cyhal_uart_is_tx_active(&cy_retarget_io_uart_obj);
-}
-
-
-//--------------------------------------------------------------------------------------------------
-// cy_retarget_io_deinit
-//--------------------------------------------------------------------------------------------------
-void cy_retarget_io_deinit(void)
-{
- // Since the largest hardware buffer would be 256 bytes
- // it takes about 500 ms to transmit the 256 bytes at 9600 baud.
- // Thus 1000 ms gives roughly 50% padding to this time.
- int timeout_remaining_ms = 1000;
- while (timeout_remaining_ms > 0)
- {
- if (!cy_retarget_io_is_tx_active())
- {
- break;
- }
- cyhal_system_delay_ms(1);
- timeout_remaining_ms--;
- }
- CY_ASSERT(timeout_remaining_ms != 0);
- cyhal_uart_free(&cy_retarget_io_uart_obj);
- cy_retarget_io_mutex_deinit();
-}
-
-
-#if defined(__cplusplus)
-}
-#endif
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.h b/boot/cypress/libs/retarget-io/cy_retarget_io.h
deleted file mode 100644
index 7316ea9..0000000
--- a/boot/cypress/libs/retarget-io/cy_retarget_io.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/***********************************************************************************************//**
- * \file cy_retarget_io.h
- *
- * \brief
- * Provides APIs for transmitting messages to or from the board via standard
- * printf/scanf functions. Messages are transmitted over a UART connection which
- * is generally connected to a host machine. Transmission is done at 115200 baud
- * using the tx and rx pins provided by the user of this library. The UART
- * instance is made available via cy_retarget_io_uart_obj in case any changes
- * to the default configuration are desired.
- * NOTE: If the application is built using newlib-nano, by default, floating
- * point format strings (%f) are not supported. To enable this support you must
- * add '-u _printf_float' to the linker command line.
- *
- ***************************************************************************************************
- * \copyright
- * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **************************************************************************************************/
-
-/**
- * \addtogroup group_board_libs Retarget IO
- * \{
- */
-
-#pragma once
-
-#include <stdio.h>
-#include "cy_result.h"
-#include "cyhal_hw_types.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/** UART HAL object used by this library */
-extern cyhal_uart_t cy_retarget_io_uart_obj;
-
-/** UART baud rate */
-#define CY_RETARGET_IO_BAUDRATE (115200)
-
-/**
- * \brief Initialization function for redirecting low level IO commands to allow
- * sending messages over a UART interface. This will setup the communication
- * interface to allow using printf and related functions.
- *
- * In an RTOS environment, this function must be called after the RTOS has been
- * initialized.
- *
- * \param tx UART TX pin, if no TX pin use NC
- * \param rx UART RX pin, if no RX pin use NC
- * \param baudrate UART baudrate
- * \returns CY_RSLT_SUCCESS if successfully initialized, else an error about
- * what went wrong
- */
-#define cy_retarget_io_init(tx, rx, baudrate) cy_retarget_io_init_fc(tx, rx, NC, NC, baudrate)
-
-#ifdef DOXYGEN
-
-/** Defining this macro enables conversion of line feed (LF) into carriage
- * return followed by line feed (CR & LF) on the output direction (STDOUT). You
- * can define this macro through the DEFINES variable in the application
- * Makefile.
- */
-#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
-#endif // DOXYGEN
-
-/**
- * \brief Initialization function for redirecting low level IO commands to allow
- * sending messages over a UART interface with flow control. This will setup the
- * communication interface to allow using printf and related functions.
- *
- * In an RTOS environment, this function must be called after the RTOS has been
- * initialized.
- *
- * \param tx UART TX pin, if no TX pin use NC
- * \param rx UART RX pin, if no RX pin use NC
- * \param cts UART CTS pin, if no CTS pin use NC
- * \param rts UART RTS pin, if no RTS pin use NC
- * \param baudrate UART baudrate
- * \returns CY_RSLT_SUCCESS if successfully initialized, else an error about
- * what went wrong
- */
-cy_rslt_t cy_retarget_io_init_fc(cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts,
- cyhal_gpio_t rts, uint32_t baudrate);
-
-/**
- * \brief Checks whether there is data waiting to be written to the serial console.
- * \returns true if there are pending TX transactions, otherwise false
- */
-bool cy_retarget_io_is_tx_active(void);
-
-/**
- * \brief Releases the UART interface allowing it to be used for other purposes.
- * After calling this, printf and related functions will no longer work.
- */
-void cy_retarget_io_deinit(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/** \} group_board_libs */
diff --git a/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out b/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out
deleted file mode 100644
index c16bb08..0000000
--- a/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out
+++ /dev/null
Binary files differ
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.c b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
index 18ad9eb..38ad111 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
@@ -5,9 +5,9 @@
* Simple wrapper containing all generated files and function to initialize
* all generated code.
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.h b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
index c65929a..2a3341c 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
@@ -5,9 +5,9 @@
* Simple wrapper containing all generated files and function to initialize
* all generated code.
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp b/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
deleted file mode 100644
index 2f754ab..0000000
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
+++ /dev/null
@@ -1,27 +0,0 @@
-/*******************************************************************************
- * File Name: cycfg.timestamp
- *
- * Description:
- * Sentinel file for determining if generated source is up to date.
- * This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
- *
- *******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- ******************************************************************************/
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
index 90d5a10..ce92aee 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
@@ -4,9 +4,9 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
index 1c8e274..7c6e663 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
@@ -4,9 +4,9 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
index 958f2a3..e2761bf 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
@@ -5,9 +5,9 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
deleted file mode 100644
index 42ffcbb..0000000
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*******************************************************************************
- * File Name: cycfg_peripherals.c
- *
- * Description:
- * Peripheral Hardware Block configuration
- * This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
- *
- *******************************************************************************
- * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- ******************************************************************************/
-
-#include "cycfg_peripherals.h"
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
index decbc73..8ed96df 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
@@ -4,9 +4,9 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
index 1787b68..898b6df 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
@@ -4,9 +4,9 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
@@ -45,14 +45,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
@@ -71,14 +71,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
{
@@ -97,14 +97,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_ECO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_IN_PORT_NUM,
.channel_num = CYBSP_ECO_IN_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
{
@@ -123,14 +123,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_ECO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_OUT_PORT_NUM,
.channel_num = CYBSP_ECO_OUT_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
@@ -149,14 +149,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
@@ -175,14 +175,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
@@ -201,14 +201,14 @@
.vohSel = 0UL,
};
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
void init_cycfg_pins(void)
{
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
index f27f86d..aa85520 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
@@ -4,9 +4,9 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
@@ -45,7 +45,7 @@
extern "C" {
#endif /* defined(__cplusplus) */
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_CAN_TX (P0_2)
#define CYBSP_CAN_RX (P0_3)
#define CYBSP_SPI_MISO (P10_0)
@@ -96,7 +96,7 @@
#define CYBSP_USER_LED3 (P16_3)
#define LED3 CYBSP_USER_LED3
#define CYBSP_USER_BTN2 (P17_3)
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT21
@@ -111,13 +111,13 @@
#define CYBSP_WCO_IN_HSIOM ioss_0_port_21_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
#define CYBSP_WCO_IN P21_0
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT21
@@ -132,13 +132,13 @@
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_21_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
#define CYBSP_WCO_OUT P21_1
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_ECO_IN_ENABLED 1U
#define CYBSP_ECO_IN_PORT GPIO_PRT21
@@ -153,13 +153,13 @@
#define CYBSP_ECO_IN_HSIOM ioss_0_port_21_pin_2_HSIOM
#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
#define CYBSP_ECO_IN P21_2
#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_ECO_OUT_ENABLED 1U
#define CYBSP_ECO_OUT_PORT GPIO_PRT21
@@ -174,7 +174,7 @@
#define CYBSP_ECO_OUT_HSIOM ioss_0_port_21_pin_3_HSIOM
#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
#define CYBSP_ECO_OUT P21_3
#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
@@ -187,7 +187,7 @@
#define CYBSP_TRACE_DATA2 (P22_2)
#define CYBSP_TRACE_DATA3 (P22_3)
#define CYBSP_TRACE_CLK (P22_4)
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT23
@@ -202,13 +202,13 @@
#define CYBSP_SWO_HSIOM ioss_0_port_23_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P23_4
#define CYBSP_SWO P23_4
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT23
@@ -223,13 +223,13 @@
#define CYBSP_SWDCK_HSIOM ioss_0_port_23_pin_5_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P23_5
#define CYBSP_SWDCK P23_5
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT23
@@ -244,7 +244,7 @@
#define CYBSP_SWDIO_HSIOM ioss_0_port_23_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P23_6
#define CYBSP_SWDIO P23_6
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
@@ -273,49 +273,49 @@
#define CYBSP_QSPI_D1 (P7_2)
#define CYBSP_QSPI_D2 (P7_3)
#define CYBSP_QSPI_D3 (P7_4)
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
-#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+#endif /* defined (CY_USING_HAL) */
void init_cycfg_pins(void);
void reserve_cycfg_pins(void);
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
index c2d6e16..591c440 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
@@ -4,7 +4,7 @@
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
- * QSPI Configurator 4.30.0.1865
+ * QSPI Configurator 4.50.0.2481
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
index b834288..9472c71 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
@@ -4,7 +4,7 @@
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
- * QSPI Configurator 4.30.0.1865
+ * QSPI Configurator 4.50.0.2481
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
@@ -28,7 +28,7 @@
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
-#define CY_SMIF_CFG_TOOL_VERSION (430)
+#define CY_SMIF_CFG_TOOL_VERSION (450)
/* Supported QSPI Driver version */
#define CY_SMIF_DRV_VERSION_REQUIRED (100)
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
index 6a568a0..d72f510 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
@@ -4,9 +4,9 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
index 7922f27..82287c7 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
@@ -4,9 +4,9 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
@@ -283,6 +283,76 @@
};
#endif /* (!defined(CY_DEVICE_SECURE)) */
+__WEAK void cycfg_ClockStartupError(uint32_t error);
+
+#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED)
+__STATIC_INLINE void Cy_SysClk_Ilo0DeInit();
+#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */
+
+#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED)
+__STATIC_INLINE void Cy_SysClk_Ilo1DeInit();
+#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */
+
+#if ((!defined(CY_DEVICE_SECURE)))
+__STATIC_INLINE void Cy_SysClk_FllDeInit();
+#endif /* ((!defined(CY_DEVICE_SECURE))) */
+
+#if (CY_CPU_CORTEX_M7)
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit();
+#endif /* (CY_CPU_CORTEX_M7) */
+
+#if (!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkBakInit();
+__STATIC_INLINE void Cy_SysClk_EcoInit();
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init();
+__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init();
+
+#if (!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_FllInit();
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf1Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf5Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf6Init();
+__STATIC_INLINE void Cy_SysClk_ClkHf7Init();
+
+#if (!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_Ilo0Init();
+__STATIC_INLINE void Cy_SysClk_Ilo1Init();
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+__STATIC_INLINE void Cy_SysClk_ClkLfInit();
+__STATIC_INLINE void Cy_SysClk_ClkMemInit();
+
+#if (!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath3Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath4Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath5Init();
+__STATIC_INLINE void Cy_SysClk_ClkPath6Init();
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit();
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+__STATIC_INLINE void Cy_SysClk_Pll0Init();
+__STATIC_INLINE void Cy_SysClk_Pll1Init();
+__STATIC_INLINE void Cy_SysClk_Pll2Init();
+__STATIC_INLINE void Cy_SysClk_Pll3Init();
+
+#if (!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit();
+__STATIC_INLINE void Cy_SysClk_WcoInit();
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+__STATIC_INLINE void init_cycfg_power(void);
+
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
index 93575ee..b3dbc75 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
@@ -4,9 +4,9 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
- * Configurator Backend 3.20.0
- * device-db 4.12.0.5709
- * mtb-pdl-cat1 3.600.0.33254
+ * Configurator Backend 3.50.0
+ * device-db 4.100.0.8863
+ * mtb-pdl-cat1 3.10.0.32115
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
diff --git a/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
index 295934a..91da26c 100644
--- a/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
+++ b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
@@ -4,10 +4,10 @@
# Description:
# This file contains a SMIF Bank layout for use with OpenOCD.
# This file was automatically generated and should not be modified.
-# QSPI Configurator: 4.30.0.1865
+# QSPI Configurator: 4.50.0.2481
#
################################################################################
-# Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct
index 8627ef0..4c36bfd 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct
@@ -3,7 +3,7 @@
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
-;* \file xmc7200d_x8384_cm0plus.sct
+;* \file xmc7200_x8384_cm0plus.sct
;* \version 1.0
;*
;* Linker file for the ARMCC.
@@ -57,7 +57,7 @@
; SRAM reservations
#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
-#define CM0PLUS_SRAM_RESERVE 0x00020000
+#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
#define SRAM_CM0P_START BASE_SRAM_CM0P
@@ -65,7 +65,7 @@
; Code flash reservations
#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
-#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000
+#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct
new file mode 100644
index 0000000..c752362
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct
@@ -0,0 +1,115 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file xmc7200d_x8384_cm0plus.sct
+;* \version 1.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
+; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
+
+#define SRAM_START_RESERVE 0
+#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+#define STACK_SIZE 0x1000
+#define RAMVECTORS_ALIGNMENT 128
+
+; SRAM reservations
+#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
+#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
+#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
+#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
+#define SRAM_CM0P_START BASE_SRAM_CM0P
+#define SRAM_CM0P_SIZE SIZE_SRAM_CM0P
+
+; Code flash reservations
+#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
+#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */
+#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
+#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
+#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P
+#define CODE_FLASH_CM0P_SIZE SIZE_CODE_FLASH_CM0P
+
+; Cortex-M0+ application flash area
+LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS SRAM_CM0P_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ * (.bss.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE
+ {
+ }
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
index fa98705..379f27c 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
@@ -383,15 +383,19 @@
* Symbols for use by secure config
*============================================================
*/
-__secure_object_size = __app_image_end - __app_header_start;
-__app_header_vtable_offset = __Vectors - __app_header_start;
+EXTERN (__secure_object_size)
+PROVIDE(__secure_object_size = __app_image_end - __app_header_start);
+EXTERN (__app_header_vtable_offset)
+PROVIDE(__app_header_vtable_offset = __Vectors - __app_header_start);
/*============================================================
* Symbols for use by cymcuelftool
*============================================================
*/
-__cy_app_verify_start = ORIGIN(cm0_flash);
-__cy_app_verify_length = __secure_object_size;
+EXTERN (__cy_app_verify_start)
+PROVIDE(__cy_app_verify_start = ORIGIN(cm0_flash));
+EXTERN (__cy_app_verify_length)
+PROVIDE(__cy_app_verify_length = __secure_object_size);
/* Check application header placement */
ASSERT(__app_header_start == ORIGIN(cm0_flash), "Incorrect app header placement")
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld
new file mode 100644
index 0000000..7f2e08e
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld
@@ -0,0 +1,367 @@
+/***************************************************************************//**
+* \file xmc7200d_x8384_cm0plus.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM7_1 SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT = 128;
+
+sram_start_reserve = 0;
+sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+
+cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
+
+sram_base_address = 0x28000000;
+code_flash_base_address = 0x10000000;
+
+_base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom;
+_size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
+_base_CODE_FLASH_CM0P = code_flash_base_address;
+_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
+
+/* Fixed Addesses */
+_base_WORK_FLASH = 0x14000000;
+_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
+_base_SFLASH_USER_DATA = 0x17000800;
+_size_SFLASH_USER_DATA = 0x00000800;
+_base_SFLASH_NAR = 0x17001A00;
+_size_SFLASH_NAR = 0x00000200;
+_base_SFLASH_PUB_KEY = 0x17006400;
+_size_SFLASH_PUB_KEY = 0x00000C00;
+_base_SFLASH_APP_PROT = 0x17007600;
+_size_SFLASH_APP_PROT = 0x00000200;
+_base_SFLASH_TOC2 = 0x17007C00;
+_size_SFLASH_TOC2 = 0x00000200;
+_base_XIP = 0x60000000;
+_size_XIP = 0x08000000;
+_base_EFUSE = 0x90700000;
+_size_EFUSE = 0x00100000;
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
+ */
+ cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
+ cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
+
+ /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ */
+ em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
+ sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
+ sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
+ xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
+ efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+ /* Cortex-M4 application flash area */
+ .text ORIGIN(cm0_flash) :
+ {
+ /* Cortex-M4 flash vector table */
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > cm0_flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > cm0_flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > cm0_flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG ((__data_end__ - __data_start__)/4) /* Size */
+
+ __copy_table_end__ = .;
+ } > cm0_flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__)/4)
+ __zero_table_end__ = .;
+ } > cm0_flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) :
+ {
+ . = ALIGN(RAMVECTORS_ALIGNMENT);
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > cm0_ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > cm0_ram AT>cm0_flash
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > cm0_ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > cm0_ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > cm0_ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > cm0_ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+}
+
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf
index 62813e2..d1e9824 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf
@@ -1,5 +1,5 @@
/*******************************************************************************
-* \file xmc7200d_x8384_cm0plus.icf
+* \file xmc7200_x8384_cm0plus.icf
* \version 1.0.0
*
* Linker file for the IAR compiler.
@@ -39,31 +39,59 @@
define symbol sram_start_reserve = 0;
define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
-define symbol cm0plus_sram_reserve = 0x00020000; /* cm0 sram size */
-define symbol cm0plus_code_flash_reserve = 0x00080000; /* cm7_0 sram size */
-define symbol cm7_0_code_flash_reserve = 0x00200000;
+define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
define symbol sram_base_address = 0x28000000;
define symbol code_flash_base_address = 0x10000000;
-define symbol code_flash_total_size = 0x00080000;
define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
define symbol cm0plus_heap_reserve = 0x00001000;
define symbol cm0plus_stack_reserve = 0x00001000;
-define symbol heap_reserve = cm0plus_heap_reserve;
-define symbol stack_reserve = (cm0plus_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash values.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf',
+ * where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.icf'.
+ * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
+ * after which cm0p core aplication must be build and flashed again.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom;
+define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1
+
+/* Flash */
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address
+define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1
+
+/*-Sizes-*/
+
+define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve
+
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol heap_reserve = __ICFEDIT_size_heap__;
+define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
-define symbol _base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom;
-define symbol _size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
-define symbol _base_CODE_FLASH_CM0P = code_flash_base_address;
-define symbol _size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
-define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
-define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
-define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
-define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__;
+define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1;
+define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__;
+define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1;
/*============================================================
* Memory definitions
@@ -74,8 +102,6 @@
define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ];
define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ];
-define region CODE_FLASH_CM7_0 = mem:[from _base_CODE_FLASH_CM7_0 size _size_CODE_FLASH_CM7_0 ];
-define region CODE_FLASH_CM7_1 = mem:[from _base_CODE_FLASH_CM7_1 size _size_CODE_FLASH_CM7_1 ];
/*============================================================
* Block definitions
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf
new file mode 100644
index 0000000..63900d4
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf
@@ -0,0 +1,148 @@
+/*******************************************************************************
+* \file xmc7200d_x8384_cm0plus.icf
+* \version 1.0.0
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+define symbol RAMVECTORS_ALIGNMENT = 128;
+
+define symbol sram_start_reserve = 0;
+define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+
+define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
+
+define symbol sram_base_address = 0x28000000;
+define symbol code_flash_base_address = 0x10000000;
+
+define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
+
+define symbol cm0plus_heap_reserve = 0x00001000;
+define symbol cm0plus_stack_reserve = 0x00001000;
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash values.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf',
+ * where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.icf'.
+ * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
+ * after which cm0p core aplication must be build and flashed again.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom;
+define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1
+
+/* Flash */
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address
+define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1
+
+/*-Sizes-*/
+
+define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve
+
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol heap_reserve = __ICFEDIT_size_heap__;
+define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
+
+
+define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__;
+define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1;
+define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__;
+define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1;
+
+/*============================================================
+ * Memory definitions
+ *============================================================
+ */
+
+define memory mem with size = 4G;
+
+define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ];
+define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ];
+
+/*============================================================
+ * Block definitions
+ *============================================================
+ */
+define block CSTACK with alignment = 8, size = stack_reserve { };
+define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
+define block HEAP_STACK { block HEAP, last block CSTACK };
+
+/*============================================================
+ * Initialization
+ *============================================================
+ */
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*============================================================
+ * Placement
+ *============================================================
+ */
+
+/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
+/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
+
+place at start of CODE_FLASH { section .intvec };
+place in CODE_FLASH { readonly };
+
+place in SRAM { readwrite };
+place at end of SRAM { block HEAP_STACK };
+
+keep { section .intvec };
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+/* The start of CM7_0/1 vector table is required by CM0+ application to correctly
+ * set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
+ */
+
+define exported symbol __ecc_init_sram_start_address = start(SRAM);
+define exported symbol __ecc_init_sram_end_address = end(SRAM);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
index 7a4e9fd..b4624d5 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_cm0plus.c
-* \version 1.0
+* \version 1.2
*
* The device system-source file.
*
********************************************************************************
* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
+* Copyright 2021-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -199,14 +199,14 @@
PrepareSystemCallInfrastructure();
/* startup Init done */
- SystemIrqInit();
-
+ Cy_PDL_Init(CY_DEVICE_CFG);
Cy_WDT_Unlock();
Cy_WDT_Disable();
Cy_SystemInit();
SystemCoreClockUpdate();
+ SystemIrqInit();
}
@@ -282,17 +282,18 @@
*****************************************************************************/
static void CopyVectorTable(void)
{
- const uint8_t u8NrOfVectors = (uint8_t) ((uint32_t) &__Vectors_Size / 4);
- uint32_t * const pu32RamTable = (uint32_t *) __ramVectors;
- uint32_t * const pu32RomTable = (uint32_t *) (&__Vectors);
+ const uint8_t numVectors = (uint8_t)((uint32_t)&__Vectors_Size / 4);
+ uint32_t * const ramTable = (uint32_t *)__ramVectors;
+ uint32_t * const romTable = (uint32_t *)(&__Vectors);
-
- for(uint8_t u8Index = 0; u8Index < u8NrOfVectors; u8Index++)
+ // Copy the vector table from ROM into RAM
+ for(uint8_t index = 0; index < numVectors; index++)
{
- pu32RamTable[u8Index] = pu32RomTable[u8Index];
+ ramTable[index] = romTable[index];
}
- SCB->VTOR = (uint32_t) pu32RamTable;
+ // Update the ARM System Control Block vector table base address.
+ SCB->VTOR = (uint32_t)ramTable;
}
/**
@@ -305,12 +306,13 @@
{
const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4);
const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4);
- uint32_t * const pu32RamTable = (uint32_t *) __ramVectors;
- uint32_t * const pu32SromTable = (uint32_t *) SROM_VECTOR_TABLE_BASE_ADDRESS;
+ volatile uint32_t * const volatile ramTable = (uint32_t *)__ramVectors;
+ /* The array syntax is necessary to avoid out-of-bounds warnings in some compilers. */
+ volatile uint32_t (* const volatile sromTable)[VECTORTABLE_SIZE] = (uint32_t (*)[VECTORTABLE_SIZE])SROM_VECTOR_TABLE_BASE_ADDRESS;
// Use IRQ0 and IRQ1 handlers from SROM vector table
- pu32RamTable[u8Irq0Index] = pu32SromTable[u8Irq0Index];
- pu32RamTable[u8Irq1Index] = pu32SromTable[u8Irq1Index];
+ ramTable[u8Irq0Index] = (*sromTable)[u8Irq0Index];
+ ramTable[u8Irq1Index] = (*sromTable)[u8Irq1Index];
NVIC_SetPriority(NvicMux0_IRQn, 1);
NVIC_SetPriority(NvicMux1_IRQn, 0);
@@ -364,24 +366,14 @@
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
- uint32_t pathFreqHz;
- uint32_t clkHfPath;
-
/* Get frequency for the high-frequency clock*/
- clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+ cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM);
- pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
-
- SystemCoreClock = pathFreqHz;
-
- cy_Hfclk0FreqHz = SystemCoreClock;
+ /* The CM0P core's clock source is the slow clock. */
+ SystemCoreClock = Cy_SysClk_ClkSlowGetFrequency();
/* Get Peripheral clock Frequency*/
- clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
-
- pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
-
- cy_PeriClkFreqHz = pathFreqHz;
+ cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM);
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct
new file mode 100644
index 0000000..e186acc
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct
@@ -0,0 +1,152 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file xmc7200_x8384_cm7.sct
+;* \version 1.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
+; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
+
+
+; RAM
+#define SRAM_TOTAL_SIZE 0x00100000 /* 1024K : SRAM0 + SRAM1 */
+
+; FLASH
+#define CODE_FLASH_TOTAL_SIZE 0x00830000 /* 8384K : TOTAL FLASH SIZE */
+
+#define SRAM_START_RESERVE 0
+#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+#define STACK_SIZE 0x1000
+#define RAMVECTORS_ALIGNMENT 128
+
+; RAM
+#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
+#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
+#define CM7_NON_CACHEABLE_SRAM_RESERVE 0x00020000 /* 128k: non-cacheable sram size */
+#define CM7_0_SRAM_RESERVE SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_NON_CACHEABLE_SRAM_RESERVE /* 880K : cm7_0 sram size */
+
+; FLASH
+#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
+#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */
+#define CM7_0_CODE_FLASH_RESERVE 0x007B0000 /* 7872K: cm7_0 flash size */
+
+; SRAM reservations
+#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
+#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
+#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
+#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
+/* Always make sure that the starting address of the non-cacheable region is aligned to the non-cacheable region size boundary. */
+#define SIZE_SRAM_NON_CACHE CM7_NON_CACHEABLE_SRAM_RESERVE /* 128K : non-cacheable sram size */
+#define BASE_SRAM_NON_CACHE SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+
+; Code flash reservations
+#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
+#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
+#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
+#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
+
+#define BASE_SRAM BASE_SRAM_CM7_0
+#define SIZE_SRAM SIZE_SRAM_CM7_0
+#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0
+#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0
+
+
+; Cortex-M0+ application flash image area
+LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P
+{
+ .cy_m0p_image +0
+ {
+ * (.cy_m0p_image)
+ }
+}
+
+; Cortex-M7 application flash area
+LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS BASE_SRAM UNINIT
+ {
+ * (.bss.noinit.RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ * (.bss.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE
+ {
+ }
+
+ RAM_NONCACHE BASE_SRAM_NON_CACHE ALIGN 32 SIZE_SRAM_NON_CACHE
+ {
+ * (.cy_sharedmem)
+ }
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker_d.sct b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker_d.sct
new file mode 100644
index 0000000..a02e7ac
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_ARM/linker_d.sct
@@ -0,0 +1,173 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file xmc7200d_x8384_cm7.sct
+;* \version 1.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;* http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
+; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
+
+
+; RAM
+#define SRAM_TOTAL_SIZE 0x00100000 /* 1024K : SRAM0 + SRAM1 */
+
+; FLASH
+#define CODE_FLASH_TOTAL_SIZE 0x00830000 /* 8384K : TOTAL FLASH SIZE */
+
+#define SRAM_START_RESERVE 0
+#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+#define STACK_SIZE 0x1000
+#define RAMVECTORS_ALIGNMENT 128
+
+; RAM
+#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
+#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
+#define CM7_1_SRAM_RESERVE 0x00010000 /* 64k: cm7_1 sram size */
+#define CM7_NON_CACHEABLE_SRAM_RESERVE 0x00020000 /* 128k: non-cacheable sram size */
+#define CM7_0_SRAM_RESERVE SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE - CM7_NON_CACHEABLE_SRAM_RESERVE /* 838K: cm7_0 sram size */
+
+; FLASH
+#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
+#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */
+#define CM7_0_CODE_FLASH_RESERVE 0x00200000 /* 2048K: cm7_0 flash size */
+
+; SRAM reservations
+#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
+#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
+#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
+#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
+/* In case of single CM7 device CM7_1 values should not be used */
+#define SIZE_SRAM_CM7_1 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE - CM7_NON_CACHEABLE_SRAM_RESERVE /* 64K : cm7_1 sram size */
+#define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+/* Always make sure that the starting address of the non-cacheable region is aligned to the non-cacheable region size boundary. */
+#define SIZE_SRAM_NON_CACHE CM7_NON_CACHEABLE_SRAM_RESERVE /* 128K : non-cacheable sram size */
+#define BASE_SRAM_NON_CACHE SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE + CM7_1_SRAM_RESERVE
+
+
+; Code flash reservations
+#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
+#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
+#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
+#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
+#define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
+#define SIZE_CODE_FLASH_CM7_1 CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE /* 5824K : cm7_1 flash size */
+
+; For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined
+#ifdef _CORE_CM7_1_
+#define BASE_SRAM BASE_SRAM_CM7_1
+#define SIZE_SRAM SIZE_SRAM_CM7_1
+#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_1
+#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_1
+#elif _CORE_CM7_0_
+#define BASE_SRAM BASE_SRAM_CM7_0
+#define SIZE_SRAM SIZE_SRAM_CM7_0
+#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0
+#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0
+#else
+; Assert if either _CORE_CM7_1_ or _CORE_CM7_0_ is not defined
+ScatterAssert(0);
+#endif
+
+#ifdef _CORE_CM7_0_
+; Cortex-M0+ application flash image area
+LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P
+{
+ .cy_m0p_image +0
+ {
+ * (.cy_m0p_image)
+ }
+}
+#endif
+
+; Cortex-M7 application flash area
+LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS BASE_SRAM UNINIT
+ {
+ * (.bss.noinit.RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ * (.bss.noinit)
+ }
+
+ ; Application heap area (HEAP)
+ ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
+ {
+ }
+
+ ; Stack region growing down
+ ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE
+ {
+ }
+
+#ifdef _CORE_CM7_0_
+ RAM_NONCACHE BASE_SRAM_NON_CACHE ALIGN 32 SIZE_SRAM_NON_CACHE
+ {
+ * (.cy_sharedmem)
+ }
+#endif
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld
new file mode 100644
index 0000000..495d6c9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld
@@ -0,0 +1,457 @@
+/***************************************************************************//**
+* \file xmc7200_x8384_cm7.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM7 SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT = 128;
+
+sram_start_reserve = 0;
+
+sram_total_size = 0x00100000; /* SRAM0 + SRAM1 */
+sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+cm7_sram_non_cache_reserve = 0x00020000; /* 128K :non-cacheable sram size */
+cm7_0_sram_reserve = sram_total_size - cm0plus_sram_reserve - cm7_sram_non_cache_reserve; /* 880K : cm7_0 sram size */
+
+code_flash_total_size = 0x00830000; /* 8384K: total flash size */
+cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
+cm7_0_code_flash_reserve = 0x007B0000; /* 7872K: cm7_0 flash size */
+
+code_flash_base_address = 0x10000000;
+sram_base_address = 0x28000000;
+
+/* SRAM reservations */
+_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
+_size_SRAM_CM7_0 = cm7_0_sram_reserve;
+
+_base_SRAM_NON_CACHE = _base_SRAM_CM7_0 + _size_SRAM_CM7_0;
+_size_SRAM_NON_CACHE = cm7_sram_non_cache_reserve;
+
+/* Code flash reservations */
+_base_CODE_FLASH_CM0P = code_flash_base_address;
+_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
+_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
+_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
+
+/* Fixed Addresses */
+_base_WORK_FLASH = 0x14000000;
+_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
+_base_CM7_0_ITCM = 0x00000000;
+_size_CM7_0_ITCM = 0x00004000;
+_base_CM7_0_DTCM = 0x20000000;
+_size_CM7_0_DTCM = 0x00004000;
+
+/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
+_base_SRAM = _base_SRAM_CM7_0;
+_size_SRAM = _size_SRAM_CM7_0;
+_base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
+_size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
+_base_SFLASH_USER_DATA = 0x17000800;
+_size_SFLASH_USER_DATA = 0x00000800;
+_base_SFLASH_NAR = 0x17001A00;
+_size_SFLASH_NAR = 0x00000200;
+_base_SFLASH_PUB_KEY = 0x17006400;
+_size_SFLASH_PUB_KEY = 0x00000C00;
+_base_SFLASH_APP_PROT = 0x17007600;
+_size_SFLASH_APP_PROT = 0x00000200;
+_base_SFLASH_TOC2 = 0x17007C00;
+_size_SFLASH_TOC2 = 0x00000200;
+_base_XIP = 0x60000000;
+_size_XIP = 0x08000000;
+_base_EFUSE = 0x90700000;
+_size_EFUSE = 0x00100000;
+_base_ITCM = _base_CM7_0_ITCM;
+_size_ITCM = _size_CM7_0_ITCM;
+_base_DTCM = _base_CM7_0_DTCM;
+_size_DTCM = _size_CM7_0_DTCM;
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
+ ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */
+ ram_noncache (rxw) : ORIGIN = _base_SRAM_NON_CACHE, LENGTH = _size_SRAM_NON_CACHE /* Non-Cacheable SRAM */
+ flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
+ flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */
+
+ /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ */
+ em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
+ sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
+ sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
+ xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
+ efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
+ itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */
+ dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+ /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
+ .cy_cm0p_image ORIGIN(flash_cm0p):
+ {
+ . = ALIGN(4);
+ __cy_m0p_code_start = . ;
+ KEEP(*(.cy_m0p_image))
+ __cy_m0p_code_end = . ;
+ } > flash_cm0p
+
+ /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
+ ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
+
+ /* Cortex-M7 application flash area */
+ .text ORIGIN(flash) :
+ {
+ /* Cortex-M7 flash vector table */
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG ((__data_end__ - __data_start__)/4) /* Size */
+
+ /* Copy data section to noncache RAM */
+ LONG (__noncache_ramdata_lma_start__) /* From */
+ LONG (__noncacheable_ram_start__) /* To */
+ LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4) /* Size */
+
+ /* Copy code to ITCM */
+ LONG (__zero_table_end__) /* From */
+ LONG (__itcm_start__) /* To */
+ LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
+
+ /* Copy data to DTCM */
+ LONG (__itcm_flash_end__) /* From */
+ LONG (__dtcm_start__) /* To */
+ LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__)/4)
+ __zero_table_end__ = .;
+ } > flash
+
+ /* itcm */
+ .cy_itcm ORIGIN(itcm):
+ {
+ __itcm_start__ = .;
+ KEEP(*(.cy_itcm))
+ __itcm_end__ = .;
+ } > itcm AT>flash
+
+ __itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
+
+ /* dtcm */
+ .cy_dtcm ORIGIN(dtcm):
+ {
+ __dtcm_start__ = .;
+ KEEP(*(.cy_dtcm))
+ __dtcm_end__ = .;
+ } > dtcm AT>flash
+
+ __etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
+
+
+ .ramVectors (NOLOAD) :
+ {
+ . = ALIGN(RAMVECTORS_ALIGNMENT);
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(32);
+
+ __data_end__ = .;
+
+ } > ram AT>flash
+
+ __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+ .ram_noncache :
+ {
+ . = ALIGN(32);
+ __noncacheable_ram_start__ = .;
+ *(.cy_sharedmem)
+ . = ALIGN(4);
+ __noncacheable_ram_end__ = .;
+ } > ram_noncache AT>flash
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+}
+
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+
+__ecc_init_sram_start_address = ORIGIN(ram);
+__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker_d.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker_d.ld
new file mode 100644
index 0000000..cadb9f4
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker_d.ld
@@ -0,0 +1,467 @@
+/***************************************************************************//**
+* \file xmc7200d_x8384_cm7.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM7 SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT = 128;
+
+sram_start_reserve = 0;
+
+sram_total_size = 0x00100000; /* SRAM0 + SRAM1 */
+sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+cm7_1_sram_reserve = 0x00010000; /* 64k : cm7_1 sram size */
+cm7_sram_non_cache_reserve = 0x00020000; /* 128K :non-cacheable sram size */
+cm7_0_sram_reserve = sram_total_size - cm0plus_sram_reserve - cm7_1_sram_reserve - cm7_sram_non_cache_reserve; /* 838K: cm7_0 sram size */
+
+code_flash_total_size = 0x00830000; /* 8384K: total flash size */
+cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
+cm7_0_code_flash_reserve = 0x00200000; /* 2048K: cm7_0 flash size */
+
+code_flash_base_address = 0x10000000;
+sram_base_address = 0x28000000;
+
+/* SRAM reservations */
+_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
+_size_SRAM_CM7_0 = cm7_0_sram_reserve;
+/* In case of single CM7 device CM7_1 values should not be used */
+_base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+_size_SRAM_CM7_1 = cm7_1_sram_reserve; /* 64K : cm7_1 sram size */
+
+_base_SRAM_NON_CACHE = _base_SRAM_CM7_1 + _size_SRAM_CM7_1;
+_size_SRAM_NON_CACHE = cm7_sram_non_cache_reserve;
+
+/* Code flash reservations */
+_base_CODE_FLASH_CM0P = code_flash_base_address;
+_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
+_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
+_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
+_base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+_size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+
+/* Fixed Addresses */
+_base_WORK_FLASH = 0x14000000;
+_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
+_base_CM7_0_ITCM = 0x00000000;
+_size_CM7_0_ITCM = 0x00004000;
+_base_CM7_0_DTCM = 0x20000000;
+_size_CM7_0_DTCM = 0x00004000;
+_base_CM7_1_ITCM = 0x00000000;
+_size_CM7_1_ITCM = 0x00004000;
+_base_CM7_1_DTCM = 0x20000000;
+_size_CM7_1_DTCM = 0x00004000;
+
+/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
+_base_SRAM = DEFINED(_CORE_CM7_1_) ? _base_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_SRAM = DEFINED(_CORE_CM7_1_) ? _size_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_CODE_FLASH = DEFINED(_CORE_CM7_1_) ? _base_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_CODE_FLASH_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_CODE_FLASH = DEFINED(_CORE_CM7_1_) ? _size_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_CODE_FLASH_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_SFLASH_USER_DATA = 0x17000800;
+_size_SFLASH_USER_DATA = 0x00000800;
+_base_SFLASH_NAR = 0x17001A00;
+_size_SFLASH_NAR = 0x00000200;
+_base_SFLASH_PUB_KEY = 0x17006400;
+_size_SFLASH_PUB_KEY = 0x00000C00;
+_base_SFLASH_APP_PROT = 0x17007600;
+_size_SFLASH_APP_PROT = 0x00000200;
+_base_SFLASH_TOC2 = 0x17007C00;
+_size_SFLASH_TOC2 = 0x00000200;
+_base_XIP = 0x60000000;
+_size_XIP = 0x08000000;
+_base_EFUSE = 0x90700000;
+_size_EFUSE = 0x00100000;
+_base_ITCM = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_ITCM : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_ITCM = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_ITCM : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_DTCM = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_DTCM : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_DTCM = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_DTCM : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
+ ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */
+ ram_noncache (rxw) : ORIGIN = _base_SRAM_NON_CACHE, LENGTH = _size_SRAM_NON_CACHE /* Non-Cacheable SRAM */
+ flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
+ flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */
+
+ /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ */
+ em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
+ sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
+ sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
+ xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
+ efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
+ itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */
+ dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+ /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
+ .cy_cm0p_image ORIGIN(flash_cm0p):
+ {
+ . = ALIGN(4);
+ __cy_m0p_code_start = . ;
+ KEEP(*(.cy_m0p_image))
+ __cy_m0p_code_end = . ;
+ } > flash_cm0p
+
+ /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
+ ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
+
+ /* Cortex-M7 application flash area */
+ .text ORIGIN(flash) :
+ {
+ /* Cortex-M7 flash vector table */
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG ((__data_end__ - __data_start__)/4) /* Size */
+
+ /* Copy data section to noncache RAM */
+ LONG (__noncache_ramdata_lma_start__) /* From */
+ LONG (__noncacheable_ram_start__) /* To */
+ LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4) /* Size */
+
+ /* Copy code to ITCM */
+ LONG (__zero_table_end__) /* From */
+ LONG (__itcm_start__) /* To */
+ LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
+
+ /* Copy data to DTCM */
+ LONG (__itcm_flash_end__) /* From */
+ LONG (__dtcm_start__) /* To */
+ LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__)/4)
+
+ __zero_table_end__ = .;
+ } > flash
+
+
+ /* itcm */
+ .cy_itcm ORIGIN(itcm):
+ {
+ __itcm_start__ = .;
+ KEEP(*(.cy_itcm))
+ __itcm_end__ = .;
+ } > itcm AT>flash
+
+ __itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
+
+ /* dtcm */
+ .cy_dtcm ORIGIN(dtcm):
+ {
+ __dtcm_start__ = .;
+ KEEP(*(.cy_dtcm))
+ __dtcm_end__ = .;
+ } > dtcm AT>flash
+
+ __etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
+
+
+ .ramVectors (NOLOAD) :
+ {
+ . = ALIGN(RAMVECTORS_ALIGNMENT);
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(32);
+
+ __data_end__ = .;
+
+ } > ram AT>flash
+
+ __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+ .ram_noncache :
+ {
+ . = ALIGN(32);
+ __noncacheable_ram_start__ = .;
+ *(.cy_sharedmem)
+ . = ALIGN(4);
+ __noncacheable_ram_end__ = .;
+ } > ram_noncache AT>flash
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+}
+
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+
+__ecc_init_sram_start_address = ORIGIN(ram);
+__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf
new file mode 100644
index 0000000..e18c25f
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf
@@ -0,0 +1,199 @@
+/*******************************************************************************
+* \file xmc7200_x8384_cm7.icf
+* \version 1.0.0
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+define symbol sram_start_reserve = 0;
+
+define symbol sram_total_size = 0x00100000;
+define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+define symbol sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+define symbol cm7_0_sram_reserve = 0x000DC000; /* 880K : cm7_0 sram size */
+define symbol cm7_sram_non_cache_reserve = 0x00020000; /* 128K :non-cacheable sram size */
+
+
+define symbol code_flash_total_size = 0x00830000; /* 8384K: total flash size */
+define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
+define symbol cm7_0_code_flash_reserve = 0x007B0000; /* 7872K: cm7_0 flash size */
+
+
+define symbol code_flash_base_address = 0x10000000;
+define symbol sram_base_address = 0x28000000;
+
+define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
+
+define symbol cm7_heap_reserve = 0x00001000;
+define symbol cm7_stack_reserve = 0x00001000;
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM7 cores.
+ * You can change the memory allocation by editing RAM and Flash values.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm0plus.icf'.
+ * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
+ * after which cm0p core aplication must be build and flashed again.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; // sram_base_address + cm0plus_sram_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x280DFFFF; // cm7_0_sram_reserve;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+/* RAM non-cacheable ram */
+/* Always make sure that the starting address of the non-cacheable region is aligned to the non-cacheable region size boundary. */
+define symbol __ICFEDIT_region_IRAM3_start__ = 0x280E0000; // sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+define symbol __ICFEDIT_region_IRAM3_end__ = 0x280FFFFF; // sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; // code_flash_base_address + cm0plus_code_flash_reserve
+define symbol __ICFEDIT_region_IROM1_end__ = 0x1082FFFF; // cm7_0_code_flash_reserve
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+
+define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve
+
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol heap_reserve = __ICFEDIT_size_heap__;
+define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
+
+/* SRAM reservations */
+define symbol _base_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_start__;
+define symbol _size_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1;
+
+define symbol _base_SRAM_NON_CACHE = __ICFEDIT_region_IRAM3_start__;
+define symbol _size_SRAM_NON_CACHE = __ICFEDIT_region_IRAM3_end__ - __ICFEDIT_region_IRAM3_start__ + 1;
+
+/* Code flash reservations */
+define symbol _base_CODE_FLASH_CM0P = code_flash_base_address;
+define symbol _size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
+define symbol _base_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_start__;
+define symbol _size_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1;
+
+
+define symbol _base_SRAM = _base_SRAM_CM7_0;
+define symbol _size_SRAM = _size_SRAM_CM7_0;
+define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
+define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
+
+
+/*============================================================
+ * Memory definitions
+ *============================================================
+ */
+
+define memory mem with size = 4G;
+
+define region SRAM = mem:[from _base_SRAM size _size_SRAM ];
+define region SRAM_NONCACHE = mem:[from _base_SRAM_NON_CACHE size _size_SRAM_NON_CACHE];
+define region CODE_FLASH = mem:[from _base_CODE_FLASH size _size_CODE_FLASH ];
+
+/*============================================================
+ * Block definitions
+ *============================================================
+ */
+define block CSTACK with alignment = 8, size = stack_reserve { };
+define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
+define block HEAP_STACK { block HEAP, last block CSTACK };
+define block CM0P_RO with size = (_size_CODE_FLASH_CM0P) { readonly section .cy_m0p_image };
+define block CY_SHAREDMEM with alignment = 32 { section .cy_sharedmem };
+
+/*============================================================
+ * Initialization
+ *============================================================
+ */
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*============================================================
+ * Placement
+ *============================================================
+ */
+
+/* Flash - Cortex-M0+ application image */
+place at address (_base_CODE_FLASH_CM0P) { block CM0P_RO };
+
+/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
+/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
+
+place at start of CODE_FLASH { section .intvec };
+place in CODE_FLASH { readonly };
+
+place in SRAM { readwrite };
+place at end of SRAM { block HEAP_STACK };
+
+place in SRAM_NONCACHE { block CY_SHAREDMEM };
+
+keep { section .intvec };
+keep { section .cy_m0p_image };
+
+/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
+ * use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
+ * the area of SRAM where "ROM type" sections are linked to
+ */
+define exported symbol __ecc_init_sram_start_address = start(SRAM);
+define exported symbol __ecc_init_sram_end_address = end(SRAM);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker_d.icf b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker_d.icf
new file mode 100644
index 0000000..5c4e613
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/TOOLCHAIN_IAR/linker_d.icf
@@ -0,0 +1,222 @@
+/*******************************************************************************
+* \file xmc7200d_x8384_cm7.icf
+* \version 1.0.0
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+define symbol sram_start_reserve = 0;
+
+define symbol sram_total_size = 0x00100000;
+define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+define symbol sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
+define symbol cm7_0_sram_reserve = 0x000CC000; /* 838K: cm7_0 sram size */
+define symbol cm7_1_sram_reserve = 0x00010000; /* 64K : cm7_1 sram size */
+define symbol cm7_sram_non_cache_reserve = 0x00020000; /* 128K :non-cacheable sram size */
+
+define symbol code_flash_total_size = 0x00830000; /* 8384K: total flash size */
+define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
+define symbol cm7_0_code_flash_reserve = 0x00200000; /* 2048K: cm7_0 flash size */
+
+
+define symbol code_flash_base_address = 0x10000000;
+define symbol sram_base_address = 0x28000000;
+
+define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
+
+define symbol cm7_heap_reserve = 0x00001000;
+define symbol cm7_stack_reserve = 0x00001000;
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM7 cores.
+ * You can change the memory allocation by editing RAM and Flash values.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'xmc7200d_x8384_cm0plus.icf'.
+ * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
+ * after which cm0p core aplication must be build and flashed again.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; // sram_base_address + cm0plus_sram_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x280CFFFF; // cm7_0_sram_reserve
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x280D0000; // sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x280DFFFF; // sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve - cm7_sram_non_cache_reserve
+/* RAM non-cacheable ram */
+/* Always make sure that the starting address of the non-cacheable region is aligned to the non-cacheable region size boundary. */
+define symbol __ICFEDIT_region_IRAM3_start__ = 0x280E0000; // sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve + cm7_1_sram_reserve;
+define symbol __ICFEDIT_region_IRAM3_end__ = 0x280FFFFF; // sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve - cm7_1_sram_reserve;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; // code_flash_base_address + cm0plus_code_flash_reserve
+define symbol __ICFEDIT_region_IROM1_end__ = 0x1027FFFF; // cm7_0_code_flash_reserve
+define symbol __ICFEDIT_region_IROM2_start__ = 0x10280000; // code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve
+define symbol __ICFEDIT_region_IROM2_end__ = 0x1082FFFF; // code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve
+
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+
+define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve
+
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol heap_reserve = __ICFEDIT_size_heap__;
+define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
+
+/* SRAM reservations */
+define symbol _base_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_start__;
+define symbol _size_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1;
+define symbol _base_SRAM_CM7_1 = __ICFEDIT_region_IRAM2_start__;
+define symbol _size_SRAM_CM7_1 = __ICFEDIT_region_IRAM2_end__ - __ICFEDIT_region_IRAM2_start__ + 1;
+define symbol _base_SRAM_NON_CACHE = __ICFEDIT_region_IRAM3_start__;
+define symbol _size_SRAM_NON_CACHE = __ICFEDIT_region_IRAM3_end__ - __ICFEDIT_region_IRAM3_start__ + 1;
+
+/* Code flash reservations */
+define symbol _base_CODE_FLASH_CM0P = code_flash_base_address;
+define symbol _size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
+define symbol _base_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_start__;
+define symbol _size_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1;
+define symbol _base_CODE_FLASH_CM7_1 = __ICFEDIT_region_IROM2_start__;
+define symbol _size_CODE_FLASH_CM7_1 = __ICFEDIT_region_IROM2_end__ - __ICFEDIT_region_IROM2_start__ + 1;
+
+if(isdefinedsymbol(_CORE_CM7_1_))
+{
+ define symbol _base_SRAM = _base_SRAM_CM7_1;
+ define symbol _size_SRAM = _size_SRAM_CM7_1;
+ define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_1;
+ define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_1;
+}
+
+if(isdefinedsymbol(_CORE_CM7_0_))
+{
+ define symbol _base_SRAM = _base_SRAM_CM7_0;
+ define symbol _size_SRAM = _size_SRAM_CM7_0;
+ define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
+ define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
+}
+
+/* Note: If _CORE_CM7_1_ or _CORE_CM7_0_ is not defined in linker option then Linking will fail */
+
+/*============================================================
+ * Memory definitions
+ *============================================================
+ */
+
+define memory mem with size = 4G;
+
+define region SRAM = mem:[from _base_SRAM size _size_SRAM ];
+if(isdefinedsymbol(_CORE_CM7_0_))
+{
+define region SRAM_NONCACHE = mem:[from _base_SRAM_NON_CACHE size _size_SRAM_NON_CACHE];
+}
+define region CODE_FLASH = mem:[from _base_CODE_FLASH size _size_CODE_FLASH ];
+
+/*============================================================
+ * Block definitions
+ *============================================================
+ */
+define block CSTACK with alignment = 8, size = stack_reserve { };
+define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
+define block HEAP_STACK { block HEAP, last block CSTACK };
+define block CM0P_RO with size = (_size_CODE_FLASH_CM0P) { readonly section .cy_m0p_image };
+if(isdefinedsymbol(_CORE_CM7_0_))
+{
+define block CY_SHAREDMEM with alignment = 32 { section .cy_sharedmem };
+}
+
+/*============================================================
+ * Initialization
+ *============================================================
+ */
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+/*============================================================
+ * Placement
+ *============================================================
+ */
+
+/* Flash - Cortex-M0+ application image */
+place at address (_base_CODE_FLASH_CM0P) { block CM0P_RO };
+
+/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
+/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
+
+place at start of CODE_FLASH { section .intvec };
+place in CODE_FLASH { readonly };
+
+place in SRAM { readwrite };
+place at end of SRAM { block HEAP_STACK };
+
+if(isdefinedsymbol(_CORE_CM7_0_))
+{
+place in SRAM_NONCACHE { block CY_SHAREDMEM };
+}
+
+keep { section .intvec };
+keep { section .cy_m0p_image };
+
+/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
+ * use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
+ * the area of SRAM where "ROM type" sections are linked to
+ */
+define exported symbol __ecc_init_sram_start_address = start(SRAM);
+define exported symbol __ecc_init_sram_end_address = end(SRAM);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
deleted file mode 100644
index cd13ca8..0000000
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*******************************************************************************
-* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#ifndef __STARTUP_CAT1C_H__
-#define __STARTUP_CAT1C_H__
-
-#define FIXED_EXP_NR (15u)
-#define VECTORTABLE_SIZE (16u + FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
-#define VECTORTABLE_ALIGN (128) /* alignment for 85 entries (32x4=128) is 2^7=128 bytes */
-
-
-#endif /* __STARTUP_CAT1C_H__ */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
index ccdfec2..c75629f 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
+* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -129,10 +129,12 @@
* The Handler is called when the CPU interrupt0 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr0_Handler(void)
{
CM7_CpuIntr_Handler(0);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -142,10 +144,12 @@
* The Handler is called when the CPU interrupt1 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr1_Handler(void)
{
CM7_CpuIntr_Handler(1);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -155,10 +159,12 @@
* The Handler is called when the CPU interrupt2 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr2_Handler(void)
{
CM7_CpuIntr_Handler(2);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -168,10 +174,12 @@
* The Handler is called when the CPU interrupt3 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr3_Handler(void)
{
CM7_CpuIntr_Handler(3);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -181,10 +189,13 @@
* The Handler is called when the CPU interrupt4 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr4_Handler(void)
{
CM7_CpuIntr_Handler(4);
}
+CY_SECTION_ITCM_END
+
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr5_Handler
@@ -193,10 +204,12 @@
* The Handler is called when the CPU interrupt5 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr5_Handler(void)
{
CM7_CpuIntr_Handler(5);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -206,10 +219,12 @@
* The Handler is called when the CPU interrupt6 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr6_Handler(void)
{
CM7_CpuIntr_Handler(6);
}
+CY_SECTION_ITCM_END
/*******************************************************************************
@@ -219,10 +234,12 @@
* The Handler is called when the CPU interrupt7 occurs.
*
*******************************************************************************/
+CY_SECTION_ITCM_BEGIN
void Default_CpuIntr7_Handler(void)
{
CM7_CpuIntr_Handler(7);
}
+CY_SECTION_ITCM_END
void NMIException_Handler (void) __attribute__ ((weak, alias("Default_NMIException_Handler")));
@@ -288,6 +305,14 @@
_Pragma("GCC diagnostic pop")
#endif /* __GNUC__ */
+#ifdef ENABLE_CM7_DATA_CACHE
+static void cy_cache_update(void)
+{
+ SCB_CleanDCache();
+ SCB_InvalidateICache();
+}
+#endif /* ENABLE_CM7_DATA_CACHE */
+
/* Provide empty __WEAK implementation for the low-level initialization
routine required by the RTOS-enabled applications.
clib-support library provides FreeRTOS-specific implementation:
@@ -304,8 +329,25 @@
void software_init_hook();
void software_init_hook()
{
+#ifdef ENABLE_CM7_DATA_CACHE
+ cy_cache_update();
+#endif /* ENABLE_CM7_DATA_CACHE */
cy_toolchain_init();
}
+
+#elif defined(__ARMCC_VERSION)
+/*
+ * ARMClang constructor attribute, function will be
+ * automatically executed before main when the program starts
+ * */
+void __attribute__((constructor)) software_init_hook(void)
+{
+#ifdef ENABLE_CM7_DATA_CACHE
+ cy_cache_update();
+#endif /* ENABLE_CM7_DATA_CACHE */
+ cy_toolchain_init();
+}
+
#elif defined(__ICCARM__)
/* Initialize data section */
void __iar_data_init3(void);
@@ -324,12 +366,34 @@
/**/
#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+#if !defined(CY_DEVICE_TVIIC2D6M)
+#ifdef ENABLE_CM7_DATA_CACHE
+static void config_noncacheable_region(void)
+{
+
+ ARM_MPU_Disable();
+ /* Configure 128KB of SRAM as a non-cache region starting from BASE_SRAM_NON_CACHE
+ Always make sure that the starting address of the non-cacheable region is aligned to the non-cacheable region size boundary.
+ */
+ ARM_MPU_SetRegionEx(0, (uint32_t)BASE_SRAM_NON_CACHE, \
+ ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 0x1, 0, 0, 0, 0, \
+ ARM_MPU_REGION_SIZE_128KB));
+ ARM_MPU_Enable(0x4);
+
+}
+#endif /* ENABLE_CM7_DATA_CACHE */
+#endif
// Reset Handler
void Reset_Handler(void)
{
/* disable global interrupt */
__disable_irq();
+#if !defined(CY_DEVICE_TVIIC2D6M)
+#ifdef ENABLE_CM7_DATA_CACHE
+ config_noncacheable_region();
+#endif /* ENABLE_CM7_DATA_CACHE */
+#endif
/* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register
* (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0]) */
@@ -398,6 +462,10 @@
/* Initialize data section */
__iar_data_init3();
+#ifdef ENABLE_CM7_DATA_CACHE
+ cy_cache_update();
+#endif /* ENABLE_CM7_DATA_CACHE */
+
/* Initialization hook for RTOS environment */
cy_toolchain_init();
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
deleted file mode 100644
index e6b7373..0000000
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/***************************************************************************//**
-* \file system_cat1c.h
-* \version 1.0
-*
-* \brief Device system header file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-
-#ifndef _SYSTEM_FACELIFT_H_
-#define _SYSTEM_FACELIFT_H_
-
-/**
-* \addtogroup group_system_config_cm7
-* \{
-* Provides device startup, system configuration, and linker script files.
-* The system startup provides the followings features:
-* - \ref group_system_config_device_memory_definition_cm7
-* - \ref group_system_config_device_initialization_cm7
-* - \ref group_system_config_heap_stack_config_cm7
-* - \ref group_system_config_default_handlers_cm7
-* - \ref group_system_config_device_vector_table_cm7
-* - \ref group_system_config_cm7_functions
-*
-* \section group_system_config_configuration_cm7 Configuration Considerations
-*
-* \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition
-* Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts.
-*
-* \note - The linker files provided with the PDL are generic and handle all common
-* use cases. Your project may not use every section defined in the linker files.
-* In that case you may see warnings during the build process. To eliminate build
-* warnings in your project, you can simply comment out or remove the relevant
-* code in the linker file.
-*
-* \note - There is a common linker script for both CM7_0 and CM7_1 core.
-* By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system.
-* For example, below piece of code is implemented in the build system.
-* \code
-* ifeq ($(TOOLCHAIN),IAR)
-* LDFLAGS += --config_def _CORE_cm7_1_=1
-* else ifeq ($(TOOLCHAIN),GCC_ARM)
-* LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1'
-* endif
-* \endcode
-*
-* <b>ARM GCC</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
-* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
-* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
-* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
-* Cy_SysEnableCM7() function call.
-* By default,
-* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
-* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
-*
-* Change the flash and RAM sizes by editing the macro values in the
-* linker files for both CPUs:
-* - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group:
-* \code
-* cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
-* cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P
-* \endcode
-* - 'xx_yy_cm7.ld', where 'xx_yy' is the device group:
-* \code
-* ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM
-* flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
-* flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
-* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
-* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
-* same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file,
-* where 'xx_yy' is the device group.
-*
-* - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
-* in the 'system_xx.h', where 'xx' is the device family:\n
-* \code
-* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
-* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
-* \endcode
-* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
-*
-* <b>ARM Compiler</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
-* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
-*
-* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
-* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
-* Cy_SysEnableCM7() function call.
-* By default,
-* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
-* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
-*
-* \note The linker files provided with the PDL are generic and handle all common
-* use cases. Your project may not use every section defined in the linker files.
-* In that case you may see the warnings during the build process:
-* L6314W (no section matches pattern) and/or L6329W
-* (pattern only matches removed unused sections). In your project, you can
-* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-* the linker. You can also comment out or remove the relevant code in the linker
-* file.
-*
-* Change the flash and RAM sizes by editing the macros value in the
-* linker files for both CPUs:
-* - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group:
-* \code
-* #define SRAM_BASE_ADDRESS 0x28000000
-* #define CM0PLUS_SRAM_RESERVE 0x00020000
-* #define CODE_FLASH_BASE_ADDRESS 0x10000000
-* #define CM0PLUS_CODE_FLASH_RESERVE 0x00080000
-* \endcode
-* - 'xx_yy_cm7.sct', where 'xx_yy' is the device group:
-* \code
-* #define SRAM_BASE_ADDRESS 0x28000000 //SRAM START
-* #define CM7_0_SRAM_RESERVE 0x00060000 //cm7_0 sram size
-* #define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
-* #define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
-* //In case of dual CM7-core MCU device device
-* #define SIZE_SRAM_CM7_1 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE
-* #define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
-*
-* #define CODE_FLASH_BASE_ADDRESS 0x10000000 //FLASH START
-* #define CM7_0_CODE_FLASH_RESERVE 0x00200000 //cm7_0 flash size
-* #define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
-* #define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
-* //In case of dual CM7-core MCU device device
-* #define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
-* #define SIZE_CODE_FLASH_CM7_1 CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
-* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
-* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
-* same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file,
-* where 'xx_yy' is the device group.
-*
-* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
-* in the 'system_xx.h', where 'xx' is the device family:\n
-* \code
-* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
-* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
-* \endcode
-* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
-
-* <b>IAR</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
-* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
-* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
-* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
-* Cy_SysEnableCM7() function call.
-* By default,
-* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
-* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
-*
-* Change the flash and RAM sizes by editing the macros value in the
-* linker files for both CPUs:
-* - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group:
-* \code
-* define symbol sram_base_address = 0x28000000;
-* define symbol cm0plus_sram_reserve = 0x00020000; //cm0 sram size
-* define symbol code_flash_base_address = 0x10000000;
-* define symbol cm0plus_code_flash_reserve = 0x00080000; //cm0 flash size
-* \endcode
-* - 'xx_yy_cm7.icf', where 'xx_yy' is the device group:
-* \code
-* define symbol sram_base_address = 0x28000000;
-* define symbol cm7_0_sram_reserve = 0x00060000;
-* define symbol _base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
-* define symbol _size_SRAM_CM7_0 = cm7_0_sram_reserve;
-* //In case of dual CM7-core MCU device device
-* define symbol _base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
-* define symbol _size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
-*
-* define symbol code_flash_base_address = 0x10000000;
-* define symbol cm7_0_code_flash_reserve = 0x00200000;
-* define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
-* define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
-* //In case of dual CM7-core MCU device device
-* define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
-* define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
-* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
-* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
-* same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file,
-* where 'xx_yy' is the device group.
-*
-* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
-* in the 'system_xx.h', where 'xx' is the device family:\n
-* \code
-* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
-* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
-* \endcode
-* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
-*
-* \subsection group_system_config_device_initialization_cm7 Device Initialization
-* After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup.
-* The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup.
-* The startup code is the piece of code which is executed after every system reset.
-* It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function.
-* The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core.
-*
-* The CM0+ startup code implements the following functions to run the CM0+ application:
-*
-* 1. In the Reset Handler, it disables global interrupts
-* 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core,
-* sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet.
-* 4. Calls SystemInit() function
-* - Initializes and enables the SRAM memory for ECC
-* - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
-* - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority,
-* then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1.
-* So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1
-* - Unlocks and disable WDT (Watchdog timer)
-* - Calls the SystemCoreClockUpdate()
-* 5. Executes main() application
-*
-* The CM7 startup code implement the following functions to run the CM7 user application:
-*
-* 1. In the Reset handler, it disables global interrupts
-* 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register
-* 3. Enables CM7 core ITCM and DTCM
-* 4. Enables the FPU if it is used
-* 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
-* 6. Enables the CM7 core instruction and data cache
-* 7. Calls SystemInit() function
-* - Unlocks and disable WDT (Watchdog timer)
-* - Calls the SystemCoreClockUpdate()
-* 6. Executes CM7 main() application
-*
-* \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration
-* By default, the stack size is set to 0x00001000 and the Heap size is allocated
-* dynamically to the whole available free memory up to stack memory.
-* The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address.
-* The Heap grows opposite of Stack. It grows from lower to higher address.
-* The Heap top starts from end of used data section till Stack end.
-*
-* \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC
-* <b>Editing source code files</b>\n
-* The stack size is defined in the linker script files: 'xx_yy_zz.ld',
-* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
-* 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
-* Change the stack size by modifying the following line:\n
-* \code STACK_SIZE = 0x1000; \endcode
-*
-* \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler
-* <b>Editing source code files</b>\n
-* The stack size is defined in the linker script files: 'xx_yy_zz.sct',
-* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
-* 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
-* Change the stack size by modifying the following line:\n
-* \code #define STACK_SIZE 0x1000 \endcode
-*
-* \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR
-* <b>Editing source code files</b>\n
-* The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf',
-* where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
-* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
-* Change the heap and stack sizes by modifying the following lines:\n
-* \code define symbol cm7_stack_reserve = 0x00001000; \endcode
-*
-* \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition
-* The default interrupt handler functions are defined as weak functions to a dummy
-* handler in the startup file. The naming convention for the interrupt handler names
-* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
-* user code by defining the handler function using the same name. For example:
-* \code
-* void scb_0_interrupt_IRQHandler(void)
-*{
-* ...
-*}
-* \endcode
-*
-* \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM
-* This process uses memory sections defined in the linker script. The startup
-* code actually defines the contents of the vector table and performs the copy.
-*
-* \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC
-* The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
-* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
-* It defines sections and locations in memory.\n
-* Copy interrupt vectors from flash to RAM: \n
-* From: \code LONG (__Vectors) \endcode
-* To: \code LONG (__ram_vectors_start__) \endcode
-* Size: \code LONG (__Vectors_End - __Vectors) \endcode
-* The vector table address (and the vector table itself) are defined in the
-* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
-* The code in these files copies the vector table from Flash to RAM.
-*
-* \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler
-* The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
-* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and
-* 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table
-* (RESET_RAM) shall be first in the RAM section.\n
-* RESET_RAM represents the vector table. It is defined in the startup
-* files (e.g. startup_cm0plus.S and startup_cm7.c).
-* The code in these files copies the vector table from Flash to RAM.
-*
-* \subsubsection group_system_config_device_vector_table_iar_cm7 IAR
-* The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
-* for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and '
-* 'xmc7100d_x4160_cm0plus.icf'.\n
-* The vector table address (and the vector table itself) are defined in the
-* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
-* The code in these files copies the vector table from Flash to RAM.
-*
-* \section group_system_config_changelog_cm7 Changelog
-* <table class="doxtable">
-* <tr>
-* <th>Version</th>
-* <th>Changes</th>
-* <th>Reason for Change</th>
-* </tr>
-* <tr>
-* <td>1.0</td>
-* <td>Initial version</td>
-* <td></td>
-* </tr>
-* </table>
-*
-* \defgroup group_system_config_macro_cm7 Macros
-* \{
-* \defgroup group_system_config_system_macro_cm7 System Macros
-* \}
-* \defgroup group_system_config_functions_cm7 Functions
-* \{
-* \defgroup group_system_config_cm7_functions Cortex-M7 Control
-* \}
-* \}
-*/
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*******************************************************************************
-* Include files
-*******************************************************************************/
-#include <stdint.h>
-#include "xmc7xxx_partition.h"
-
-/*******************************************************************************
-* Global preprocessor symbols/macros ('define')
-*******************************************************************************/
-#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
- (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
- (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
- #define CY_SYSTEM_CPU_CM0P 1UL
-#else
- #define CY_SYSTEM_CPU_CM0P 0UL
-#endif
-
-
-/*******************************************************************************
-*
-* START OF USER SETTINGS HERE
-* ===========================
-*
-* All lines with '<<<' can be set by user.
-*
-*******************************************************************************/
-
-/**
-* \addtogroup group_system_config_system_macro_cm7
-* \{
-*/
-
-/*******************************************************************************
-*
-* END OF USER SETTINGS HERE
-* =========================
-*
-*******************************************************************************/
-
-/** Start address of the Cortex-M7_0 application */
-#ifndef CY_CORTEX_M7_0_APPL_ADDR
- #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
-#endif
-
-/** Start address of the Cortex-M7_1 application */
-#ifndef CY_CORTEX_M7_1_APPL_ADDR
- #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
-#endif
-
-/** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */
-#define CY_SYS_CM7_STATUS_ENABLED (3U)
-/** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */
-#define CY_SYS_CM7_STATUS_DISABLED (0U)
-/** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */
-#define CY_SYS_CM7_STATUS_RETAINED (2U)
-/** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */
-#define CY_SYS_CM7_STATUS_RESET (1U)
-/** \} group_system_config_system_macro_cm7 */
-
-/** \cond */
-/** Cortex-M7 core 0 */
-#define CORE_CM7_0 (0U)
-/** Cortex-M7 core 1 */
-#define CORE_CM7_1 (1U)
-/** Error Selection */
-#define CORE_MAX (2U)
-
-extern uint32_t cy_delayFreqHz;
-extern uint32_t cy_delayFreqKhz;
-extern uint32_t cy_delayFreqMhz;
-
-extern uint32_t SystemCoreClock;
-extern uint32_t cy_Hfclk0FreqHz;
-extern uint32_t cy_PeriClkFreqHz;
-extern uint32_t cy_AhbFreqHz;
-
-extern void SystemInit(void);
-extern void SystemIrqInit(void);
-extern void SystemCoreClockUpdate(void);
-
-/** \endcond */
-
-/**
-* \addtogroup group_system_config_cm7_functions
-* \{
-*/
-/*******************************************************************************
-* Function Name: Cy_SysGetCM7Status
-****************************************************************************//**
-*
-* Gets the Cortex-M7 core power mode.
-*
-* \param core Core type (CM7_0 or CM7_1).
-*
-* \return \ref group_system_config_system_macro_cm7 \n
-* If 0: CY_SYS_CM7_STATUS_DISABLED \n
-* 1: CY_SYS_CM7_STATUS_RESET \n
-* 2: CY_SYS_CM7_STATUS_RETAINED \n
-* 3: CY_SYS_CM7_STATUS_ENABLED \n
-*
-******************************************************************************/
-extern uint32_t Cy_SysGetCM7Status(uint8_t core);
-/*******************************************************************************
-* Function Name: Cy_SysEnableCM7
-****************************************************************************//**
-*
-* Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled
-* or retained mode.
-*
-* \param core Core type (CM7_0 or CM7_1).
-*
-* \param vectorTableOffset The offset of the vector table base address from
-* memory address 0x00000000. The offset should be multiple to 1024 bytes.
-*
-*******************************************************************************/
-extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
-/*******************************************************************************
-* Function Name: Cy_SysDisableCM7
-****************************************************************************//**
-*
-* Disables the Cortex-M7 core.
-*
-* \param core Core type (CM7_0 or CM7_1).
-*
-* \warning Do not call the function while the Cortex-M7 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-extern void Cy_SysDisableCM7(uint8_t core);
-/*******************************************************************************
-* Function Name: Cy_SysRetainCM7
-****************************************************************************//**
-*
-* Retains the Cortex-M7 core.
-*
-* \param core Core type (CM7_0 or CM7_1).
-*
-* \warning Do not call the function while the Cortex-M7 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-extern void Cy_SysRetainCM7(uint8_t core);
-/*******************************************************************************
-* Function Name: Cy_SysResetCM7
-****************************************************************************//**
-*
-* Resets the Cortex-M7 core.
-*
-* \param core Core type (CM7_0 or CM7_1).
-*
-* \warning Do not call the function while the Cortex-M7 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-extern void Cy_SysResetCM7(uint8_t core);
-/** \} group_system_config_cm7_functions */
-
-
-/** \cond */
-
-extern void Default_Handler (void);
-
-extern void Cy_SystemInit(void);
-extern void Cy_SystemInitFpuEnable(void);
-extern void CyMain(void);
-
-#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
-#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
-/** \endcond */
-
-
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SYSTEM_FACELIFT_H_ */
-
-
-/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
index 80058f3..3a6c32f 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_cm7.c
-* \version 1.0
+* \version 1.2
*
* The device system-source file.
*
********************************************************************************
* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
+* Copyright 2021-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -55,7 +55,7 @@
/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
CY_NOINIT uint32_t SystemCoreClock ;
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). Note that the HfClk0 does not source any CPU core directly. */
CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
@@ -166,24 +166,18 @@
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
- uint32_t pathFreqHz;
- uint32_t clkHfPath;
+ /* Get frequency for the fast clock source of the core we are currently building for. */
+ #if defined (CORE_NAME_CM7_0) && (CORE_NAME_CM7_0 == 1)
+ SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(0);
+ #else
+ SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(1);
+ #endif
- /* Get frequency for the high-frequency clock # 0 */
- clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+ /* This is part of the clock tree for the CM0+; do not use for CM7 clock calculations. */
+ cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM);
- pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
-
- SystemCoreClock = pathFreqHz;
-
- cy_Hfclk0FreqHz = SystemCoreClock;
-
- /* Get frequency for the high-frequency clock # 2 , whcih is used for PERI PCLK*/
- clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
-
- pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
-
- cy_PeriClkFreqHz = pathFreqHz;
+ /* Get frequency for the high-frequency clock # 2 , which is used for PERI PCLK. */
+ cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM);
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
@@ -218,7 +212,7 @@
* The system interrupt mapped to CPU interrupt will be fetched and executed
*
*******************************************************************************/
-
+CY_SECTION_ITCM_BEGIN
void CM7_CpuIntr_Handler(uint8_t intrNum)
{
uint32_t system_int_idx;
@@ -242,5 +236,5 @@
#endif
NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
}
-
+CY_SECTION_ITCM_END
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/bsp.mk b/boot/cypress/platforms/BSP/XMC7000/system/bsp.mk
new file mode 100644
index 0000000..7bb1fdc
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/bsp.mk
@@ -0,0 +1,77 @@
+################################################################################
+# \file bsp.mk
+#
+# \brief
+# Define the KIT-XMC72-EVK target.
+#
+################################################################################
+# \copyright
+# Copyright 2021-2024 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+ifeq ($(WHICHFILE),true)
+$(info Processing $(lastword $(MAKEFILE_LIST)))
+endif
+
+# Any additional components to apply when using this board.
+# Use a default CM0+ image (XMC7x_CM0P_SLEEP). This can be swapped for a
+# different pre-built image or removed if custom built project.
+BSP_COMPONENTS:=XMC7x_CM0P_SLEEP
+
+# Any additional defines to apply when using this board.
+BSP_DEFINES:=CYBSP_WIFI_WL_REG_ON_GPIO_DRIVE_MODE=CYHAL_GPIO_DRIVE_STRONG
+
+# Path to the flash loaders to patch for this board
+CY_QSPI_FLM_DIR=$(MTB_TOOLS__TARGET_DIR)/config/FlashLoaders/
+
+# Path to the patched flash loaders for this board
+CY_QSPI_FLM_DIR_OUTPUT=$(MTB_TOOLS__TARGET_DIR)/config/GeneratedSource/
+
+ifneq (,$(filter XMC7x_CM0P_SLEEP, $(BSP_COMPONENTS)))
+BSP_LINKER_CORE:=linker
+else
+BSP_LINKER_CORE:=linker_d
+endif
+ifeq ($(TOOLCHAIN),GCC_ARM)
+ BSP_LINKER_SCRIPT_EXT:=ld
+else ifeq ($(TOOLCHAIN),ARM)
+ BSP_LINKER_SCRIPT_EXT:=sct
+else ifeq ($(TOOLCHAIN),IAR)
+ BSP_LINKER_SCRIPT_EXT:=icf
+endif
+MTB_BSP__LINKER_SCRIPT=$(MTB_TOOLS__TARGET_DIR)/COMPONENT_$(MTB_RECIPE__CORE)/TOOLCHAIN_$(TOOLCHAIN)/$(BSP_LINKER_CORE).$(BSP_LINKER_SCRIPT_EXT)
+
+################################################################################
+# ALL ITEMS BELOW THIS POINT ARE AUTO GENERATED BY THE BSP ASSISTANT TOOL.
+# DO NOT MODIFY DIRECTLY. CHANGES SHOULD BE MADE THROUGH THE BSP ASSISTANT.
+################################################################################
+
+# Board device selection. MPN_LIST tracks what was selected in the BSP Assistant
+# All other variables are derived by BSP Assistant based on the MPN_LIST.
+MPN_LIST:=XMC7200D-E272K8384
+DEVICE:=XMC7200D-E272K8384
+DEVICE_COMPONENTS:=CAT1 CAT1C CAT1C8M
+DEVICE_LIST:=XMC7200D-E272K8384
+DEVICE_TOOL_IDS:=bsp-assistant device-configurator dfuh-tool library-manager memory-analyzer motor-suite-gui project-creator qspi-configurator smartio-configurator
+DEVICE_XMC7200D-E272K8384_CORES:=CORE_NAME_CM0P_0 CORE_NAME_CM7_0 CORE_NAME_CM7_1
+DEVICE_XMC7200D-E272K8384_DIE:=TVIIBH8M
+DEVICE_XMC7200D-E272K8384_FEATURES:=CM7_0_FPU_PRESENT CM7_1_FPU_PRESENT
+DEVICE_XMC7200D-E272K8384_FLASH_KB:=8384
+DEVICE_XMC7200D-E272K8384_IPBLOCKS:=M7CPUSS M7CPUSS_V1 MXAUDIOSS_VER2_S40E MXAUDIOSS_VER2_S40E_V2 MXDFT MXDFT_V1 MXEFUSE_VER2 MXEFUSE_VER2_V2 MXETH MXETH_V1 MXEVTGEN MXEVTGEN_V1 MXFLEXRAY MXFLEXRAY_V1 MXLIN MXLIN_V1 MXPERI_VER3 MXPERI_VER3_V3 MXS40EPASS MXS40EPASS_V1 MXS40IOSS MXS40IOSS_V3 MXS40SRSS_VER3 MXS40SRSS_VER3_V3 MXSCB_VER2_S40E MXSCB_VER2_S40E_V2 MXSDHC MXSDHC_V1 MXSMIF_VER2_S40E MXSMIF_VER2_S40E_V2 MXTCPWM_VER2 MXTCPWM_VER2_V2 MXTTCANFD_S40E MXTTCANFD_S40E_V1
+DEVICE_XMC7200D-E272K8384_SRAM_KB:=1024
+RECIPE_DIR:=$(SEARCH_recipe-make-cat1c)
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.c b/boot/cypress/platforms/BSP/XMC7000/system/cybsp.c
similarity index 98%
rename from boot/cypress/platforms/BSP/XMC7000/cybsp.c
rename to boot/cypress/platforms/BSP/XMC7000/system/cybsp.c
index 6f08f7a..00c25fd 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/cybsp.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.h b/boot/cypress/platforms/BSP/XMC7000/system/cybsp.h
similarity index 97%
rename from boot/cypress/platforms/BSP/XMC7000/cybsp.h
rename to boot/cypress/platforms/BSP/XMC7000/system/cybsp.h
index 7ba085f..cd27cf6 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/cybsp.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_doc.h
similarity index 99%
rename from boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
rename to boot/cypress/platforms/BSP/XMC7000/system/cybsp_doc.h
index 5378efd..30363dc 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_doc.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_hw_config.h
similarity index 95%
rename from boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
rename to boot/cypress/platforms/BSP/XMC7000/system/cybsp_hw_config.h
index b8f3546..a6c9bad 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_hw_config.h
@@ -7,7 +7,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_types.h
similarity index 87%
rename from boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
rename to boot/cypress/platforms/BSP/XMC7000/system/cybsp_types.h
index c20d555..e7b5e4b 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/cybsp_types.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@@ -20,6 +20,7 @@
#pragma once
+#include "cybsp_hw_config.h"
#include "cybsp_doc.h"
#if defined(__cplusplus)
@@ -52,11 +53,19 @@
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
+#if defined(COMPONENT_CAT1D)
+#define CYBSP_LED_STATE_ON (1U)
+#else
#define CYBSP_LED_STATE_ON (0U)
+#endif /* defined(COMPONENT_CAT1D) */
#endif
/** Pin state for the LED off. */
#ifndef CYBSP_LED_STATE_OFF
+#if defined(COMPONENT_CAT1D)
+#define CYBSP_LED_STATE_OFF (0U)
+#else
#define CYBSP_LED_STATE_OFF (1U)
+#endif /* defined(COMPONENT_CAT1D) */
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
index cd13ca8..3540379 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
@@ -1,21 +1,3 @@
-/*******************************************************************************
-* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
#ifndef __STARTUP_CAT1C_H__
#define __STARTUP_CAT1C_H__
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
index 6f64626..4e28c28 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_cat1c.h
-* \version 1.0
+* \version 1.2
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
+* Copyright 2021-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -350,6 +350,16 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
+* <td>1.2</td>
+* <td>Fixed warning for the GCC 14 compiler.</td>
+* <td>Code improvements.</td>
+* </tr>
+* <tr>
+* <td>1.1</td>
+* <td>Restructured code.</td>
+* <td>Code improvement.</td>
+* </tr>
+* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
@@ -375,7 +385,11 @@
* Include files
*******************************************************************************/
#include <stdint.h>
+#if defined (CY_DEVICE_TVIIC2D6M)
+#include "tviic_partition.h"
+#else
#include "xmc7xxx_partition.h"
+#endif
/*******************************************************************************
* Global preprocessor symbols/macros ('define')
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
index 9c76d22..56f47ab 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
@@ -1,21 +1,3 @@
-/*******************************************************************************
-* \copyright
-* Copyright 2025 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
#if !defined(LAYOUT_CAT1C_H)
#define LAYOUT_CAT1C_H
@@ -29,6 +11,7 @@
#define SRAM_BASE_ADDRESS CY_SRAM_BASE /* SRAM START */
#define TOTAL_RAM CY_SRAM_SIZE
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K cm0plus */
+#define CM7_SRAM_NON_CACHE_RESERVE 0x00020000 /* 128K :non-cacheable sram size */
/* FLASH */
#define CODE_FLASH_BASE_ADDRESS CY_FLASH_LG_SBM_BASE /* FLASH START */
@@ -59,9 +42,12 @@
#define BASE_SRAM_CM0P (SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM)
#define SIZE_SRAM_CM0P (CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM)
#define BASE_SRAM_CM7_0 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
-#define SIZE_SRAM_CM7_0 TOTAL_RAM - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE
+#define SIZE_SRAM_CM7_0 TOTAL_RAM - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE - CM7_SRAM_NON_CACHE_RESERVE
#define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + SIZE_SRAM_CM7_0
+#define BASE_SRAM_NON_CACHE BASE_SRAM_CM7_1 + CM7_1_SRAM_RESERVE
+#define SIZE_SRAM_NON_CACHE CM7_SRAM_NON_CACHE_RESERVE
+
/* Code flash reservations */
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
diff --git a/boot/cypress/platforms/CYW20829.md b/boot/cypress/platforms/CYW20829.md
index d6e546b..4896929 100644
--- a/boot/cypress/platforms/CYW20829.md
+++ b/boot/cypress/platforms/CYW20829.md
@@ -2,57 +2,57 @@
### Prerequisites
-#### Edgeprotecttools
+#### EdgeProtectTools
The CYW20829/CYW89829 devices have a set of security features. A special tool called `edgeprotecttools` is required to use most of them.
-`Edgeprotecttools` is a Python package, which can be installed using the conventional `python pip` packet manager:
+EdgeProtectTools is a Python package, which can be installed using the conventional `python pip` package installer:
python -m pip install edgeprotecttools
-`Edgeprotecttools` is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption, and more. For more details on functionality, go to [https://pypi.org/project/edgeprotecttools](https://pypi.org/project/edgeprotecttools) or [https://github.com/Infineon/edgeprotecttools#provision-device](https://github.com/Infineon/edgeprotecttools#provision-device)
+EdgeProtectTools is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption, and more. For more details on functionality, go to [https://pypi.org/project/edgeprotecttools](https://pypi.org/project/edgeprotecttools) or [https://github.com/Infineon/edgeprotecttools#provision-device](https://github.com/Infineon/edgeprotecttools#provision-device)
-Invocation of edgeprotecttools is build-in post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
+Invocation of `edgeprotecttools` is built into the post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
-Requirements for `Edgeprotecttools` installation can be found [here](https://github.com/Infineon/edgeprotecttools?tab=readme-ov-file#prerequisites).
+Requirements for `edgeprotecttools` installation can be found [here](https://github.com/Infineon/edgeprotecttools?tab=readme-ov-file#prerequisites).
### MCUBootApp specifics
-The CYW20829/CYW89829 silicons can be provisioned in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829/CYW89829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
+The CYW20829/CYW89829 chips can be provisioned in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829/CYW89829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
- signing of images;
- - rollback protection (hardware secure counter).
+ - rollback protection (hardware secure counter).
-The work with the CYW20829/CYW89829 chips begin from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure on Secure.
+The work with the CYW20829/CYW89829 chips begins from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure or Secure.
### Device and environment initialization
-For the edgeprotecttools environment setup, the MCUboot `boot/cypress` folder is used.
+For the `edgeprotecttools` environment setup the `boot/cypress` folder is used.
To create a common configuration, use:
- edgeprotecttools -t cyw20829 init
+ edgeprotecttools -t <TARGET> --rev <REVISION> init
+
+Run the following command and use the name of your <TARGET> cyw20829 or cyw89829, and <REVISION> a0, b0 or b1. If the REVISION option is not specified, the `edgeprotecttools` will use the latest revision.
To configure an OpenOCD package path (via ModusToolbox™ Programming Tools by default):
- edgeprotecttools set-ocd --name openocd --path C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ edgeprotecttools set-ocd --name openocd --path C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
For SECURE `LCS`, a few more steps are necessary. You will need to generate an RSA key pair (or copy it to the keys folder, if it was generated previously), to provision a chip in Secure mode:
- edgeprotecttools -t cyw20829 -p policy/policy_secure.json create-key -k 0
+ edgeprotecttools -t <TARGET> -p policy/policy_secure.json create-key -k 0
To get access to the chip after provisioning, a debug certificate is required:
- edgeprotecttools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
-
-where N is the key number, zero or one.
+ edgeprotecttools -t <TARGET> -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k 0
### CYW20829/CYW89829 provisioning and reprovisioning
-For the first provision of the CYW20829 chip, use:
+For the first provision of the CYW20829 or CYW89829 chip, use:
- edgeprotecttools -t cyw20829 -p policy/policy_%LCS%.json provision-device
+ edgeprotecttools -t <TARGET> -p policy/policy_%LCS%.json provision-device
or
- edgeprotecttools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
+ edgeprotecttools -t <TARGET> -p policy/policy_reprovisioning_%LCS%.json reprovision-device
for the following reprovision procedure.
@@ -60,12 +60,12 @@
### Default memory map
-The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/memory/CYW20829/flashmap`. One can use the predefined flash map or define your own using the predefined file as a template.
+The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/memory/CYW20829/flashmap`. One can use the predefined flash map or create your own using the predefined file as a template.
### Direct-XIP mode support
-Additionally to the classic mode with `BOOT` and `UPGRADE` slots, MCUBoot for CYW20829/CYW89829 platform supports the `Direct-XIP` mode. The main difference is that both slots, named `Primary` and `Secondary`, are equal, and the image in one slot has no effect on the other image. In this mode, MCUBoot checks the version of the images and launches the application with the higher version number. The version number can be set via the `IMG_VER` command-line parameter. If both version numbers are equal, the image in the primary slot will be launched. The build number is not taken into account during version comparison; only the major, minor, and patch version numbers are considered.
-In the `Direct-XIP` mode, both images are treated like `UPGRADE` images. This implies that each image must set the `IMG_OK` flag during its first startup. If the `IMG_OK` flag is not set, the corresponding application will be erased, and the application from the other slot will be launched. If neither application sets the `IMG_OK` flag, MCUBoot will erase both applications. The `Direct-XIP` mode supports encrypted images. In this mode, the MCUBootApp and all images are encrypted using the same `AES-CTR` encryption key. For more information, refer to the `Encrypted image support` section.
+Additionally to the classic mode with `BOOT` and `UPGRADE` slots, MCUBootApp for CYW20829/CYW89829 platform supports the `Direct-XIP` mode. The main difference is that both slots, named `Primary` and `Secondary`, are equal, and the image in one slot has no effect on the other image. In this mode, MCUBootApp checks the version of the images and launches the application with the higher version number. The version number can be set via the `IMG_VER` command-line parameter. If both version numbers are equal, the image in the primary slot will be launched. The build number is not taken into account during version comparison; only the major, minor, and patch version numbers are considered.
+In the `Direct-XIP` mode, both images are treated like `UPGRADE` images. This implies that each image must set the `IMG_OK` flag during its first startup. If the `IMG_OK` flag is not set, the corresponding application will be erased, and the application from the other slot will be launched. If neither application sets the `IMG_OK` flag, MCUBootApp will erase both applications. The `Direct-XIP` mode supports encrypted images. In this mode, the MCUBootApp and all images are encrypted using the same `AES-CTR` encryption key. For more information, refer to the `Encrypted image support` section.
Another change is that the `APP_SLOT` command line parameter should be used for application compilation instead of the `IMG_TYPE` parameter. Use `APP_SLOT=1` for the `Primary` slot and `APP_SLOT=2` for the `Secondary`.
To enable the `Direct-XIP` mode, use the appropriate flash map, such as `cyw20829_direct_xip_single.json`
@@ -78,7 +78,7 @@
### Skip image validation
-To decrease the boot time of MCUBoot, image validation can be skipped before launching the application. This flow is recommended in cases where boot time is more important than reliability. To disable image validation for a selected slot, use the `MCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT=1` or `MCUBOOT_SKIP_VALIDATE_SECONDARY_SLOT=1` command-line parameter.
+To decrease the boot time of MCUBootApp, image validation can be skipped before launching the application. This flow is recommended in cases where boot time is more important than reliability. To disable image validation for a selected slot, use the `MCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT=1` or `MCUBOOT_SKIP_VALIDATE_SECONDARY_SLOT=1` command-line parameter.
To skip image validation entirely, the `MCUBOOT_SKIP_VALIDATE=1` option can be used.
### Direct-XIP APIs
@@ -86,7 +86,7 @@
The Direct-XIP API provides a comprehensive set of functions for managing firmware images and their associated metadata in boot slots. This API is designed to facilitate secure and reliable firmware updates in embedded systems and supports operations such as slot validation, image state management, and metadata handling. Below is a summary of the key API functions and their purposes.
- Image Validation:
-Use `boot_validate_slot_for_image_id` to ensure that the firmware image in a slot is valid before executing it. This API is useful when MCUBoot startup validation is disabled.
+Use `boot_validate_slot_for_image_id` to ensure that the firmware image in a slot is valid before executing it. This API is useful when MCUBootApp startup validation is disabled.
- Slot Management:
Use `boot_set_inactive_slot`, `boot_is_slot_inactive`, or `boot_set_pending_slot` to manage the activation and deactivation of firmware slots.
@@ -202,24 +202,24 @@
CYW20829/CYW89829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode, all code is decrypted transparently by the AES algorithm.
-MCUboot has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
+MCUBootApp has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
-**MCUboot image validation flow**
+**MCUBootApp image validation flow**
- Decrypt the AES key / initial vector (IV) from HKDF
- Set up AES IV + CTR nonce (Image addr = base_addr + header_size)
- Read slot data by MMIO
-- Decrypt the image in the slot using MCUboot internal functionality
+- Decrypt the image in the slot using MCUBootApp internal functionality
- Calculate and verify hash from decrypted data
- Validate the slot image by hash and sign it
-**MCUboot image upgrade flow**
+**MCUBootApp image upgrade flow**
- Read slot 1 sector data using MMIO
- Skip data decryption
- Write data to the primary slot using MMIO
-**MCUboot Application Run**
+**MCUBootApp Run**
- Set up SMIF registers
- Set the AES key
- Set AES IV
@@ -236,12 +236,12 @@
make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
-NOTE: In the case where a common AES-CTR key is used to encrypt both the MCUBoot and BlinkyApp applications, MCUBoot should be compiled first. This is because the common NONCE file for the AES-CTR algorithm is generated during the MCUBoot compilation. Since BlinkyApp will use the same NONCE file, it should be compiled after MCUBoot. This also applies to cases where MCUBoot is recompiled and a new NONCE file is generated.
+NOTE: In the case where a common AES-CTR key is used to encrypt both the MCUBootApp and BlinkyApp applications, MCUBoot should be compiled first. This is because the common NONCE file for the AES-CTR algorithm is generated during the MCUBootApp compilation. Since BlinkyApp will use the same NONCE file, it should be compiled after MCUBootApp. This also applies to cases where MCUBootApp is recompiled and a new NONCE file is generated.
#### Encrypted image support using secured encryption key
-The CYW20829 MCU supports on-the-fly XIP (eXecute In Place) encryption utilizing a provisioned AES-128 key in both `SECURE` and `NORMAL_NO_SECURE` lifecycles. SMIF encryption can be enabled only once, during the first device provisioning, and cannot be changed in the future.
-Information about key generation for image encryption and device provisioning can be found in the documentation for the `Edge Protect Tools` utility:
+The CYW20829/CYW89829 MCU supports on-the-fly XIP (eXecute In Place) encryption utilizing a provisioned AES-128 key in both `SECURE` and `NORMAL_NO_SECURE` lifecycles. SMIF encryption can be enabled only once, during the first device provisioning, and cannot be changed in the future.
+Information about key generation for image encryption and device provisioning can be found in the documentation for the EdgeProtectTools utility:
https://github.com/Infineon/edgeprotecttools/blob/master/docs/README_CYW20829.md#encrypt-the-user-application
NOTE: To enable SMIF encryption in the `NORMAL_NO_SECURE` LCS, you will need at least EdgeProtectTools version 1.5.0, and B0 revision of the silicon (or later).
@@ -252,22 +252,22 @@
##### Build Example
-Use the following command to build your application with XIP encryption enabled:
+Use the following commands to build your application with XIP encryption enabled:
```sh
-make app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json LCS=SECURE SMIF_ENC=1
+make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json LCS=SECURE SMIF_ENC=1
-make clean app BUILDCFG=Debug APP_NAME=BlinkyApp PLATFORM=CYW20829 FLASH_MAP=./platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json IMG_TYPE=UPGRADE SMIF_ENC=1
+make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=./platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json IMG_TYPE=UPGRADE SMIF_ENC=1
```
##### Preparing and Encrypting Application Images
-Users must prepare non-encrypted signed images for their applications and perform manual encryption using edgeprotecttools with the "encrypt" command. This command requires specifying the encryption key, nonce, and image address as the initial vector (IV).
+Users must prepare non-encrypted signed images for their applications and perform manual encryption using `edgeprotecttools` with the "encrypt" command. This command requires specifying the encryption key, nonce, and image address as the initial vector (IV).
##### Encryption Example
To encrypt your application binary, use the following command:
```sh
-edgeprotecttools -t cyw20829 encrypt --input BlinkyApp.bin --output BlinkyApp_encrypted.bin --iv 0x08020000 --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/CYW20829/Debug/MCUBootApp.signed_nonce.bin
+edgeprotecttools -t <TARGET> encrypt --input BlinkyApp.bin --output BlinkyApp_encrypted.bin --iv 0x08020000 --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/<TARGET>/Debug/MCUBootApp.signed_nonce.bin
```
**Parameters:**
@@ -277,7 +277,7 @@
- --enckey: The path to the encryption key file (e.g., keys/encrypt_key.bin).
- --nonce: The nonce used for MCUBootApp encryption. Specify the path to the autogenerated nonce file (e.g., ./MCUBootApp/out/CYW20829/Debug/MCUBootApp.signed_nonce.bin).
-By following these steps, you can ensure that your application binaries are securely encrypted and ready for execution on the CYW20829 MCU with on-the-fly XIP encryption enabled.
+By following these steps, you can ensure that your application binaries are securely encrypted and ready for execution on the CYW20829/CYW89829 MCU with on-the-fly XIP encryption enabled.
##### USE_IMG_TRAILER Parameter Description
The `USE_IMG_TRAILER` parameter provides developers with the ability to disable the generation of the image trailer and padding between the image body and the trailer, reducing the image size. This feature is useful for encrypted images. Padding bytes in encrypted images are transformed into random data, making the image size non-compressible. Disabling the trailer and padding reduces unnecessary overhead in such cases. By default, this parameter is enabled `USE_IMG_TRAILER=1`.
@@ -288,11 +288,11 @@
```sh
make app APP_NAME=BlinkyApp PLATFORM=CYW20829 FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json APP_SLOT=1 IMG_VER=1.0.0+100 USE_IMG_TRAILER=0
```
-NOTE: The application slot must be erased before writing the image when USE_IMG_TRAILER parameter is zero.
+NOTE: The application slot must be erased before programming the image with `USE_IMG_TRAILER=0`.
### Rollback protection Support
-As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829/CYW89829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829/CYW89829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
+As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829/CYW89829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829/CYW89829 is implemented as an eFuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of eFuse is burned.
The initial value of the rollback counter is programmed into the chip at the provisioning stage. The provisioning policy for Secure mode contains a corresponding field (file `policy/policy_secure.json`):
@@ -319,20 +319,20 @@
If the `nv_counter` value is left untouched, any image with counters higher than 0 and less than value defined by `bits_per_cnt` (or equal to) can be programmed into the chip.
-`bits_per_cnt` also defines a distribution of eFuse among images in system. For example, in first case MCUBootApp is considered to be single image configuration with all 32 available eFuses dedicated to this one image.
+`bits_per_cnt` also defines a distribution of eFuse among images in system. For example, in the first case MCUBootApp is considered to be single image configuration with all 32 available eFuses dedicated to this one image.
-In second case MCUBootApp is considered to be multi-image configuration with 2 images. 24 bits of 32 available eFuses are dedicated to image id 1, and 8 bits to image id 2.
+In the second case MCUBootApp is considered to be multi-image configuration with 2 images. 24 bits of 32 available eFuses are dedicated to image id 1, and 8 bits to image id 2.
This distribution can be changed by user at initial provisioning stage and SHOULD NOT be changed at later reprovisioning stages.
-`"value": [2, 3]` filed sets corresponding value for image ids. Here `4` would be assigned to image id `1` and `5` to image id `2`.
+`"value": [2, 3]` field sets corresponding value for image ids. Here `2` would be assigned to image id `1` and `3` to image id `2`.
If the `nv_counter` value is increased in `policy/policy_secure.json` at the provisioning stage, the `nv_counter` value in `policy/policy_reprovisioning_secure.json` must start from the value not less than the value in `policy/policy_secure.json` file.
More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/edgeprotecttools/blob/master/docs/README_CYW20829.md#command-provision-device)
-When preparing an image for MCUBootApp with the rollback counter support, the `edgeprotecttools` signs it with `policy/policy_secure.json` in the post-build stage of `make`. The `nv_counter` value remains the same as one in the chip or sets higher. When `edgeprotecttools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (bit mask representation of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
+When preparing an image for MCUBootApp with the rollback counter support, the `edgeprotecttools` signs it with `policy/policy_secure.json` in the post-build stage of `make`. The `nv_counter` value remains the same as one in the chip or sets higher. When `edgeprotecttools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (bit mask representation of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the eFuse counter.
-If image counter value is set to higher then defined for this image by `bits_per_cnt` filed in policy, for example, image id 1 is provisioned to have 16 bits for its counter, but image programmed has nv counter value of 20 embedded in TLVs - MCUBootApp would discard it as invalid.
+If image counter value is set to higher than defined for this image by `bits_per_cnt` field in policy, for example, image id 1 is provisioned to have 16 bits for its counter, but image programmed has nv counter value of 20 embedded in TLVs - MCUBootApp would discard it as invalid.
### Building MCUBootApp and BlinkyApp with rollback protection
@@ -354,13 +354,13 @@
To update NV-counter for an appropriate image you have to increase NV-counter in the reprovisioning policy `/policy/policy_reprovisioning_secure.json`, after that re-build the `BlinkyApp` and re-program your device.
-The CYW20829/CYW89829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `edgeprotecttools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
+The CYW20829/CYW89829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of eFuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `edgeprotecttools` under `targets/cyw20829/packets/apps` or `targets/cyw89829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
-To enable the rollback counter feature, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot`.
+To enable the rollback counter feature, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot` or `boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot`.
-The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
+The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex` or `./MCUBootApp/out/CYW89829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
-When MCUBootApp detects that the rollback counter must be updated on CYW20829/CYW89829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM then detects the service app with its data, copies it to the corresponding addresses in RAM, and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
+When MCUBootApp detects that the rollback counter must be updated on CYW20829/CYW89829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signals BootROM to launch the service application and calls a system reset. BootROM then detects the service app with its data, copies it to the corresponding addresses in RAM, and executes it. Reprovisioning app then updates the `nv-counter` value in eFuse. An automatic reset can (and for convenience should) be initiated after that. To enable this flow, `sys_reset_req` is set to `true` (`false` by default).
"sys_reset_req": {
"description": "Resets a device after RAM application finishes execution.",
@@ -373,7 +373,7 @@
**Case 1**
-An image is singed using the `policy_reprovisioning_secure.json` policy with the `nv-counter` field value set to 1; the current value of NV-counter in the chip is `0` and programmed to the primary slot of MCUBootApp.
+An image is signed using the `policy_reprovisioning_secure.json` policy with the `nv-counter` field value set to 1; the current value of NV-counter in the chip is `0` and programmed to the primary slot of MCUBootApp.
MCUBootApp validates the image in the primary slot and initiates a rollback counter update. The image in the primary slot is started after that.
@@ -425,7 +425,7 @@
**Attention!** Don't omit `clean_boot` and `clean_upgrade` to avoid any issues!
### Programming applications
-The HEXes for device programming you can find:
+You can find the HEX files for programming at:
for MCUBootApp: `MCUBootApp.hex` in the directory 'MCUBootApp/out/CYW20829/*{BUILDCFG}*/'
@@ -433,7 +433,7 @@
- for IMG_ID=1, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**boot**/'
- for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**upgrade**/'
- for IMG_ID=2, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**boot**/'
- - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**upgrade**/'
+ - for IMG_ID=2, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**upgrade**/'
Default **{BUILDCFG}** is 'Debug', so all previous commands for the 'multi-image' case will build a 'Debug' configuration.
@@ -441,13 +441,13 @@
The following instruction assumes the usage of one of Cypress KitProg3 devices and a development board.
-Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` is steady on.
Open the terminal application and execute the following commands:
- export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
- $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x100000 psize 0x1000 esize 0x40000} }; set DEBUG_CERTIFICATE ./packets/debug_cert.bin" -f $OPENOCD_PATH/scripts/target/infineon/cyw20829.cfg -c "init; reset init; cmsis_flash init; program ./BlinkyApp/out/CYW20829/Release/upgrade/BlinkyApp.hex; shutdown"
+ $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x100000 psize 0x1000 esize 0x40000} }; set DEBUG_CERTIFICATE ./packets/debug_cert.bin" -f $OPENOCD_PATH/scripts/target/infineon/cyw20829.cfg -c "init; reset init; cmsis_flash init; program ./BlinkyApp/out/CYW20829/Debug/upgrade/BlinkyApp.hex; shutdown"
**Warning**
diff --git a/boot/cypress/platforms/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
index ac10910..07ba9a9 100644
--- a/boot/cypress/platforms/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -297,7 +297,7 @@
INCLUDE_DIRS += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
-INCLUDE_DIRS += $(PRJ_DIR)/libs/retarget-io
+INCLUDE_DIRS += $(PRJ_DIR)/libs/retarget-io/include
INCLUDE_DIRS += $(PRJ_DIR)/libs/mtb-hal-cat1/include
INCLUDE_DIRS += $(PRJ_DIR)/libs/mtb-hal-cat1/include_pvt
@@ -307,7 +307,6 @@
DEFINES += -DCY_USING_HAL
DEFINES += -DCOMPONENT_CM33
DEFINES += -DCOMPONENT_PSOC6HAL
-DEFINES += -DCOMPONENT_PSVP_CYW20829
DEFINES += -DCOMPONENT_SOFTFP
DEFINES += -DFLASH_BOOT
diff --git a/boot/cypress/platforms/PSOC6.md b/boot/cypress/platforms/PSOC6.md
index 6c9b7f7..167c4cf 100644
--- a/boot/cypress/platforms/PSOC6.md
+++ b/boot/cypress/platforms/PSOC6.md
@@ -89,11 +89,11 @@
Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.5\openocd` folder.
Open the terminal application and execute the following commands:
- export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.5/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/platforms/XMC7000.mk b/boot/cypress/platforms/XMC7000.mk
index 510841d..280bf76 100644
--- a/boot/cypress/platforms/XMC7000.mk
+++ b/boot/cypress/platforms/XMC7000.mk
@@ -233,6 +233,8 @@
INCLUDE_DIRS += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
INCLUDE_DIRS += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)
+C_FILES += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/cybsp.c
+
DEFINES += -DCY_USING_HAL
DEFINES += -DCOMPONENT_$(CORE)
DEFINES += -DCOMPONENT_$(CORE)_$(CORE_ID)
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_direct_xip_single.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_direct_xip_single.json
new file mode 100644
index 0000000..22791c5
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_direct_xip_single.json
@@ -0,0 +1,39 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "primary_slot": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "primary_slot_size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "secondary_slot": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "secondary_slot_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/utils/CYW20829/platform_utils.c b/boot/cypress/platforms/utils/CYW20829/platform_utils.c
index d6c7299..ffecb3d 100644
--- a/boot/cypress/platforms/utils/CYW20829/platform_utils.c
+++ b/boot/cypress/platforms/utils/CYW20829/platform_utils.c
@@ -309,6 +309,8 @@
uint32_t reset_handler = (uint32_t)&hang;
#ifdef MCUBOOT_ENC_IMAGES_XIP
+ uint32_t dword_counter = 0u;
+
if (key != NULL && iv != NULL) {
SMIF_Type *smif_device = qspi_get_device();
@@ -323,8 +325,10 @@
Cy_SMIF_SetMode(smif_device, CY_SMIF_MEMORY);
/* Clean up key and IV */
- (void)memset(key, 0, BOOTUTIL_CRYPTO_AES_CTR_KEY_SIZE);
- (void)memset(iv, 0, BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE);
+ for(dword_counter = 0; dword_counter < BOOTUTIL_CRYPTO_AES_CTR_KEY_SIZE / 4; dword_counter++)
+ ((volatile uint32_t *)key)[dword_counter] = 0u; // avoid memset compilator optimization
+ for(dword_counter = 0; dword_counter < BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE / 4; dword_counter++)
+ ((volatile uint32_t *)iv)[dword_counter] = 0u; // avoid memset compilator optimization
}
#else
(void)key;
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 39876fe..a68d992 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -26,10 +26,10 @@
include host.mk
# Compilers
-GCC_ARM := 1
-IAR := 2
-ARM := 3
-OTHER := 4
+GCC_ARM := 1
+IAR := 2
+ARM := 3
+OTHER := 4
ifeq ($(VERBOSE), 1)
$(info $(COMPILER))
@@ -39,7 +39,7 @@
# NOTE: Absolute pathes for now for the sake of development
ifeq ($(HOST_OS), win)
ifeq ($(COMPILER), GCC_ARM)
- TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/Infineon/Tools/mtb-gcc-arm-eabi/14.2.1/gcc
MY_TOOLCHAIN_PATH := $(call get_os_path, $(TOOLCHAIN_PATH))
TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
GCC_PATH := $(TOOLCHAIN_PATH)
@@ -49,14 +49,14 @@
endif
else ifeq ($(HOST_OS), osx)
- TOOLCHAIN_PATH ?= /Applications/mtb-gcc-arm-eabi/11.3.1/gcc
+ TOOLCHAIN_PATH ?= /Applications/mtb-gcc-arm-eabi/14.2.1/gcc
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
LD := $(CC)
else ifeq ($(HOST_OS), linux)
- TOOLCHAIN_PATH ?= /opt/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ TOOLCHAIN_PATH ?= /opt/Tools/mtb-gcc-arm-eabi/14.2.1/gcc
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
@@ -71,7 +71,7 @@
# Set flags for toolchain executables
ifeq ($(COMPILER), GCC_ARM)
# set build-in compiler flags
- CFLAGS_COMMON := -mthumb -ffunction-sections -fdata-sections -g -Wall -Wextra
+ CFLAGS_COMMON := -mthumb -ffunction-sections -fdata-sections -g -Wall -Wextra
CFLAGS_COMMON += -Wno-discarded-qualifiers -Wno-ignored-qualifiers # KILLME
ifeq ($(WARN_AS_ERR), 1)
@@ -82,7 +82,10 @@
CFLAGS_SPECIAL ?= -Og -g3 -ffile-prefix-map=$(CURDIR)=.
CFLAGS_COMMON += $(CFLAGS_SPECIAL)
else ifeq ($(BUILDCFG), Release)
- ifeq ($(CFLAGS_OPTIMIZATION), )
+ ifeq ($(FAMILY), XMC7000)
+ # XMC7000 Release mode size optimization workaround
+ CFLAGS_COMMON += -O1 -g -DNDEBUG
+ else ifeq ($(CFLAGS_OPTIMIZATION), )
# Blinky upgrade releas XIP WORKAROUND
CFLAGS_COMMON += -Os -g -DNDEBUG
endif
@@ -94,7 +97,12 @@
CC_DEPEND = -MD -MP -MF
- LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc -ffreestanding -fno-builtin-memset -fno-builtin-memcpy
+ LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc -ffreestanding -fno-builtin-memset -fno-builtin-memcpy
+
+ GCC_VERSION := $(shell $(CC) -dumpversion | cut -d. -f1)
+ ifeq ($(shell expr $(GCC_VERSION) \> 11), 1)
+ LDFLAGS += -Wl,--no-warn-rwx-segments
+ endif
ifeq ($(WARN_AS_ERR), 1)
LDFLAGS_COMMON += -Wl,--fatal-warnings