Add initial implementation of MCUBoot application for Cypress PSOC6 platform
Signed-off-by: Roman Okhrimenko <roman.okhrimenko@cypress.com>
diff --git a/boot/cypress/.gitignore b/boot/cypress/.gitignore
new file mode 100644
index 0000000..9a2c99f
--- /dev/null
+++ b/boot/cypress/.gitignore
@@ -0,0 +1,41 @@
+outdir/
+.*.swp
+target.sh
+*.pyc
+tags
+rusty-tags.*
+
+# mynewt
+/repos/
+/project.state
+/bin/
+/targets/
+**/build/**/*
+
+#Eclipse project files
+.cproject
+.project
+
+# Compiled python modules.
+*.pyc
+
+# Setuptools distribution folder.
+/scripts/dist/
+
+# Python egg metadata, regenerated from source files by setuptools.
+/scripts/*.egg-info
+/scripts/*.egg
+
+# Build dirs
+*out/*/*
+*out/obj/*
+
+# Build files
+*.o
+*.d
+*.map
+*.elf
+*.bin
+*.hex
+*.log
+*.lst
\ No newline at end of file
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
new file mode 100644
index 0000000..f22e1e6
--- /dev/null
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -0,0 +1,112 @@
+################################################################################
+# \file BlinkyApp.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe demo application BlinkyApp for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Cypress' MCUBoot Application supports GCC ARM only at this moment
+# Set defaults to:
+# - compiler GCC
+# - build configuration to Debug
+# - image type to BOOT
+COMPILER ?= GCC_ARM
+IMG_TYPE ?= BOOT
+
+# image type can be BOOT or UPGRADE
+IMG_TYPES = BOOT UPGRADE
+
+# CypressBootloader Image ID to use for signing, defualt is ID for multi image
+CYB_IMG_ID ?= 16
+
+ifneq ($(COMPILER), GCC_ARM)
+$(error Only GCC ARM is supported at this moment)
+endif
+
+CUR_APP_PATH = $(CURDIR)/$(APP_NAME)
+
+include $(CUR_APP_PATH)/platforms.mk
+include $(CUR_APP_PATH)/libs.mk
+include $(CUR_APP_PATH)/toolchains.mk
+
+# Application-specific DEFINES
+ifeq ($(IMG_TYPE), BOOT)
+ DEFINES_APP := -DBOOT_IMG
+else
+ DEFINES_APP := -DUPGRADE_IMG
+endif
+
+# Define start of application, RAM start and size, slot size
+ifeq ($(PLATFORM), PSOC_062_2M)
+ DEFINES_APP += -DRAM_START=0x08000000
+ DEFINES_APP += -DRAM_SIZE=0x20000
+ DEFINES_APP += -DUSER_APP_START=0x10018000
+ SLOT_SIZE ?= 0x10000
+endif
+
+# Collect Test Application sources
+SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
+# Collect all the sources
+SOURCES_APP += $(SOURCES_APP_SRC)
+
+# Collect includes for BlinkyApp
+INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
+
+# Overwite path to linker script if custom is required, otherwise default from BSP is used
+ifeq ($(COMPILER), GCC_ARM)
+LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/linker/$(APP_NAME).ld)
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+ASM_FILES_APP :=
+
+# We still need this for MCUBoot apps signing
+IMGTOOL_PATH ?= ../../scripts/imgtool.py
+
+SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -v "2.0" -S $(SLOT_SIZE) -M 512 --overwrite-only -R 0 -k keys/$(SIGN_KEY_FILE).pem
+
+# Output folder
+OUT := $(APP_NAME)/out
+# Output folder to contain build artifacts
+OUT_TARGET := $(OUT)/$(PLATFORM)
+
+OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
+
+# Set build directory for BOOT and UPGRADE images
+ifeq ($(IMG_TYPE), UPGRADE)
+ SIGN_ARGS += --pad
+ UPGRADE_SUFFIX :=_upgrade
+ OUT_CFG := $(OUT_CFG)/upgrade
+else
+ OUT_CFG := $(OUT_CFG)/boot
+endif
+
+pre_build:
+ $(info [PRE_BUILD] - Generating linker script for application $(CUR_APP_PATH)/linker/$(APP_NAME).ld)
+ @$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_template.ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
+
+# Post build action to execute after main build job
+post_build: $(OUT_CFG)/$(APP_NAME).hex
+ $(info [POST_BUILD] - Executing post build script for $(APP_NAME))
+ mv -f $(OUT_CFG)/$(APP_NAME).hex $(OUT_CFG)/$(APP_NAME)_unsigned.hex
+ $(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex
diff --git a/boot/cypress/BlinkyApp/Readme.md b/boot/cypress/BlinkyApp/Readme.md
new file mode 100644
index 0000000..2431481
--- /dev/null
+++ b/boot/cypress/BlinkyApp/Readme.md
@@ -0,0 +1,124 @@
+### Blinking LED test application for MCUBoot Bootloader.
+
+**Description:**
+
+Implements simple Blinky LED CM4 application to demonstrate MCUBoot Application and CypressBootloader operation in terms of BOOT and UPGRADE process.
+
+It is started by MCUBoot Application or CypressBootloader which is running on CM0p.
+
+Functionality:
+
+* Blinks RED led with 2 different rates, depending on type of image - BOOT or UPGRADE.
+* Prints debug info and version of itself to terminal at 115200 baud.
+* Can be built for BOOT slot or UPGRADE slot of bootloader.
+
+**Currently supported platforms:**
+
+* PSOC_062_2M
+
+**Pre-build action:**
+
+Pre-build action is implemented for defining start address and size of flash, as well as RAM start address and size for BlinkyApp.
+These values are set by specifing following macros: `-DUSER_APP_SIZE`, `-DUSER_APP_START`, `-DRAM_SIZE`, `-DRAM_START` in makefile.
+
+Pre-build action calls GCC preprocessor which intantiates defines for particular values in `BlinkyApp_template.ld`.
+
+Default values set for currently supported targets:
+* PSOC_062_2M in `BlinkyApp.mk` to `-DUSER_APP_START=0x10018000`
+
+**Building an application:**
+
+Root directory for build is **boot/cypress.**
+
+The following command will build regular HEX file of a BlinkyApp for BOOT slot:
+
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+
+This have following defaults suggested:
+
+ BUILDCFG=Debug
+ IMG_TYPE=BOOT
+
+To build UPGRADE image use following command:
+
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000
+
+ Note: HEADER_OFFSET=%SLOT_SIZE%
+
+Example command-line for single-image:
+
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+
+**Building Multi-Image**
+
+`BlinkyApp` can be built to use in multi-image bootloader configuration.
+
+To get appropriate artifacts to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
+
+Example usage:
+
+Considering default config:
+
+* first image BOOT (PRIMARY) slot start `0x10018000`
+* slot size `0x10000`
+* second image BOOT (PRIMARY) slot start `0x10038000`
+
+To get appropriate artifact for second image PRIMARY slot run this command:
+
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
+
+*Note:* only 2 images are supported at the moment.
+
+**Post-Build:**
+
+Post build action is executed at compile time for `BlinkyApp`. In case of build for `PSOC_062_2M` platform it calls `imgtool` from `MCUBoot` scripts and adds signature to compiled image.
+
+Flags passed to `imgtool` for signature are defined in `SIGN_ARGS` variable in BlinkyApp.mk.
+
+**How to program an application:**
+
+Use any preferred tool for programming hex files.
+
+Hex file names to use for programming:
+
+`BlinkyApp` always produce build artifacts in 2 separate folders - `boot` and `upgrade`.
+
+`BlinkyApp` built to run with `MCUBootApp` produces files with name BlinkyApp.hex in `boot` directory and `BlinkyApp_upgrade.hex` in `upgrade` folder. These files are ready to be flashed to the board.
+
+`BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
+
+Files to use for programming are:
+
+`BOOT` - boot/BlinkyApp.hex
+`UPGRADE` - upgrade/BlinkyApp_upgrade.hex
+
+**Flags:**
+- `BUILDCFG` - configuration **Release** or **Debug**
+- `MAKEINFO` - 0 (default) - less build info, 1 - verbose output of compilation.
+- `HEADER_OFFSET` - 0 (default) - no offset of output hex file, 0x%VALUE% - offset for output hex file. Value 0x10000 is slot size MCUBoot Bootloader in this example.
+- `IMG_TYPE` - `BOOT` (default) - build image for BOOT slot of MCUBoot Bootloader, `UPGRADE` - build image for UPGRADE slot of MCUBoot Bootloader.
+
+**NOTE**: In case of `UPGRADE` image `HEADER_OFFSET` should be set to MCUBoot Bootloader slot size.
+
+**Example terminal output:**
+
+When user application programmed in BOOT slot:
+
+ ===========================
+ [BlinkyApp] BlinkyApp v1.0 [CM4]
+ ===========================
+ [BlinkyApp] GPIO initialized
+ [BlinkyApp] UART initialized
+ [BlinkyApp] Retarget I/O set to 115200 baudrate
+ [BlinkyApp] Red led blinks with 1 sec period
+
+When user application programmed in UPRADE slot and upgrade procedure was successful:
+
+ ===========================
+ [BlinkyApp] BlinkyApp v2.0 [+]
+ ===========================
+
+ [BlinkyApp] GPIO initialized
+ [BlinkyApp] UART initialized
+ [BlinkyApp] Retarget I/O set to 115200 baudrate
+ [BlinkyApp] Red led blinks with 0.25 sec period
diff --git a/boot/cypress/BlinkyApp/libs.mk b/boot/cypress/BlinkyApp/libs.mk
new file mode 100644
index 0000000..0fbcf75
--- /dev/null
+++ b/boot/cypress/BlinkyApp/libs.mk
@@ -0,0 +1,89 @@
+################################################################################
+# \file libs.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe libraries needed for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+################################################################################
+# PDL library
+################################################################################
+PDL_VERSION = 121
+#
+CUR_LIBS_PATH = $(CURDIR)/libs
+
+# Collect source files for PDL
+SOURCES_PDL := $(wildcard $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/source/*.c)
+
+# Collect source files for Retarget-io
+SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
+
+# Collect source files for HAL
+SOURCES_HAL := $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/*.c)
+SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/triggers/*.c)
+SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/pin_packages/*.c)
+
+# PDL related include directories
+INCLUDE_DIRS_PDL := $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/include
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/devices/include/ip
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/devices/include
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/cmsis/include
+
+# Retarget-io related include directories
+INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
+
+# core-libs related include directories
+INCLUDE_DIRS_CORE_LIB := $(CUR_LIBS_PATH)/core-lib/include
+
+# Collect dirrectories containing headers for PSOC6 HAL
+INCLUDE_DIRS_HAL := $(CUR_LIBS_PATH)/psoc6hal/include
+INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
+INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
+INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/triggers
+
+# Collected source files for libraries
+SOURCES_LIBS := $(SOURCES_PDL)
+SOURCES_LIBS += $(SOURCES_PLATFORM)
+SOURCES_LIBS += $(SOURCES_RETARGET_IO)
+SOURCES_LIBS += $(SOURCES_HAL)
+
+# Collected include directories for libraries
+INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PLATFORM))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
+
+ASM_FILES_PDL :=
+ifeq ($(COMPILER), GCC_ARM)
+ASM_FILES_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+ASM_FILES_LIBS := $(ASM_FILES_PDL)
+ASM_FILES_LIBS += $(ASM_FILES_PLATFORM)
+
+# Add define for PDL version
+DEFINES_PDL += -DPDL_VERSION=$(PDL_VERSION)
+
+DEFINES_LIBS := $(DEFINES_PLATFORM)
+DEFINES_LIBS += $(DEFINES_PDL)
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
new file mode 100644
index 0000000..81fbc22
--- /dev/null
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
@@ -0,0 +1,425 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm4_dual.ld
+* \version 2.60
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include <main.h>
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* Size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+/* The size of the MCU boot header area at the start of FLASH */
+BOOT_HEADER_SIZE = 0x400;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+ */
+ ram (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE
+ flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ /* Cortex-M4 application flash area */
+ .text ORIGIN(flash) + BOOT_HEADER_SIZE :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK application.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
new file mode 100644
index 0000000..936511d
--- /dev/null
+++ b/boot/cypress/BlinkyApp/main.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#include "system_psoc6.h"
+#include "cy_pdl.h"
+#include "cyhal.h"
+#include "cy_retarget_io.h"
+
+/* Define pins for UART debug output */
+
+#define CY_DEBUG_UART_TX (P5_1)
+#define CY_DEBUG_UART_RX (P5_0)
+
+#if defined(PSOC_062_2M)
+#warning "Check if User LED is correct for your target board."
+#define LED_PORT GPIO_PRT13
+#define LED_PIN 7U
+#endif
+
+#define LED_NUM 5U
+#define LED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define LED_INIT_DRIVESTATE 1
+
+const cy_stc_gpio_pin_config_t LED_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = HSIOM_SEL_GPIO,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+#ifdef BOOT_IMG
+ #define BLINK_PERIOD (1000u)
+ #define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v1.0 [CM4]\r\n"
+ #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
+#elif UPGRADE_IMG
+ #define BLINK_PERIOD (250u)
+ #define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v2.0 [+]\r\n"
+ #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
+#else
+ #error "[BlinkyApp] Please specify type of image: -DBOOT_IMG or -DUPGRADE_IMG\r\n"
+#endif
+
+void check_result(int res)
+{
+ if (res != CY_RSLT_SUCCESS)
+ {
+ CY_ASSERT(0);
+ }
+}
+
+void test_app_init_hardware(void)
+{
+ /* enable interrupts */
+ __enable_irq();
+
+ /* Disabling watchdog so it will not interrupt normal flow later */
+ Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
+ /* Initialize retarget-io to use the debug UART port */
+ check_result(cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX,
+ CY_RETARGET_IO_BAUDRATE));
+
+ printf("\n===========================\r\n");
+ printf(GREETING_MESSAGE_VER);
+ printf("===========================\r\n");
+
+ printf("[BlinkyApp] GPIO initialized \r\n");
+ printf("[BlinkyApp] UART initialized \r\n");
+ printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
+
+}
+
+int main(void)
+{
+ uint32_t blinky_period = BLINK_PERIOD;
+
+ test_app_init_hardware();
+
+ printf(GREETING_MESSAGE_INFO);
+
+ for (;;)
+ {
+ /* Toggle the user LED periodically */
+ Cy_SysLib_Delay(blinky_period/2);
+
+ /* Invert the USER LED state */
+ Cy_GPIO_Inv(LED_PORT, LED_PIN);
+ }
+ return 0;
+}
diff --git a/boot/cypress/BlinkyApp/main.h b/boot/cypress/BlinkyApp/main.h
new file mode 100644
index 0000000..4fafb4e
--- /dev/null
+++ b/boot/cypress/BlinkyApp/main.h
@@ -0,0 +1,25 @@
+/*
+\copyright
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef USER_APP_START
+#define USER_APP_START 0x10000000
+#endif
+
+#ifndef USER_APP_SIZE
+#define USER_APP_SIZE 0x10000
+#endif
\ No newline at end of file
diff --git a/boot/cypress/BlinkyApp/platforms.mk b/boot/cypress/BlinkyApp/platforms.mk
new file mode 100644
index 0000000..2f4faf9
--- /dev/null
+++ b/boot/cypress/BlinkyApp/platforms.mk
@@ -0,0 +1,109 @@
+################################################################################
+# \file targets.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Target PLATFORM BlinkyApp is built for. PSOC_064_2M is set as default
+# Supported:
+# - PSOC_064_2M
+# - PSOC_064_1M
+# - PSOC_064_512K
+# - PSOC_062_2M
+
+# default TARGET
+PLATFORM ?= PSOC_064_2M
+#
+SB_PLATFORMS := PSOC_064_2M PSOC_064_1M PSOC_064_512K
+PLATFORMS := PSOC_062_2M $(SB_PLATFORMS)
+
+# For which core this application is built
+CORE := CM4
+
+# Set paths for related folders
+CUR_LIBS_PATH := $(CURDIR)/libs
+PLATFORMS_PATH := $(CURDIR)/platforms
+PLATFORM_PATH := $(PLATFORMS_PATH)/$(PLATFORM)
+
+# Target dependent definitions
+ifeq ($(PLATFORM), PSOC_064_2M)
+DEVICE ?= CYB0644ABZI-S2D44
+PLATFORM_SUFFIX := 02
+else ifeq ($(PLATFORM), PSOC_064_1M)
+DEVICE ?= CYB06447BZI-BLD53
+PLATFORM_SUFFIX := 01
+else ifeq ($(PLATFORM), PSOC_064_512K)
+DEVICE ?= CYB06445LQI-S3D42
+PLATFORM_SUFFIX := 03
+else ifeq ($(PLATFORM), PSOC_062_2M)
+DEVICE ?= CY8C624ABZI-D44
+PLATFORM_SUFFIX := 02
+endif
+
+# Check if path to cysecuretools is set in case Secure Boot target
+ifneq ($(filter $(PLATFORM), $(SB_PLATFORMS)),)
+ifeq ($(CY_SEC_TOOLS_PATH), )
+$(error Variable CY_SEC_TOOLS_PATH - path to cysecuretools package not set. \
+ Use `python -m pip show cysecuretools` to determine intallation folder.` \
+ Then set it in Makefile to continue work.)
+endif
+endif
+
+# Collect C source files for PLATFORM
+SOURCES_PLATFORM += $(wildcard $(PLATFORMS_PATH)/*.c)
+SOURCES_PLATFORM += $(wildcard $(PLATFORM_PATH)/$(CORE)/*.c)
+# Exclude system file for cm4
+SOURCES_PLATFORM := $(filter-out %/system_psoc6_cm0plus.c, $(SOURCES_PLATFORM))
+
+# Collect dirrectories containing headers for PLATFORM
+INCLUDE_DIRS_PLATFORM := $(PLATFORMS_PATH)
+INCLUDE_DIRS_PLATFORM += $(PLATFORM_PATH)/$(CORE)
+
+# Collect Assembler files for PLATFORM
+STARTUP_FILE := $(PLATFORM_PATH)/$(CORE)/$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_cm4
+
+ifeq ($(COMPILER), GCC_ARM)
+ ASM_FILES_PLATFORM := $(STARTUP_FILE).S
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+# Add device name from PLATFORM makefile to defines
+DEFINES += $(DEVICE)
+
+# Get defines from PLATFORM makefile and convert it to regular -DMY_NAME style
+ifneq ($(DEFINES),)
+ DEFINES_PLATFORM :=$(addprefix -D, $(subst -,_,$(DEFINES)))
+endif
+
+DEFINES_PLATFORM += $(addprefix -D, $(PLATFORM))
+
+ifneq ($(COMPILER), GCC_ARM)
+$(error Only GCC ARM is supported at this moment)
+endif
+ifeq ($(MAKEINFO) , 1)
+$(info ==============================================================================)
+$(info = PLATFORM files =)
+$(info ==============================================================================)
+$(info $(SOURCES_PLATFORM))
+$(info $(ASM_FILES_PLATFORM))
+endif
diff --git a/boot/cypress/BlinkyApp/toolchains.mk b/boot/cypress/BlinkyApp/toolchains.mk
new file mode 100644
index 0000000..3868436
--- /dev/null
+++ b/boot/cypress/BlinkyApp/toolchains.mk
@@ -0,0 +1,128 @@
+################################################################################
+# \file toolchains.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported toolchains for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Compilers
+GCC_ARM := 1
+IAR := 2
+ARM := 3
+OTHER := 4
+
+ifeq ($(MAKEINFO), 1)
+$(info $(COMPILER))
+endif
+# Detect host OS to make resolving compiler pathes easier
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S), Darwin)
+ HOST_OS = osx
+else
+ ifeq ($(UNAME_S), Linux)
+ HOST_OS = linux
+ else
+ HOST_OS = win
+ endif
+endif
+
+# Path to the compiler installation
+# NOTE: Absolute pathes for now for the sake of development
+ifeq ($(HOST_OS), win)
+ ifeq ($(COMPILER), GCC_ARM)
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox_1.0/tools/gcc-7.2.1-1.0
+ MY_TOOLCHAIN_PATH:=$(subst \,/,$(TOOLCHAIN_PATH))
+ TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
+ GCC_PATH := $(TOOLCHAIN_PATH)
+ # executables
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+
+ else ifeq ($(COMPILER), IAR)
+ IAR_PATH := C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0/arm
+ # executables
+ CC := "$(IAR_PATH)/bin/iccarm.exe"
+ AS := "$(IAR_PATH)/bin/iasmarm.exe"
+ LD := "$(IAR_PATH)/bin/ilinkarm.exe"
+ endif
+
+else ifeq ($(HOST_OS), osx)
+ TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
+ GCC_PATH := $(TOOLCHAIN_PATH)
+
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+
+else ifeq ($(HOST_OS), linux)
+ TOOLCHAIN_PATH ?= /usr/bin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc
+ GCC_PATH := $(TOOLCHAIN_PATH)
+ # executables
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+endif
+
+PDL_ELFTOOL := "hal/tools/$(HOST_OS)/elf/cymcuelftool"
+
+OBJDUMP := "$(GCC_PATH)/bin/arm-none-eabi-objdump"
+OBJCOPY := "$(GCC_PATH)/bin/arm-none-eabi-objcopy"
+
+# Set flags for toolchain executables
+ifeq ($(COMPILER), GCC_ARM)
+ # set build-in compiler flags
+ CFLAGS_COMMON := -mcpu=cortex-m4 -mthumb -mfloat-abi=soft -fno-stack-protector -ffunction-sections -fdata-sections -ffat-lto-objects -fstrict-aliasing -g -Wall -Wextra
+ ifeq ($(BUILDCFG), Debug)
+ CFLAGS_COMMON += -Og -g3
+ else ifeq ($(BUILDCFG), Release)
+ CFLAGS_COMMON += -Os -g
+ else
+ $(error BUILDCFG : '$(BUILDCFG)' is not supported)
+ endif
+ # add defines and includes
+ CFLAGS := $(CFLAGS_COMMON) $(INCLUDES)
+ CC_DEPEND = -MD -MP -MF
+
+ LDFLAGS_COMMON := -mcpu=cortex-m4 -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -L "$(GCC_PATH)/lib/gcc/arm-none-eabi/7.2.1/thumb/v6-m" -ffat-lto-objects -g --enable-objc-gc
+ ifeq ($(BUILDCFG), Debug)
+ LDFLAGS_COMMON += -Og
+ else ifeq ($(BUILDCFG), Release)
+ LDFLAGS_COMMON += -Os
+ else
+ $(error BUILDCFG : '$(BUILDCFG)' is not supported)
+ endif
+ LDFLAGS_NANO := -L "$(GCC_PATH)/arm-none-eabi/lib/thumb/v6-m"
+ LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO)
+
+else ifeq ($(COMPILER), IAR)
+
+ CFLAGS := --debug --endian=little --cpu=Cortex-M4 -e --fpu=None --dlib_config "$(IAR_PATH)\INC\c\DLib_Config_Normal.h"
+ CFLAGS += -Ohz --silent
+ CFLAGS += $(INCLUDES)
+ CC_DEPEND = --dependencies
+
+ AS_FLAGS := -s+ "-M<>" -w+ -r --cpu Cortex-M4 --fpu None -S
+
+ LINKER_SCRIPT := $(CHIP_SERIES).icf
+
+ #options to extend stack analize: --log call_graph --log_file $(OUT)/stack_usage_$(SUFFIX).txt
+ LDFLAGS_STACK_USAGE := --stack_usage_control $(STACK_CONTROL_FILE) --diag_suppress=Ls015 --diag_suppress=Ls016
+ LDFLAGS_COMMON := --vfe --text_out locale --silent --inline --merge_duplicate_sections
+ LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_STACK_USAGE) --config $(LINKER_SCRIPT) --map $(OUT_TARGET)/$(APP_NAME).map --entry Cy_FB_ResetHandler --no_exceptions
+endif
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.ld b/boot/cypress/MCUBootApp/MCUBootApp.ld
new file mode 100644
index 0000000..832017b
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp.ld
@@ -0,0 +1,408 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm0plus.ld
+* \version 2.60
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* Size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
+ */
+ ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x20000
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x18000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ /* Cortex-M0+ application flash area */
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - STACK_SIZE ;
+ PROVIDE(__stack = __StackTop);
+
+ .stackSpace (NOLOAD) : ALIGN(8)
+ {
+ . = . + STACK_SIZE ;
+ } > ram
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram);
+ __HeapLimit = .;
+ } > ram
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
new file mode 100644
index 0000000..0411eae
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -0,0 +1,83 @@
+################################################################################
+# \file targets.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Cypress' MCUBoot Application supports GCC ARM only at this moment
+# Set default compiler to GCC if not specified from command line
+COMPILER ?= GCC_ARM
+
+MCUBOOT_IMAGE_NUMBER ?= 1
+
+ifneq ($(COMPILER), GCC_ARM)
+$(error Only GCC ARM is supported at this moment)
+endif
+
+CUR_APP_PATH = $(CURDIR)/$(APP_NAME)
+
+include $(CUR_APP_PATH)/platforms.mk
+include $(CUR_APP_PATH)/libs.mk
+include $(CUR_APP_PATH)/toolchains.mk
+
+# Application-specific DEFINES
+DEFINES_APP := -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
+DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
+DEFINES_APP += -DCORE=$(CORE)
+DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
+
+# Collect MCUBoot sourses
+SOURCES_MCUBOOT := $(wildcard $(CURDIR)/../bootutil/src/*.c)
+# Collect MCUBoot Application sources
+SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
+# Collect Flash Layer port sources
+SOURCES_FLASH_PORT := $(wildcard $(CURDIR)/cy_flash_pal/*.c)
+# Collect all the sources
+SOURCES_APP := $(SOURCES_MCUBOOT)
+SOURCES_APP += $(SOURCES_APP_SRC)
+SOURCES_APP += $(SOURCES_FLASH_PORT)
+
+INCLUDES_DIRS_MCUBOOT := $(addprefix -I, $(CURDIR)/../bootutil/include)
+INCLUDES_DIRS_MCUBOOT += $(addprefix -I, $(CURDIR)/../bootutil/src)
+
+INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include)
+INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include/flash_map_backend)
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/config)
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/os)
+
+ASM_FILES_APP :=
+
+# Output folder
+OUT := $(APP_NAME)/out
+# Output folder to contain build artifacts
+OUT_TARGET := $(OUT)/$(PLATFORM)
+
+OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
+
+# Overwite path to linker script if custom is required, otherwise default from BSP is used
+ifeq ($(COMPILER), GCC_ARM)
+LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/$(APP_NAME).ld)
+else
+$(error Only GCC ARM is supported at this moment)
+endif
\ No newline at end of file
diff --git a/boot/cypress/MCUBootApp/README.md b/boot/cypress/MCUBootApp/README.md
new file mode 100644
index 0000000..dfa8312
--- /dev/null
+++ b/boot/cypress/MCUBootApp/README.md
@@ -0,0 +1,147 @@
+### Port of MCUBoot library to be used with Cypress targets
+
+**Solution Description**
+
+Given solution demonstrates operation of MCUBoot on Cypress' PSoC6 device.
+
+There are two applications implemented:
+* MCUBootApp - PSoC6 MCUBoot-based bootloading application;
+* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
+
+The demonstration device is CY8CPROTO-062-4343W board which is PSoC6 device with 2M of Flash available.
+
+The default flash map implemented is the following:
+
+* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
+* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
+* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
+* [0x10038000, 0x10039000] - scratch area;
+
+Size of slots `0x10000` - 64kb
+
+**Important**: make sure primary, secondary slot and bootloader app sizes are appropriate and correspond to flash area size defined in Applications' linker files.
+
+MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses completely SW implementation of cryptographic functions based on mbedTLS Library.
+
+**How to modify Flash map:**
+
+__Option 1.__
+
+Navigate to `sysflash.h` and modify the flash area(s) / slots sizes to meet your needs.
+
+__Option 2.__
+
+Navigate to `sysflash.h`, uncomment `CY_FLASH_MAP_EXT_DESC` definition.
+Now define and initialize `struct flash_area *boot_area_descs[]` with flash memory addresses and sizes you need at the beginning of application, so flash APIs from `cy_flash_map.c` will use it.
+
+__Note:__ for both options make sure you have updated `MCUBOOT_MAX_IMG_SECTORS` appropriatery with sector size assumed to be 512.
+
+**How to override the flash map values during build process:**
+
+Navigate to MCUBootApp.mk, find section `DEFINES_APP +=`
+Update this line and or add similar for flash map parameters to override.
+
+The possible list could be:
+
+* MCUBOOT_MAX_IMG_SECTORS
+* CY_FLASH_MAP_EXT_DESC
+* CY_BOOT_SCRATCH_SIZE
+* CY_BOOT_BOOTLOADER_SIZE
+* CY_BOOT_PRIMARY_1_SIZE
+* CY_BOOT_SECONDARY_1_SIZE
+* CY_BOOT_PRIMARY_2_SIZE
+* CY_BOOT_SECONDARY_2_SIZE
+
+As an example in a makefile it should look like following:
+
+`DEFINES_APP +=-DCY_FLASH_MAP_EXT_DESC`
+
+`DEFINES_APP +=-DMCUBOOT_MAX_IMG_SECTORS=512`
+
+`DEFINES_APP +=-DCY_BOOT_PRIMARY_1_SIZE=0x15000`
+
+**Multi-Image Operation**
+
+Multi-image operation considers upgrading and verification of more then one image on the device.
+
+To enable multi-image operation define `MCUBOOT_IMAGE_NUMBER` in `MCUBootApp/mcuboot_config.h` file should be set to 2 (only dual-image is supported at the moment). This could also be done on build time by passing `MCUBOOT_IMAGE_NUMBER=2` as parameter to `make`.
+
+Default value of `MCUBOOT_IMAGE_NUMBER` is 1, which corresponds to single image configuratios.
+
+In multi-image operation (two images are considered for simplicity) MCUBoot Bootloader application operates as following:
+
+* Verifies Primary_1 and Primary_2 images;
+* Verifies Secondary_1 and Secondary_2 images;
+* Upgrades Secondary to Primary if valid images found;
+* Boots image from Primary_1 slot only;
+* Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid;
+
+This ensures two dependent applications can be accepted by device only in case both images are valid.
+
+**Default Flash map for Multi-Image operation:**
+
+`0x10000000 - 0x10018000` - MCUBoot Bootloader
+
+`0x10018000 - 0x10028000` - Primary_1 (BOOT) slot of Bootloader
+
+`0x10028000 - 0x10038000` - Secondary_1 (UPGRADE) slot of Bootloader
+
+`0x10038000 - 0x10048000` - Primary_2 (BOOT) slot of Bootloader
+
+`0x10048000 - 0x10058000` - Secondary_2 (UPGRADE) slot of Bootloader
+
+`0x10058000 - 0x10058100` - Scratch of Bootloader
+
+Size of slots `0x10000` - 64kb
+
+**Downloading Solution's Assets**
+
+There is a set assets required:
+
+* MCUBooot Library (root repository)
+* PSoC6 HAL Library
+* PSoC6 Peripheral Drivers Library (PDL)
+* mbedTLS Cryptographic Library
+
+To get submodules - run the following command:
+
+ git submodule update --init --recursive
+
+**Building Solution**
+
+This folder contains make files infrastructure for building MCUBoot Bootloader. Same approach used in sample BlinkyLedApp application. Example command are provided below for couple different build configurations.
+
+* Build MCUBootApp in `Debug` for signle image use case.
+
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1
+
+* Build MCUBootApp in `Release` for multi image use case.
+
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release MCUBOOT_IMAGE_NUMBER=2
+
+Root directory for build is **boot/cypress.**
+
+**Currently supported platforms:**
+
+* PSOC_062_2M
+
+**Build environment troubleshooting:**
+
+Regular shell/terminal combination on Linux and MacOS.
+
+On Windows:
+
+* Cygwin
+* Msys2
+
+Also IDE may be used:
+* Eclipse / ModusToolbox ("makefile project from existing source")
+
+*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
+
+*Python/Python3* - make sure you have correct path referenced in `PATH`;
+
+*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
+
+This will iherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h
new file mode 100644
index 0000000..5c07711
--- /dev/null
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h
@@ -0,0 +1,22 @@
+/*
+ * mcuboot_assert.h
+ *
+ * Cypress-specific assert() macro redefinition
+ *
+ */
+
+#ifndef MCUBOOT_ASSERT_H
+#define MCUBOOT_ASSERT_H
+
+//#include "cy_bootloader_services.h"
+
+#define CYBL_ASSERT(...) Cy_BLServ_Assert(__VA_ARGS__)
+
+#if !defined(NDEBUG)
+#undef assert
+#define assert(...) CYBL_ASSERT(__VA_ARGS__)
+#else
+#define assert
+#endif
+
+#endif /* MCUBOOT_ASSERT_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
new file mode 100644
index 0000000..eb539a5
--- /dev/null
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
@@ -0,0 +1,148 @@
+/* Copyright 2019 Cypress Semiconductor Corporation
+ *
+ * Copyright (c) 2018 Open Source Foundries Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef MCUBOOT_CONFIG_H
+#define MCUBOOT_CONFIG_H
+
+/*
+ * Template configuration file for MCUboot.
+ *
+ * When porting MCUboot to a new target, copy it somewhere that your
+ * include path can find it as mcuboot_config/mcuboot_config.h, and
+ * make adjustments to suit your platform.
+ *
+ * For examples, see:
+ *
+ * boot/zephyr/include/mcuboot_config/mcuboot_config.h
+ * boot/mynewt/mcuboot_config/include/mcuboot_config/mcuboot_config.h
+ */
+/* Default maximum number of flash sectors per image slot; change
+ * as desirable. */
+#ifndef MCUBOOT_MAX_IMG_SECTORS
+#define MCUBOOT_MAX_IMG_SECTORS 2560
+#endif
+
+/*
+ * Signature types
+ *
+ * You must choose exactly one signature type.
+ */
+
+/* Uncomment for RSA signature support */
+//#define MCUBOOT_SIGN_RSA
+
+/* Uncomment for ECDSA signatures using curve P-256. */
+#define MCUBOOT_SIGN_EC256
+#define NUM_ECC_BYTES (256 / 8) // P-256 curve size in bytes, rnok: to make compilable
+
+// #define MCUBOOT_SIGN_EC
+
+/*
+ * Upgrade mode
+ *
+ * The default is to support A/B image swapping with rollback. A
+ * simpler code path, which only supports overwriting the
+ * existing image with the update image, is also available.
+ */
+
+/* Uncomment to enable the overwrite-only code path. */
+#define MCUBOOT_OVERWRITE_ONLY
+
+#ifdef MCUBOOT_OVERWRITE_ONLY
+/* Uncomment to only erase and overwrite those slot 0 sectors needed
+ * to install the new image, rather than the entire image slot. */
+/* #define MCUBOOT_OVERWRITE_ONLY_FAST */
+#endif
+
+/*
+ * Cryptographic settings
+ *
+ * You must choose between mbedTLS and Tinycrypt as source of
+ * cryptographic primitives. Other cryptographic settings are also
+ * available.
+ */
+
+/* Uncomment to use ARM's mbedTLS cryptographic primitives */
+#define MCUBOOT_USE_MBED_TLS
+/* Uncomment to use Tinycrypt's. */
+/* #define MCUBOOT_USE_TINYCRYPT */
+
+/*
+ * Always check the signature of the image in slot 0 before booting,
+ * even if no upgrade was performed. This is recommended if the boot
+ * time penalty is acceptable.
+ */
+#define MCUBOOT_VALIDATE_PRIMARY_SLOT
+
+/*
+ * Flash abstraction
+ */
+
+/* Uncomment if your flash map API supports flash_area_get_sectors().
+ * See the flash APIs for more details. */
+// TODO: FWSECURITY-755
+#define MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+
+/* Default number of separately updateable images; change in case of
+ * multiple images. */
+#ifndef MCUBOOT_IMAGE_NUMBER
+#define MCUBOOT_IMAGE_NUMBER 1
+#endif
+
+/*
+ * Logging
+ */
+
+/*
+ * If logging is enabled the following functions must be defined by the
+ * platform:
+ *
+ * MCUBOOT_LOG_ERR(...)
+ * MCUBOOT_LOG_WRN(...)
+ * MCUBOOT_LOG_INF(...)
+ * MCUBOOT_LOG_DBG(...)
+ *
+ * The following global logging level configuration macros must also be
+ * defined, each with a unique value. Those will be used to define a global
+ * configuration and will allow any source files to override the global
+ * configuration:
+ *
+ * MCUBOOT_LOG_LEVEL_OFF
+ * MCUBOOT_LOG_LEVEL_ERROR
+ * MCUBOOT_LOG_LEVEL_WARNING
+ * MCUBOOT_LOG_LEVEL_INFO
+ * MCUBOOT_LOG_LEVEL_DEBUG
+ *
+ * The global logging level must be defined, with one of the previously defined
+ * logging levels:
+ *
+ * #define MCUBOOT_LOG_LEVEL MCUBOOT_LOG_LEVEL_(OFF|ERROR|WARNING|INFO|DEBUG)
+ *
+ * MCUBOOT_LOG_LEVEL sets the minimum level that will be logged. The function
+ * priority is:
+ *
+ * MCUBOOT_LOG_ERR > MCUBOOT_LOG_WRN > MCUBOOT_LOG_INF > MCUBOOT_LOG_DBG
+ *
+ * NOTE: Each source file is still able to request its own logging level by
+ * defining BOOT_LOG_LEVEL before #including `bootutil_log.h`
+ */
+#define MCUBOOT_HAVE_LOGGING 1
+
+/*
+ * Assertions
+ */
+
+/* Uncomment if your platform has its own mcuboot_config/mcuboot_assert.h.
+ * If so, it must provide an ASSERT macro for use by bootutil. Otherwise,
+ * "assert" is used. */
+//#define MCUBOOT_HAVE_ASSERT_H
+
+#define MCUBOOT_WATCHDOG_FEED() \
+ do { \
+ /* TODO: to be implemented */ \
+ } while (0)
+
+#endif /* MCUBOOT_CONFIG_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
new file mode 100644
index 0000000..3a8eafe
--- /dev/null
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifndef MCUBOOT_LOGGING_H
+#define MCUBOOT_LOGGING_H
+
+#include <stdio.h>
+
+#define MCUBOOT_LOG_LEVEL_OFF 0
+#define MCUBOOT_LOG_LEVEL_ERROR 1
+#define MCUBOOT_LOG_LEVEL_WARNING 2
+#define MCUBOOT_LOG_LEVEL_INFO 3
+#define MCUBOOT_LOG_LEVEL_DEBUG 4
+
+/*
+ * The compiled log level determines the maximum level that can be
+ * printed. Messages at or below this level can be printed, provided
+ * they are also enabled through the Rust logging system, such as by
+ * setting RUST_LOG to bootsim::api=info.
+ */
+#ifndef MCUBOOT_LOG_LEVEL
+#define MCUBOOT_LOG_LEVEL MCUBOOT_LOG_LEVEL_INFO
+#endif
+
+int sim_log_enabled(int level);
+
+#define sim_log_enabled(x) 1
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_ERROR
+#define MCUBOOT_LOG_ERR(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR)) { \
+ fprintf(stderr, "[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
+ } while (0)
+#else
+#define MCUBOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_WARNING
+#define MCUBOOT_LOG_WRN(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING)) { \
+ fprintf(stderr, "[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
+ } while (0)
+#else
+#define MCUBOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_INFO
+#define MCUBOOT_LOG_INF(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO)) { \
+ fprintf(stderr, "[INF] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
+ } while (0)
+#else
+#define MCUBOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
+#define MCUBOOT_LOG_DBG(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG)) { \
+ fprintf(stderr, "[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
+ } while (0)
+#else
+#define MCUBOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
+#endif
+
+#endif /* MCUBOOT_LOGGING_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
new file mode 100644
index 0000000..6bc5145
--- /dev/null
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
@@ -0,0 +1,3601 @@
+/**
+ * \file config.h
+ *
+ * \brief Configuration options (set of defines)
+ *
+ * This set of compile-time options may be used to enable
+ * or disable features selectively, and reduce the global
+ * memory footprint.
+ */
+/*
+ * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
+#define _CRT_SECURE_NO_DEPRECATE 1
+#endif
+
+/**
+ * \name SECTION: System support
+ *
+ * This section sets system specific settings.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_HAVE_ASM
+ *
+ * The compiler has support for asm().
+ *
+ * Requires support for asm() in compiler.
+ *
+ * Used in:
+ * library/aria.c
+ * library/timing.c
+ * include/mbedtls/bn_mul.h
+ *
+ * Required by:
+ * MBEDTLS_AESNI_C
+ * MBEDTLS_PADLOCK_C
+ *
+ * Comment to disable the use of assembly code.
+ */
+#define MBEDTLS_HAVE_ASM
+
+/**
+ * \def MBEDTLS_NO_UDBL_DIVISION
+ *
+ * The platform lacks support for double-width integer division (64-bit
+ * division on a 32-bit platform, 128-bit division on a 64-bit platform).
+ *
+ * Used in:
+ * include/mbedtls/bignum.h
+ * library/bignum.c
+ *
+ * The bignum code uses double-width division to speed up some operations.
+ * Double-width division is often implemented in software that needs to
+ * be linked with the program. The presence of a double-width integer
+ * type is usually detected automatically through preprocessor macros,
+ * but the automatic detection cannot know whether the code needs to
+ * and can be linked with an implementation of division for that type.
+ * By default division is assumed to be usable if the type is present.
+ * Uncomment this option to prevent the use of double-width division.
+ *
+ * Note that division for the native integer type is always required.
+ * Furthermore, a 64-bit type is always required even on a 32-bit
+ * platform, but it need not support multiplication or division. In some
+ * cases it is also desirable to disable some double-width operations. For
+ * example, if double-width division is implemented in software, disabling
+ * it can reduce code size in some embedded targets.
+ */
+//#define MBEDTLS_NO_UDBL_DIVISION
+
+/**
+ * \def MBEDTLS_NO_64BIT_MULTIPLICATION
+ *
+ * The platform lacks support for 32x32 -> 64-bit multiplication.
+ *
+ * Used in:
+ * library/poly1305.c
+ *
+ * Some parts of the library may use multiplication of two unsigned 32-bit
+ * operands with a 64-bit result in order to speed up computations. On some
+ * platforms, this is not available in hardware and has to be implemented in
+ * software, usually in a library provided by the toolchain.
+ *
+ * Sometimes it is not desirable to have to link to that library. This option
+ * removes the dependency of that library on platforms that lack a hardware
+ * 64-bit multiplier by embedding a software implementation in Mbed TLS.
+ *
+ * Note that depending on the compiler, this may decrease performance compared
+ * to using the library function provided by the toolchain.
+ */
+//#define MBEDTLS_NO_64BIT_MULTIPLICATION
+
+/**
+ * \def MBEDTLS_HAVE_SSE2
+ *
+ * CPU supports SSE2 instruction set.
+ *
+ * Uncomment if the CPU supports SSE2 (IA-32 specific).
+ */
+//#define MBEDTLS_HAVE_SSE2
+
+/**
+ * \def MBEDTLS_HAVE_TIME
+ *
+ * System has time.h and time().
+ * The time does not need to be correct, only time differences are used,
+ * by contrast with MBEDTLS_HAVE_TIME_DATE
+ *
+ * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT,
+ * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and
+ * MBEDTLS_PLATFORM_STD_TIME.
+ *
+ * Comment if your system does not support time functions
+ */
+#define MBEDTLS_HAVE_TIME
+
+/**
+ * \def MBEDTLS_HAVE_TIME_DATE
+ *
+ * System has time.h, time(), and an implementation for
+ * mbedtls_platform_gmtime_r() (see below).
+ * The time needs to be correct (not necessarily very accurate, but at least
+ * the date should be correct). This is used to verify the validity period of
+ * X.509 certificates.
+ *
+ * Comment if your system does not have a correct clock.
+ *
+ * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that
+ * behaves similarly to the gmtime_r() function from the C standard. Refer to
+ * the documentation for mbedtls_platform_gmtime_r() for more information.
+ *
+ * \note It is possible to configure an implementation for
+ * mbedtls_platform_gmtime_r() at compile-time by using the macro
+ * MBEDTLS_PLATFORM_GMTIME_R_ALT.
+ */
+#define MBEDTLS_HAVE_TIME_DATE
+
+/**
+ * \def MBEDTLS_PLATFORM_MEMORY
+ *
+ * Enable the memory allocation layer.
+ *
+ * By default mbed TLS uses the system-provided calloc() and free().
+ * This allows different allocators (self-implemented or provided) to be
+ * provided to the platform abstraction layer.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY without the
+ * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
+ * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
+ * free() function pointer at runtime.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
+ * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
+ * alternate function at compile time.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Enable this layer to allow use of alternative memory allocators.
+ */
+//#define MBEDTLS_PLATFORM_MEMORY
+
+/**
+ * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+ *
+ * Do not assign standard functions in the platform layer (e.g. calloc() to
+ * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
+ *
+ * This makes sure there are no linking errors on platforms that do not support
+ * these functions. You will HAVE to provide alternatives, either at runtime
+ * via the platform_set_xxx() functions or at compile time by setting
+ * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
+ * MBEDTLS_PLATFORM_XXX_MACRO.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Uncomment to prevent default assignment of standard functions in the
+ * platform layer.
+ */
+//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+/**
+ * \def MBEDTLS_PLATFORM_EXIT_ALT
+ *
+ * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
+ * function in the platform abstraction layer.
+ *
+ * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
+ * provide a function "mbedtls_platform_set_printf()" that allows you to set an
+ * alternative printf function pointer.
+ *
+ * All these define require MBEDTLS_PLATFORM_C to be defined!
+ *
+ * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
+ * it will be enabled automatically by check_config.h
+ *
+ * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
+ * MBEDTLS_PLATFORM_XXX_MACRO!
+ *
+ * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME
+ *
+ * Uncomment a macro to enable alternate implementation of specific base
+ * platform function
+ */
+//#define MBEDTLS_PLATFORM_EXIT_ALT
+//#define MBEDTLS_PLATFORM_TIME_ALT
+//#define MBEDTLS_PLATFORM_FPRINTF_ALT
+//#define MBEDTLS_PLATFORM_PRINTF_ALT
+//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+//#define MBEDTLS_PLATFORM_VSNPRINTF_ALT
+//#define MBEDTLS_PLATFORM_NV_SEED_ALT
+//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT
+
+/**
+ * \def MBEDTLS_DEPRECATED_WARNING
+ *
+ * Mark deprecated functions so that they generate a warning if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * This only works with GCC and Clang. With other compilers, you may want to
+ * use MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Uncomment to get warnings on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_WARNING
+
+/**
+ * \def MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Remove deprecated functions so that they generate an error if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * Uncomment to get errors on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_REMOVED
+
+/**
+ * \def MBEDTLS_CHECK_PARAMS
+ *
+ * This configuration option controls whether the library validates more of
+ * the parameters passed to it.
+ *
+ * When this flag is not defined, the library only attempts to validate an
+ * input parameter if: (1) they may come from the outside world (such as the
+ * network, the filesystem, etc.) or (2) not validating them could result in
+ * internal memory errors such as overflowing a buffer controlled by the
+ * library. On the other hand, it doesn't attempt to validate parameters whose
+ * values are fully controlled by the application (such as pointers).
+ *
+ * When this flag is defined, the library additionally attempts to validate
+ * parameters that are fully controlled by the application, and should always
+ * be valid if the application code is fully correct and trusted.
+ *
+ * For example, when a function accepts as input a pointer to a buffer that may
+ * contain untrusted data, and its documentation mentions that this pointer
+ * must not be NULL:
+ * - The pointer is checked to be non-NULL only if this option is enabled.
+ * - The content of the buffer is always validated.
+ *
+ * When this flag is defined, if a library function receives a parameter that
+ * is invalid:
+ * 1. The function will invoke the macro MBEDTLS_PARAM_FAILED().
+ * 2. If MBEDTLS_PARAM_FAILED() did not terminate the program, the function
+ * will immediately return. If the function returns an Mbed TLS error code,
+ * the error code in this case is MBEDTLS_ERR_xxx_BAD_INPUT_DATA.
+ *
+ * When defining this flag, you also need to arrange a definition for
+ * MBEDTLS_PARAM_FAILED(). You can do this by any of the following methods:
+ * - By default, the library defines MBEDTLS_PARAM_FAILED() to call a
+ * function mbedtls_param_failed(), but the library does not define this
+ * function. If you do not make any other arrangements, you must provide
+ * the function mbedtls_param_failed() in your application.
+ * See `platform_util.h` for its prototype.
+ * - If you enable the macro #MBEDTLS_CHECK_PARAMS_ASSERT, then the
+ * library defines MBEDTLS_PARAM_FAILED(\c cond) to be `assert(cond)`.
+ * You can still supply an alternative definition of
+ * MBEDTLS_PARAM_FAILED(), which may call `assert`.
+ * - If you define a macro MBEDTLS_PARAM_FAILED() before including `config.h`
+ * or you uncomment the definition of MBEDTLS_PARAM_FAILED() in `config.h`,
+ * the library will call the macro that you defined and will not supply
+ * its own version. Note that if MBEDTLS_PARAM_FAILED() calls `assert`,
+ * you need to enable #MBEDTLS_CHECK_PARAMS_ASSERT so that library source
+ * files include `<assert.h>`.
+ *
+ * Uncomment to enable validation of application-controlled parameters.
+ */
+//#define MBEDTLS_CHECK_PARAMS
+
+/**
+ * \def MBEDTLS_CHECK_PARAMS_ASSERT
+ *
+ * Allow MBEDTLS_PARAM_FAILED() to call `assert`, and make it default to
+ * `assert`. This macro is only used if #MBEDTLS_CHECK_PARAMS is defined.
+ *
+ * If this macro is not defined, then MBEDTLS_PARAM_FAILED() defaults to
+ * calling a function mbedtls_param_failed(). See the documentation of
+ * #MBEDTLS_CHECK_PARAMS for details.
+ *
+ * Uncomment to allow MBEDTLS_PARAM_FAILED() to call `assert`.
+ */
+//#define MBEDTLS_CHECK_PARAMS_ASSERT
+
+/* \} name SECTION: System support */
+
+/**
+ * \name SECTION: mbed TLS feature support
+ *
+ * This section sets support for features that are or are not needed
+ * within the modules that are enabled.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_TIMING_ALT
+ *
+ * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
+ * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
+ *
+ * Only works if you have MBEDTLS_TIMING_C enabled.
+ *
+ * You will need to provide a header "timing_alt.h" and an implementation at
+ * compile time.
+ */
+//#define MBEDTLS_TIMING_ALT
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternate core implementation of a symmetric crypto, an arithmetic or hash
+ * module (e.g. platform specific assembly optimized implementations). Keep
+ * in mind that the function prototypes should remain the same.
+ *
+ * This replaces the whole module. If you only want to replace one of the
+ * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
+ * provide the "struct mbedtls_aes_context" definition and omit the base
+ * function declarations and implementations. "aes_alt.h" will be included from
+ * "aes.h" to include the new function definitions.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * module.
+ *
+ * \warning MD2, MD4, MD5, ARC4, DES and SHA-1 are considered weak and their
+ * use constitutes a security risk. If possible, we recommend
+ * avoiding dependencies on them, and considering stronger message
+ * digests and ciphers instead.
+ *
+ */
+//#define MBEDTLS_AES_ALT
+//#define MBEDTLS_ARC4_ALT
+//#define MBEDTLS_ARIA_ALT
+//#define MBEDTLS_BLOWFISH_ALT
+//#define MBEDTLS_CAMELLIA_ALT
+//#define MBEDTLS_CCM_ALT
+//#define MBEDTLS_CHACHA20_ALT
+//#define MBEDTLS_CHACHAPOLY_ALT
+//#define MBEDTLS_CMAC_ALT
+//#define MBEDTLS_DES_ALT
+//#define MBEDTLS_DHM_ALT
+//#define MBEDTLS_ECJPAKE_ALT
+//#define MBEDTLS_GCM_ALT
+//#define MBEDTLS_NIST_KW_ALT
+//#define MBEDTLS_MD2_ALT
+//#define MBEDTLS_MD4_ALT
+//#define MBEDTLS_MD5_ALT
+//#define MBEDTLS_POLY1305_ALT
+//#define MBEDTLS_RIPEMD160_ALT
+//#define MBEDTLS_RSA_ALT
+//#define MBEDTLS_SHA1_ALT
+//#define MBEDTLS_SHA256_ALT
+//#define MBEDTLS_SHA512_ALT
+//#define MBEDTLS_XTEA_ALT
+
+/*
+ * When replacing the elliptic curve module, pleace consider, that it is
+ * implemented with two .c files:
+ * - ecp.c
+ * - ecp_curves.c
+ * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT
+ * macros as described above. The only difference is that you have to make sure
+ * that you provide functionality for both .c files.
+ */
+//#define MBEDTLS_ECP_ALT
+
+/**
+ * \def MBEDTLS_MD2_PROCESS_ALT
+ *
+ * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
+ * alternate core implementation of symmetric crypto or hash function. Keep in
+ * mind that function prototypes should remain the same.
+ *
+ * This replaces only one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
+ * no longer provide the mbedtls_sha1_process() function, but it will still provide
+ * the other function (using your mbedtls_sha1_process() function) and the definition
+ * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
+ * with this definition.
+ *
+ * \note Because of a signature change, the core AES encryption and decryption routines are
+ * currently named mbedtls_aes_internal_encrypt and mbedtls_aes_internal_decrypt,
+ * respectively. When setting up alternative implementations, these functions should
+ * be overridden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt
+ * must stay untouched.
+ *
+ * \note If you use the AES_xxx_ALT macros, then is is recommended to also set
+ * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
+ * tables.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ *
+ * \warning MD2, MD4, MD5, DES and SHA-1 are considered weak and their use
+ * constitutes a security risk. If possible, we recommend avoiding
+ * dependencies on them, and considering stronger message digests
+ * and ciphers instead.
+ *
+ */
+//#define MBEDTLS_MD2_PROCESS_ALT
+//#define MBEDTLS_MD4_PROCESS_ALT
+//#define MBEDTLS_MD5_PROCESS_ALT
+//#define MBEDTLS_RIPEMD160_PROCESS_ALT
+//#define MBEDTLS_SHA1_PROCESS_ALT
+//#define MBEDTLS_SHA256_PROCESS_ALT
+//#define MBEDTLS_SHA512_PROCESS_ALT
+//#define MBEDTLS_DES_SETKEY_ALT
+//#define MBEDTLS_DES_CRYPT_ECB_ALT
+//#define MBEDTLS_DES3_CRYPT_ECB_ALT
+//#define MBEDTLS_AES_SETKEY_ENC_ALT
+//#define MBEDTLS_AES_SETKEY_DEC_ALT
+//#define MBEDTLS_AES_ENCRYPT_ALT
+//#define MBEDTLS_AES_DECRYPT_ALT
+//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT
+//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT
+//#define MBEDTLS_ECDSA_VERIFY_ALT
+//#define MBEDTLS_ECDSA_SIGN_ALT
+//#define MBEDTLS_ECDSA_GENKEY_ALT
+
+/**
+ * \def MBEDTLS_ECP_INTERNAL_ALT
+ *
+ * Expose a part of the internal interface of the Elliptic Curve Point module.
+ *
+ * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternative core implementation of elliptic curve arithmetic. Keep in mind
+ * that function prototypes should remain the same.
+ *
+ * This partially replaces one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation
+ * is still present and it is used for group structures not supported by the
+ * alternative.
+ *
+ * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT
+ * and implementing the following functions:
+ * unsigned char mbedtls_internal_ecp_grp_capable(
+ * const mbedtls_ecp_group *grp )
+ * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
+ * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp )
+ * The mbedtls_internal_ecp_grp_capable function should return 1 if the
+ * replacement functions implement arithmetic for the given group and 0
+ * otherwise.
+ * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are
+ * called before and after each point operation and provide an opportunity to
+ * implement optimized set up and tear down instructions.
+ *
+ * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and
+ * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac
+ * function, but will use your mbedtls_internal_ecp_double_jac if the group is
+ * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when
+ * receives it as an argument). If the group is not supported then the original
+ * implementation is used. The other functions and the definition of
+ * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your
+ * implementation of mbedtls_internal_ecp_double_jac and
+ * mbedtls_internal_ecp_grp_capable must be compatible with this definition.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+/* Required for all the functions in this section */
+//#define MBEDTLS_ECP_INTERNAL_ALT
+/* Support for Weierstrass curves with Jacobi representation */
+//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
+//#define MBEDTLS_ECP_ADD_MIXED_ALT
+//#define MBEDTLS_ECP_DOUBLE_JAC_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT
+//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT
+/* Support for curves with Montgomery arithmetic */
+//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT
+//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT
+//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT
+
+/**
+ * \def MBEDTLS_TEST_NULL_ENTROPY
+ *
+ * Enables testing and use of mbed TLS without any configured entropy sources.
+ * This permits use of the library on platforms before an entropy source has
+ * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the
+ * MBEDTLS_ENTROPY_NV_SEED switches).
+ *
+ * WARNING! This switch MUST be disabled in production builds, and is suitable
+ * only for development.
+ * Enabling the switch negates any security provided by the library.
+ *
+ * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ */
+//#define MBEDTLS_TEST_NULL_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_HARDWARE_ALT
+ *
+ * Uncomment this macro to let mbed TLS use your own implementation of a
+ * hardware entropy collector.
+ *
+ * Your function must be called \c mbedtls_hardware_poll(), have the same
+ * prototype as declared in entropy_poll.h, and accept NULL as first argument.
+ *
+ * Uncomment to use your own hardware entropy collector.
+ */
+//#define MBEDTLS_ENTROPY_HARDWARE_ALT
+
+/**
+ * \def MBEDTLS_AES_ROM_TABLES
+ *
+ * Use precomputed AES tables stored in ROM.
+ *
+ * Uncomment this macro to use precomputed AES tables stored in ROM.
+ * Comment this macro to generate AES tables in RAM at runtime.
+ *
+ * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb
+ * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the
+ * initialization time before the first AES operation can be performed.
+ * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c
+ * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded
+ * performance if ROM access is slower than RAM access.
+ *
+ * This option is independent of \c MBEDTLS_AES_FEWER_TABLES.
+ *
+ */
+//#define MBEDTLS_AES_ROM_TABLES
+
+/**
+ * \def MBEDTLS_AES_FEWER_TABLES
+ *
+ * Use less ROM/RAM for AES tables.
+ *
+ * Uncommenting this macro omits 75% of the AES tables from
+ * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES)
+ * by computing their values on the fly during operations
+ * (the tables are entry-wise rotations of one another).
+ *
+ * Tradeoff: Uncommenting this reduces the RAM / ROM footprint
+ * by ~6kb but at the cost of more arithmetic operations during
+ * runtime. Specifically, one has to compare 4 accesses within
+ * different tables to 4 accesses with additional arithmetic
+ * operations within the same table. The performance gain/loss
+ * depends on the system and memory details.
+ *
+ * This option is independent of \c MBEDTLS_AES_ROM_TABLES.
+ *
+ */
+//#define MBEDTLS_AES_FEWER_TABLES
+
+/**
+ * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
+ *
+ * Use less ROM for the Camellia implementation (saves about 768 bytes).
+ *
+ * Uncomment this macro to use less memory for Camellia.
+ */
+//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CBC
+ *
+ * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CBC
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CFB
+ *
+ * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CTR
+ *
+ * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CTR
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_OFB
+ *
+ * Enable Output Feedback mode (OFB) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_OFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_XTS
+ *
+ * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES.
+ */
+#define MBEDTLS_CIPHER_MODE_XTS
+
+/**
+ * \def MBEDTLS_CIPHER_NULL_CIPHER
+ *
+ * Enable NULL cipher.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * encryption or channels without any security!
+ *
+ * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
+ * the following ciphersuites:
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_WITH_NULL_SHA
+ * MBEDTLS_TLS_RSA_WITH_NULL_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+ * MBEDTLS_TLS_PSK_WITH_NULL_SHA
+ *
+ * Uncomment this macro to enable the NULL cipher and ciphersuites
+ */
+//#define MBEDTLS_CIPHER_NULL_CIPHER
+
+/**
+ * \def MBEDTLS_CIPHER_PADDING_PKCS7
+ *
+ * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
+ * specific padding modes in the cipher layer with cipher modes that support
+ * padding (e.g. CBC)
+ *
+ * If you disable all padding modes, only full blocks can be used with CBC.
+ *
+ * Enable padding modes in the cipher layer.
+ */
+#define MBEDTLS_CIPHER_PADDING_PKCS7
+#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#define MBEDTLS_CIPHER_PADDING_ZEROS
+
+/**
+ * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+ *
+ * Enable weak ciphersuites in SSL / TLS.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * channels with virtually no security at all!
+ *
+ * This enables the following ciphersuites:
+ * MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+ *
+ * Uncomment this macro to enable weak ciphersuites
+ *
+ * \warning DES is considered a weak cipher and its use constitutes a
+ * security risk. We recommend considering stronger ciphers instead.
+ */
+//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+ *
+ * Remove RC4 ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on RC4 from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
+ * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
+ * explicitly.
+ *
+ * Uncomment this macro to remove RC4 ciphersuites by default.
+ */
+#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_3DES_CIPHERSUITES
+ *
+ * Remove 3DES ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on 3DES from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible
+ * to enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including
+ * them explicitly.
+ *
+ * A man-in-the-browser attacker can recover authentication tokens sent through
+ * a TLS connection using a 3DES based cipher suite (see "On the Practical
+ * (In-)Security of 64-bit Block Ciphers" by Karthikeyan Bhargavan and Gaëtan
+ * Leurent, see https://sweet32.info/SWEET32_CCS16.pdf). If this attack falls
+ * in your threat model or you are unsure, then you should keep this option
+ * enabled to remove 3DES based cipher suites.
+ *
+ * Comment this macro to keep 3DES in the default ciphersuite list.
+ */
+#define MBEDTLS_REMOVE_3DES_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
+ *
+ * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
+ * module. By default all supported curves are enabled.
+ *
+ * Comment macros to disable the curve and functions for it
+ */
+// #define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+// #define MBEDTLS_ECP_DP_BP256R1_ENABLED
+// #define MBEDTLS_ECP_DP_BP384R1_ENABLED
+// #define MBEDTLS_ECP_DP_BP512R1_ENABLED
+// #define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+// #define MBEDTLS_ECP_DP_CURVE448_ENABLED
+
+/**
+ * \def MBEDTLS_ECP_NIST_OPTIM
+ *
+ * Enable specific 'modulo p' routines for each NIST prime.
+ * Depending on the prime and architecture, makes operations 4 to 8 times
+ * faster on the corresponding curve.
+ *
+ * Comment this macro to disable NIST curves optimisation.
+ */
+#define MBEDTLS_ECP_NIST_OPTIM
+
+/**
+ * \def MBEDTLS_ECP_RESTARTABLE
+ *
+ * Enable "non-blocking" ECC operations that can return early and be resumed.
+ *
+ * This allows various functions to pause by returning
+ * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module,
+ * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in
+ * order to further progress and eventually complete their operation. This is
+ * controlled through mbedtls_ecp_set_max_ops() which limits the maximum
+ * number of ECC operations a function may perform before pausing; see
+ * mbedtls_ecp_set_max_ops() for more information.
+ *
+ * This is useful in non-threaded environments if you want to avoid blocking
+ * for too long on ECC (and, hence, X.509 or SSL/TLS) operations.
+ *
+ * Uncomment this macro to enable restartable ECC computations.
+ *
+ * \note This option only works with the default software implementation of
+ * elliptic curve functionality. It is incompatible with
+ * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT, MBEDTLS_ECDSA_XXX_ALT
+ * and MBEDTLS_ECDH_LEGACY_CONTEXT.
+ */
+//#define MBEDTLS_ECP_RESTARTABLE
+
+/**
+ * \def MBEDTLS_ECDH_LEGACY_CONTEXT
+ *
+ * Use a backward compatible ECDH context.
+ *
+ * Mbed TLS supports two formats for ECDH contexts (#mbedtls_ecdh_context
+ * defined in `ecdh.h`). For most applications, the choice of format makes
+ * no difference, since all library functions can work with either format,
+ * except that the new format is incompatible with MBEDTLS_ECP_RESTARTABLE.
+
+ * The new format used when this option is disabled is smaller
+ * (56 bytes on a 32-bit platform). In future versions of the library, it
+ * will support alternative implementations of ECDH operations.
+ * The new format is incompatible with applications that access
+ * context fields directly and with restartable ECP operations.
+ *
+ * Define this macro if you enable MBEDTLS_ECP_RESTARTABLE or if you
+ * want to access ECDH context fields directly. Otherwise you should
+ * comment out this macro definition.
+ *
+ * This option has no effect if #MBEDTLS_ECDH_C is not enabled.
+ *
+ * \note This configuration option is experimental. Future versions of the
+ * library may modify the way the ECDH context layout is configured
+ * and may modify the layout of the new context type.
+ */
+#define MBEDTLS_ECDH_LEGACY_CONTEXT
+
+/**
+ * \def MBEDTLS_ECDSA_DETERMINISTIC
+ *
+ * Enable deterministic ECDSA (RFC 6979).
+ * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
+ * may result in a compromise of the long-term signing key. This is avoided by
+ * the deterministic variant.
+ *
+ * Requires: MBEDTLS_HMAC_DRBG_C
+ *
+ * Comment this macro to disable deterministic ECDSA.
+ */
+#define MBEDTLS_ECDSA_DETERMINISTIC
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+ *
+ * Enable the PSK based ciphersuite modes in SSL / TLS.
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+ *
+ * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ *
+ * \warning Using DHE constitutes a security risk as it
+ * is not possible to validate custom DH parameters.
+ * If possible, it is recommended users should consider
+ * preferring other methods of key exchange.
+ * See dhm.h for more details.
+ *
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+ *
+ * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+ *
+ * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+ *
+ * Enable the RSA-only based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+ *
+ * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *
+ * \warning Using DHE constitutes a security risk as it
+ * is not possible to validate custom DH parameters.
+ * If possible, it is recommended users should consider
+ * preferring other methods of key exchange.
+ * See dhm.h for more details.
+ *
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+ *
+ * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ * MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+ *
+ * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+ *
+ * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+ *
+ * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+ *
+ * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Requires: MBEDTLS_ECJPAKE_C
+ * MBEDTLS_SHA256_C
+ * MBEDTLS_ECP_DP_SECP256R1_ENABLED
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+/**
+ * \def MBEDTLS_PK_PARSE_EC_EXTENDED
+ *
+ * Enhance support for reading EC keys using variants of SEC1 not allowed by
+ * RFC 5915 and RFC 5480.
+ *
+ * Currently this means parsing the SpecifiedECDomain choice of EC
+ * parameters (only known groups are supported, not arbitrary domains, to
+ * avoid validation issues).
+ *
+ * Disable if you only need to support RFC 5915 + 5480 key formats.
+ */
+#define MBEDTLS_PK_PARSE_EC_EXTENDED
+
+/**
+ * \def MBEDTLS_ERROR_STRERROR_DUMMY
+ *
+ * Enable a dummy error function to make use of mbedtls_strerror() in
+ * third party libraries easier when MBEDTLS_ERROR_C is disabled
+ * (no effect when MBEDTLS_ERROR_C is enabled).
+ *
+ * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
+ * not using mbedtls_strerror() or error_strerror() in your application.
+ *
+ * Disable if you run into name conflicts and want to really remove the
+ * mbedtls_strerror()
+ */
+// #define MBEDTLS_ERROR_STRERROR_DUMMY
+
+/**
+ * \def MBEDTLS_GENPRIME
+ *
+ * Enable the prime-number generation code.
+ *
+ * Requires: MBEDTLS_BIGNUM_C
+ */
+#define MBEDTLS_GENPRIME
+
+/**
+ * \def MBEDTLS_FS_IO
+ *
+ * Enable functions that use the filesystem.
+ */
+// #define MBEDTLS_FS_IO
+
+/**
+ * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ * Do not add default entropy sources. These are the platform specific,
+ * mbedtls_timing_hardclock and HAVEGE based poll functions.
+ *
+ * This is useful to have more control over the added entropy sources in an
+ * application.
+ *
+ * Uncomment this macro to prevent loading of default entropy functions.
+ */
+//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+/**
+ * \def MBEDTLS_NO_PLATFORM_ENTROPY
+ *
+ * Do not use built-in platform entropy functions.
+ * This is useful if your platform does not support
+ * standards like the /dev/urandom or Windows CryptoAPI.
+ *
+ * Uncomment this macro to disable the built-in platform entropy functions.
+ */
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_FORCE_SHA256
+ *
+ * Force the entropy accumulator to use a SHA-256 accumulator instead of the
+ * default SHA-512 based one (if both are available).
+ *
+ * Requires: MBEDTLS_SHA256_C
+ *
+ * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
+ * if you have performance concerns.
+ *
+ * This option is only useful if both MBEDTLS_SHA256_C and
+ * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
+ */
+//#define MBEDTLS_ENTROPY_FORCE_SHA256
+
+/**
+ * \def MBEDTLS_ENTROPY_NV_SEED
+ *
+ * Enable the non-volatile (NV) seed file-based entropy source.
+ * (Also enables the NV seed read/write functions in the platform layer)
+ *
+ * This is crucial (if not required) on systems that do not have a
+ * cryptographic entropy source (in hardware or kernel) available.
+ *
+ * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C
+ *
+ * \note The read/write functions that are used by the entropy source are
+ * determined in the platform layer, and can be modified at runtime and/or
+ * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used.
+ *
+ * \note If you use the default implementation functions that read a seedfile
+ * with regular fopen(), please make sure you make a seedfile with the
+ * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at
+ * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from
+ * and written to or you will get an entropy source error! The default
+ * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE
+ * bytes from the file.
+ *
+ * \note The entropy collector will write to the seed file before entropy is
+ * given to an external source, to update it.
+ */
+//#define MBEDTLS_ENTROPY_NV_SEED
+
+/**
+ * \def MBEDTLS_MEMORY_DEBUG
+ *
+ * Enable debugging of buffer allocator memory issues. Automatically prints
+ * (to stderr) all (fatal) messages on memory allocation issues. Enables
+ * function for 'debug output' of allocated memory.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Uncomment this macro to let the buffer allocator print out error messages.
+ */
+//#define MBEDTLS_MEMORY_DEBUG
+
+/**
+ * \def MBEDTLS_MEMORY_BACKTRACE
+ *
+ * Include backtrace information with each allocated block.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ * GLIBC-compatible backtrace() an backtrace_symbols() support
+ *
+ * Uncomment this macro to include backtrace information
+ */
+//#define MBEDTLS_MEMORY_BACKTRACE
+
+/**
+ * \def MBEDTLS_PK_RSA_ALT_SUPPORT
+ *
+ * Support external private RSA keys (eg from a HSM) in the PK layer.
+ *
+ * Comment this macro to disable support for external private RSA keys.
+ */
+// #define MBEDTLS_PK_RSA_ALT_SUPPORT
+
+/**
+ * \def MBEDTLS_PKCS1_V15
+ *
+ * Enable support for PKCS#1 v1.5 encoding.
+ *
+ * Requires: MBEDTLS_RSA_C
+ *
+ * This enables support for PKCS#1 v1.5 operations.
+ */
+#define MBEDTLS_PKCS1_V15
+
+/**
+ * \def MBEDTLS_PKCS1_V21
+ *
+ * Enable support for PKCS#1 v2.1 encoding.
+ *
+ * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
+ *
+ * This enables support for RSAES-OAEP and RSASSA-PSS operations.
+ */
+#define MBEDTLS_PKCS1_V21
+
+/**
+ * \def MBEDTLS_PSA_CRYPTO_SPM
+ *
+ * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is built for SPM (Secure
+ * Partition Manager) integration which separates the code into two parts: a
+ * NSPE (Non-Secure Process Environment) and an SPE (Secure Process
+ * Environment).
+ *
+ * Module: library/psa_crypto.c
+ * Requires: MBEDTLS_PSA_CRYPTO_C
+ *
+ */
+//#define MBEDTLS_PSA_CRYPTO_SPM
+
+/**
+ * \def MBEDTLS_PSA_INJECT_ENTROPY
+ *
+ * Enable support for entropy injection at first boot. This feature is
+ * required on systems that do not have a built-in entropy source (TRNG).
+ * This feature is currently not supported on systems that have a built-in
+ * entropy source.
+ *
+ * Requires: MBEDTLS_PSA_CRYPTO_STORAGE_C, MBEDTLS_ENTROPY_NV_SEED
+ *
+ */
+//#define MBEDTLS_PSA_INJECT_ENTROPY
+
+/**
+ * \def MBEDTLS_RSA_NO_CRT
+ *
+ * Do not use the Chinese Remainder Theorem
+ * for the RSA private operation.
+ *
+ * Uncomment this macro to disable the use of CRT in RSA.
+ *
+ */
+//#define MBEDTLS_RSA_NO_CRT
+
+/**
+ * \def MBEDTLS_SELF_TEST
+ *
+ * Enable the checkup functions (*_self_test).
+ */
+#define MBEDTLS_SELF_TEST
+
+/**
+ * \def MBEDTLS_SHA256_SMALLER
+ *
+ * Enable an implementation of SHA-256 that has lower ROM footprint but also
+ * lower performance.
+ *
+ * The default implementation is meant to be a reasonnable compromise between
+ * performance and size. This version optimizes more aggressively for size at
+ * the expense of performance. Eg on Cortex-M4 it reduces the size of
+ * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
+ * 30%.
+ *
+ * Uncomment to enable the smaller implementation of SHA256.
+ */
+//#define MBEDTLS_SHA256_SMALLER
+
+/**
+ * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
+ *
+ * Enable sending of alert messages in case of encountered errors as per RFC.
+ * If you choose not to send the alert messages, mbed TLS can still communicate
+ * with other servers, only debugging of failures is harder.
+ *
+ * The advantage of not sending alert messages, is that no information is given
+ * about reasons for failures thus preventing adversaries of gaining intel.
+ *
+ * Enable sending of all alert messages
+ */
+#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+
+/**
+ * \def MBEDTLS_SSL_RECORD_CHECKING
+ *
+ * Enable the function mbedtls_ssl_check_record() which can be used to check
+ * the validity and authenticity of an incoming record, to verify that it has
+ * not been seen before. These checks are performed without modifying the
+ * externally visible state of the SSL context.
+ *
+ * See mbedtls_ssl_check_record() for more information.
+ *
+ * Uncomment to enable support for record checking.
+ */
+#define MBEDTLS_SSL_RECORD_CHECKING
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CONNECTION_ID
+ *
+ * Enable support for the DTLS Connection ID extension
+ * (version draft-ietf-tls-dtls-connection-id-05,
+ * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05)
+ * which allows to identify DTLS connections across changes
+ * in the underlying transport.
+ *
+ * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`,
+ * `mbedtls_ssl_get_peer_cid()` and `mbedtls_ssl_conf_cid()`.
+ * See the corresponding documentation for more information.
+ *
+ * \warning The Connection ID extension is still in draft state.
+ * We make no stability promises for the availability
+ * or the shape of the API controlled by this option.
+ *
+ * The maximum lengths of outgoing and incoming CIDs can be configured
+ * through the options
+ * - MBEDTLS_SSL_CID_OUT_LEN_MAX
+ * - MBEDTLS_SSL_CID_IN_LEN_MAX.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Uncomment to enable the Connection ID extension.
+ */
+//#define MBEDTLS_SSL_DTLS_CONNECTION_ID
+
+/**
+ * \def MBEDTLS_SSL_ASYNC_PRIVATE
+ *
+ * Enable asynchronous external private key operations in SSL. This allows
+ * you to configure an SSL connection to call an external cryptographic
+ * module to perform private key operations instead of performing the
+ * operation inside the library.
+ *
+ */
+//#define MBEDTLS_SSL_ASYNC_PRIVATE
+
+/**
+ * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION
+ *
+ * Enable serialization of the TLS context structures, through use of the
+ * functions mbedtls_ssl_context_save() and mbedtls_ssl_context_load().
+ *
+ * This pair of functions allows one side of a connection to serialize the
+ * context associated with the connection, then free or re-use that context
+ * while the serialized state is persisted elsewhere, and finally deserialize
+ * that state to a live context for resuming read/write operations on the
+ * connection. From a protocol perspective, the state of the connection is
+ * unaffected, in particular this is entirely transparent to the peer.
+ *
+ * Note: this is distinct from TLS session resumption, which is part of the
+ * protocol and fully visible by the peer. TLS session resumption enables
+ * establishing new connections associated to a saved session with shorter,
+ * lighter handshakes, while context serialization is a local optimization in
+ * handling a single, potentially long-lived connection.
+ *
+ * Enabling these APIs makes some SSL structures larger, as 64 extra bytes are
+ * saved after the handshake to allow for more efficient serialization, so if
+ * you don't need this feature you'll save RAM by disabling it.
+ *
+ * Comment to disable the context serialization APIs.
+ */
+#define MBEDTLS_SSL_CONTEXT_SERIALIZATION
+
+/**
+ * \def MBEDTLS_SSL_DEBUG_ALL
+ *
+ * Enable the debug messages in SSL module for all issues.
+ * Debug messages have been disabled in some places to prevent timing
+ * attacks due to (unbalanced) debugging function calls.
+ *
+ * If you need all error reporting you should enable this during debugging,
+ * but remove this for production servers that should log as well.
+ *
+ * Uncomment this macro to report all debug messages on errors introducing
+ * a timing side-channel.
+ *
+ */
+//#define MBEDTLS_SSL_DEBUG_ALL
+
+/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
+ *
+ * Enable support for Encrypt-then-MAC, RFC 7366.
+ *
+ * This allows peers that both support it to use a more robust protection for
+ * ciphersuites using CBC, providing deep resistance against timing attacks
+ * on the padding or underlying cipher.
+ *
+ * This only affects CBC ciphersuites, and is useless if none is defined.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Encrypt-then-MAC
+ */
+#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+
+/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+ *
+ * Enable support for Extended Master Secret, aka Session Hash
+ * (draft-ietf-tls-session-hash-02).
+ *
+ * This was introduced as "the proper fix" to the Triple Handshake familiy of
+ * attacks, but it is recommended to always use it (even if you disable
+ * renegotiation), since it actually fixes a more fundamental issue in the
+ * original SSL/TLS design, and has implications beyond Triple Handshake.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1 or
+ * MBEDTLS_SSL_PROTO_TLS1_1 or
+ * MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Extended Master Secret.
+ */
+#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+
+/**
+ * \def MBEDTLS_SSL_FALLBACK_SCSV
+ *
+ * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
+ *
+ * For servers, it is recommended to always enable this, unless you support
+ * only one version of TLS, or know for sure that none of your clients
+ * implements a fallback strategy.
+ *
+ * For clients, you only need this if you're using a fallback strategy, which
+ * is not recommended in the first place, unless you absolutely need it to
+ * interoperate with buggy (version-intolerant) servers.
+ *
+ * Comment this macro to disable support for FALLBACK_SCSV
+ */
+#define MBEDTLS_SSL_FALLBACK_SCSV
+
+/**
+ * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE
+ *
+ * This option controls the availability of the API mbedtls_ssl_get_peer_cert()
+ * giving access to the peer's certificate after completion of the handshake.
+ *
+ * Unless you need mbedtls_ssl_peer_cert() in your application, it is
+ * recommended to disable this option for reduced RAM usage.
+ *
+ * \note If this option is disabled, mbedtls_ssl_get_peer_cert() is still
+ * defined, but always returns \c NULL.
+ *
+ * \note This option has no influence on the protection against the
+ * triple handshake attack. Even if it is disabled, Mbed TLS will
+ * still ensure that certificates do not change during renegotiation,
+ * for exaple by keeping a hash of the peer's certificate.
+ *
+ * Comment this macro to disable storing the peer's certificate
+ * after the handshake.
+ */
+#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE
+
+/**
+ * \def MBEDTLS_SSL_HW_RECORD_ACCEL
+ *
+ * Enable hooking functions in SSL module for hardware acceleration of
+ * individual records.
+ *
+ * Uncomment this macro to enable hooking functions.
+ */
+//#define MBEDTLS_SSL_HW_RECORD_ACCEL
+
+/**
+ * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
+ *
+ * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
+ *
+ * This is a countermeasure to the BEAST attack, which also minimizes the risk
+ * of interoperability issues compared to sending 0-length records.
+ *
+ * Comment this macro to disable 1/n-1 record splitting.
+ */
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
+
+/**
+ * \def MBEDTLS_SSL_RENEGOTIATION
+ *
+ * Enable support for TLS renegotiation.
+ *
+ * The two main uses of renegotiation are (1) refresh keys on long-lived
+ * connections and (2) client authentication after the initial handshake.
+ * If you don't need renegotiation, it's probably better to disable it, since
+ * it has been associated with security issues in the past and is easy to
+ * misuse/misunderstand.
+ *
+ * Comment this to disable support for renegotiation.
+ *
+ * \note Even if this option is disabled, both client and server are aware
+ * of the Renegotiation Indication Extension (RFC 5746) used to
+ * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1).
+ * (See \c mbedtls_ssl_conf_legacy_renegotiation for the
+ * configuration of this extension).
+ *
+ */
+#define MBEDTLS_SSL_RENEGOTIATION
+
+/**
+ * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+ *
+ * Enable support for receiving and parsing SSLv2 Client Hello messages for the
+ * SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to enable support for SSLv2 Client Hello messages.
+ */
+//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+
+/**
+ * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+ *
+ * Pick the ciphersuite according to the client's preferences rather than ours
+ * in the SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to respect client's ciphersuite order
+ */
+//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+
+/**
+ * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+ *
+ * Enable support for RFC 6066 max_fragment_length extension in SSL.
+ *
+ * Comment this macro to disable support for the max_fragment_length extension
+ */
+#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+
+/**
+ * \def MBEDTLS_SSL_PROTO_SSL3
+ *
+ * Enable support for SSL 3.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for SSL 3.0
+ */
+//#define MBEDTLS_SSL_PROTO_SSL3
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1
+ *
+ * Enable support for TLS 1.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_1
+ *
+ * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_MD5_C
+ * MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
+ * (Depends on ciphersuites)
+ *
+ * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_2
+
+/**
+ * \def MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Enable support for DTLS (all available versions).
+ *
+ * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
+ * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1_1
+ * or MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for DTLS
+ */
+#define MBEDTLS_SSL_PROTO_DTLS
+
+/**
+ * \def MBEDTLS_SSL_ALPN
+ *
+ * Enable support for RFC 7301 Application Layer Protocol Negotiation.
+ *
+ * Comment this macro to disable support for ALPN.
+ */
+#define MBEDTLS_SSL_ALPN
+
+/**
+ * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
+ *
+ * Enable support for the anti-replay mechanism in DTLS.
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ * MBEDTLS_SSL_PROTO_DTLS
+ *
+ * \warning Disabling this is often a security risk!
+ * See mbedtls_ssl_conf_dtls_anti_replay() for details.
+ *
+ * Comment this to disable anti-replay in DTLS.
+ */
+#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Enable support for HelloVerifyRequest on DTLS servers.
+ *
+ * This feature is highly recommended to prevent DTLS servers being used as
+ * amplifiers in DoS attacks against other hosts. It should always be enabled
+ * unless you know for sure amplification cannot be a problem in the
+ * environment in which your server operates.
+ *
+ * \warning Disabling this can ba a security risk! (see above)
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Comment this to disable support for HelloVerifyRequest.
+ */
+#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+ *
+ * Enable server-side support for clients that reconnect from the same port.
+ *
+ * Some clients unexpectedly close the connection and try to reconnect using the
+ * same source port. This needs special support from the server to handle the
+ * new connection securely, as described in section 4.2.8 of RFC 6347. This
+ * flag enables that support.
+ *
+ * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Comment this to disable support for clients reusing the source port.
+ */
+#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+
+/**
+ * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+ *
+ * Enable support for a limit of records with bad MAC.
+ *
+ * See mbedtls_ssl_conf_dtls_badmac_limit().
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ */
+#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+
+/**
+ * \def MBEDTLS_SSL_SESSION_TICKETS
+ *
+ * Enable support for RFC 5077 session tickets in SSL.
+ * Client-side, provides full support for session tickets (maintenance of a
+ * session store remains the responsibility of the application, though).
+ * Server-side, you also need to provide callbacks for writing and parsing
+ * tickets, including authenticated encryption and key management. Example
+ * callbacks are provided by MBEDTLS_SSL_TICKET_C.
+ *
+ * Comment this macro to disable support for SSL session tickets
+ */
+#define MBEDTLS_SSL_SESSION_TICKETS
+
+/**
+ * \def MBEDTLS_SSL_EXPORT_KEYS
+ *
+ * Enable support for exporting key block and master secret.
+ * This is required for certain users of TLS, e.g. EAP-TLS.
+ *
+ * Comment this macro to disable support for key export
+ */
+#define MBEDTLS_SSL_EXPORT_KEYS
+
+/**
+ * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
+ *
+ * Enable support for RFC 6066 server name indication (SNI) in SSL.
+ *
+ * Requires: MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Comment this macro to disable support for server name indication in SSL
+ */
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC
+ *
+ * Enable support for RFC 6066 truncated HMAC in SSL.
+ *
+ * Comment this macro to disable support for truncated HMAC in SSL
+ */
+#define MBEDTLS_SSL_TRUNCATED_HMAC
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT
+ *
+ * Fallback to old (pre-2.7), non-conforming implementation of the truncated
+ * HMAC extension which also truncates the HMAC key. Note that this option is
+ * only meant for a transitory upgrade period and is likely to be removed in
+ * a future version of the library.
+ *
+ * \warning The old implementation is non-compliant and has a security weakness
+ * (2^80 brute force attack on the HMAC key used for a single,
+ * uninterrupted connection). This should only be enabled temporarily
+ * when (1) the use of truncated HMAC is essential in order to save
+ * bandwidth, and (2) the peer is an Mbed TLS stack that doesn't use
+ * the fixed implementation yet (pre-2.7).
+ *
+ * \deprecated This option is deprecated and will likely be removed in a
+ * future version of Mbed TLS.
+ *
+ * Uncomment to fallback to old, non-compliant truncated HMAC implementation.
+ *
+ * Requires: MBEDTLS_SSL_TRUNCATED_HMAC
+ */
+//#define MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT
+
+/**
+ * \def MBEDTLS_THREADING_ALT
+ *
+ * Provide your own alternate threading implementation.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to allow your own alternate threading implementation.
+ */
+//#define MBEDTLS_THREADING_ALT
+
+/**
+ * \def MBEDTLS_THREADING_PTHREAD
+ *
+ * Enable the pthread wrapper layer for the threading layer.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to enable pthread mutexes.
+ */
+//#define MBEDTLS_THREADING_PTHREAD
+
+/**
+ * \def MBEDTLS_USE_PSA_CRYPTO
+ *
+ * Make the X.509 and TLS library use PSA for cryptographic operations, and
+ * enable new APIs for using keys handled by PSA Crypto.
+ *
+ * \note Development of this option is currently in progress, and parts
+ * of the X.509 and TLS modules are not ported to PSA yet. However, these parts
+ * will still continue to work as usual, so enabling this option should not
+ * break backwards compatibility.
+ *
+ * \warning The PSA Crypto API is in beta stage. While you're welcome to
+ * experiment using it, incompatible API changes are still possible, and some
+ * parts may not have reached the same quality as the rest of Mbed TLS yet.
+ *
+ * \warning This option enables new Mbed TLS APIs that are dependent on the
+ * PSA Crypto API, so can't come with the same stability guarantees as the
+ * rest of the Mbed TLS APIs. You're welcome to experiment with them, but for
+ * now, access to these APIs is opt-in (via enabling the present option), in
+ * order to clearly differentiate them from the stable Mbed TLS APIs.
+ *
+ * Requires: MBEDTLS_PSA_CRYPTO_C.
+ *
+ * Uncomment this to enable internal use of PSA Crypto and new associated APIs.
+ */
+//#define MBEDTLS_USE_PSA_CRYPTO
+
+/**
+ * \def MBEDTLS_VERSION_FEATURES
+ *
+ * Allow run-time checking of compile-time enabled features. Thus allowing users
+ * to check at run-time if the library is for instance compiled with threading
+ * support via mbedtls_version_check_feature().
+ *
+ * Requires: MBEDTLS_VERSION_C
+ *
+ * Comment this to disable run-time checking and save ROM space
+ */
+// #define MBEDTLS_VERSION_FEATURES
+
+/**
+ * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an extension in a v1 or v2 certificate.
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+
+/**
+ * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an unknown critical extension.
+ *
+ * \warning Depending on your PKI use, enabling this can be a security risk!
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+
+/**
+ * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK
+ *
+ * If set, this enables the X.509 API `mbedtls_x509_crt_verify_with_ca_cb()`
+ * and the SSL API `mbedtls_ssl_conf_ca_cb()` which allow users to configure
+ * the set of trusted certificates through a callback instead of a linked
+ * list.
+ *
+ * This is useful for example in environments where a large number of trusted
+ * certificates is present and storing them in a linked list isn't efficient
+ * enough, or when the set of trusted certificates changes frequently.
+ *
+ * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and
+ * `mbedtls_ssl_conf_ca_cb()` for more information.
+ *
+ * Uncomment to enable trusted certificate callbacks.
+ */
+//#define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK
+
+/**
+ * \def MBEDTLS_X509_CHECK_KEY_USAGE
+ *
+ * Enable verification of the keyUsage extension (CA and leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused
+ * (intermediate) CA and leaf certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip keyUsage checking for both CA and leaf certificates.
+ */
+#define MBEDTLS_X509_CHECK_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+ *
+ * Enable verification of the extendedKeyUsage extension (leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip extendedKeyUsage checking for certificates.
+ */
+#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
+ *
+ * Enable parsing and verification of X.509 certificates, CRLs and CSRS
+ * signed with RSASSA-PSS (aka PKCS#1 v2.1).
+ *
+ * Comment this macro to disallow using RSASSA-PSS in certificates.
+ */
+#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+
+/**
+ * \def MBEDTLS_ZLIB_SUPPORT
+ *
+ * If set, the SSL/TLS module uses ZLIB to support compression and
+ * decompression of packet data.
+ *
+ * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
+ * CRIME attack. Before enabling this option, you should examine with care if
+ * CRIME or similar exploits may be applicable to your use case.
+ *
+ * \note Currently compression can't be used with DTLS.
+ *
+ * \deprecated This feature is deprecated and will be removed
+ * in the next major revision of the library.
+ *
+ * Used in: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This feature requires zlib library and headers to be present.
+ *
+ * Uncomment to enable use of ZLIB
+ */
+//#define MBEDTLS_ZLIB_SUPPORT
+/* \} name SECTION: mbed TLS feature support */
+
+/**
+ * \name SECTION: mbed TLS modules
+ *
+ * This section enables or disables entire modules in mbed TLS
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_AESNI_C
+ *
+ * Enable AES-NI support on x86-64.
+ *
+ * Module: library/aesni.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the AES-NI instructions on x86-64
+ */
+#define MBEDTLS_AESNI_C
+
+/**
+ * \def MBEDTLS_AES_C
+ *
+ * Enable the AES block cipher.
+ *
+ * Module: library/aes.c
+ * Caller: library/cipher.c
+ * library/pem.c
+ * library/ctr_drbg.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *
+ * PEM_PARSE uses AES for decrypting encrypted keys.
+ */
+#define MBEDTLS_AES_C
+
+/**
+ * \def MBEDTLS_ARC4_C
+ *
+ * Enable the ARCFOUR stream cipher.
+ *
+ * Module: library/arc4.c
+ * Caller: library/cipher.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ *
+ * \warning ARC4 is considered a weak cipher and its use constitutes a
+ * security risk. If possible, we recommend avoidng dependencies on
+ * it, and considering stronger ciphers instead.
+ *
+ */
+#define MBEDTLS_ARC4_C
+
+/**
+ * \def MBEDTLS_ASN1_PARSE_C
+ *
+ * Enable the generic ASN1 parser.
+ *
+ * Module: library/asn1.c
+ * Caller: library/x509.c
+ * library/dhm.c
+ * library/pkcs12.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ */
+#define MBEDTLS_ASN1_PARSE_C
+
+/**
+ * \def MBEDTLS_ASN1_WRITE_C
+ *
+ * Enable the generic ASN1 writer.
+ *
+ * Module: library/asn1write.c
+ * Caller: library/ecdsa.c
+ * library/pkwrite.c
+ * library/x509_create.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ */
+#define MBEDTLS_ASN1_WRITE_C
+
+/**
+ * \def MBEDTLS_BASE64_C
+ *
+ * Enable the Base64 module.
+ *
+ * Module: library/base64.c
+ * Caller: library/pem.c
+ *
+ * This module is required for PEM support (required by X.509).
+ */
+#define MBEDTLS_BASE64_C
+
+/**
+ * \def MBEDTLS_BIGNUM_C
+ *
+ * Enable the multi-precision integer library.
+ *
+ * Module: library/bignum.c
+ * Caller: library/dhm.c
+ * library/ecp.c
+ * library/ecdsa.c
+ * library/rsa.c
+ * library/rsa_internal.c
+ * library/ssl_tls.c
+ *
+ * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
+ */
+#define MBEDTLS_BIGNUM_C
+
+/**
+ * \def MBEDTLS_BLOWFISH_C
+ *
+ * Enable the Blowfish block cipher.
+ *
+ * Module: library/blowfish.c
+ */
+#define MBEDTLS_BLOWFISH_C
+
+/**
+ * \def MBEDTLS_CAMELLIA_C
+ *
+ * Enable the Camellia block cipher.
+ *
+ * Module: library/camellia.c
+ * Caller: library/cipher.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ */
+#define MBEDTLS_CAMELLIA_C
+
+/**
+ * \def MBEDTLS_ARIA_C
+ *
+ * Enable the ARIA block cipher.
+ *
+ * Module: library/aria.c
+ * Caller: library/cipher.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *
+ * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384
+ * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256
+ * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384
+ */
+//#define MBEDTLS_ARIA_C
+
+/**
+ * \def MBEDTLS_CCM_C
+ *
+ * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
+ *
+ * Module: library/ccm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-CCM ciphersuites, if other requisites are
+ * enabled as well.
+ */
+#define MBEDTLS_CCM_C
+
+/**
+ * \def MBEDTLS_CERTS_C
+ *
+ * Enable the test certificates.
+ *
+ * Module: library/certs.c
+ * Caller:
+ *
+ * This module is used for testing (ssl_client/server).
+ */
+#define MBEDTLS_CERTS_C
+
+/**
+ * \def MBEDTLS_CHACHA20_C
+ *
+ * Enable the ChaCha20 stream cipher.
+ *
+ * Module: library/chacha20.c
+ */
+#define MBEDTLS_CHACHA20_C
+
+/**
+ * \def MBEDTLS_CHACHAPOLY_C
+ *
+ * Enable the ChaCha20-Poly1305 AEAD algorithm.
+ *
+ * Module: library/chachapoly.c
+ *
+ * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C
+ */
+#define MBEDTLS_CHACHAPOLY_C
+
+/**
+ * \def MBEDTLS_CIPHER_C
+ *
+ * Enable the generic cipher layer.
+ *
+ * Module: library/cipher.c
+ * Caller: library/ssl_tls.c
+ *
+ * Uncomment to enable generic cipher wrappers.
+ */
+#define MBEDTLS_CIPHER_C
+
+/**
+ * \def MBEDTLS_CMAC_C
+ *
+ * Enable the CMAC (Cipher-based Message Authentication Code) mode for block
+ * ciphers.
+ *
+ * Module: library/cmac.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C
+ *
+ */
+//#define MBEDTLS_CMAC_C
+
+/**
+ * \def MBEDTLS_CTR_DRBG_C
+ *
+ * Enable the CTR_DRBG AES-based random generator.
+ * The CTR_DRBG generator uses AES-256 by default.
+ * To use AES-128 instead, enable MBEDTLS_CTR_DRBG_USE_128_BIT_KEY below.
+ *
+ * Module: library/ctr_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_AES_C
+ *
+ * This module provides the CTR_DRBG AES random number generator.
+ */
+#define MBEDTLS_CTR_DRBG_C
+
+/**
+ * \def MBEDTLS_DEBUG_C
+ *
+ * Enable the debug functions.
+ *
+ * Module: library/debug.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module provides debugging functions.
+ */
+#define MBEDTLS_DEBUG_C
+
+/**
+ * \def MBEDTLS_DES_C
+ *
+ * Enable the DES block cipher.
+ *
+ * Module: library/des.c
+ * Caller: library/pem.c
+ * library/cipher.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *
+ * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
+ *
+ * \warning DES is considered a weak cipher and its use constitutes a
+ * security risk. We recommend considering stronger ciphers instead.
+ */
+#define MBEDTLS_DES_C
+
+/**
+ * \def MBEDTLS_DHM_C
+ *
+ * Enable the Diffie-Hellman-Merkle module.
+ *
+ * Module: library/dhm.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * DHE-RSA, DHE-PSK
+ *
+ * \warning Using DHE constitutes a security risk as it
+ * is not possible to validate custom DH parameters.
+ * If possible, it is recommended users should consider
+ * preferring other methods of key exchange.
+ * See dhm.h for more details.
+ *
+ */
+#define MBEDTLS_DHM_C
+
+/**
+ * \def MBEDTLS_ECDH_C
+ *
+ * Enable the elliptic curve Diffie-Hellman library.
+ *
+ * Module: library/ecdh.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
+ *
+ * Requires: MBEDTLS_ECP_C
+ */
+#define MBEDTLS_ECDH_C
+
+/**
+ * \def MBEDTLS_ECDSA_C
+ *
+ * Enable the elliptic curve DSA library.
+ *
+ * Module: library/ecdsa.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECDHE-ECDSA
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
+ */
+#define MBEDTLS_ECDSA_C
+
+/**
+ * \def MBEDTLS_ECJPAKE_C
+ *
+ * Enable the elliptic curve J-PAKE library.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Module: library/ecjpake.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ * ECJPAKE
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
+ */
+//#define MBEDTLS_ECJPAKE_C
+
+/**
+ * \def MBEDTLS_ECP_C
+ *
+ * Enable the elliptic curve over GF(p) library.
+ *
+ * Module: library/ecp.c
+ * Caller: library/ecdh.c
+ * library/ecdsa.c
+ * library/ecjpake.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
+ */
+#define MBEDTLS_ECP_C
+
+/**
+ * \def MBEDTLS_ENTROPY_C
+ *
+ * Enable the platform-specific entropy code.
+ *
+ * Module: library/entropy.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
+ *
+ * This module provides a generic entropy pool
+ */
+#define MBEDTLS_ENTROPY_C
+
+/**
+ * \def MBEDTLS_ERROR_C
+ *
+ * Enable error code to error string conversion.
+ *
+ * Module: library/error.c
+ * Caller:
+ *
+ * This module enables mbedtls_strerror().
+ */
+// #define MBEDTLS_ERROR_C
+
+/**
+ * \def MBEDTLS_GCM_C
+ *
+ * Enable the Galois/Counter Mode (GCM) for AES.
+ *
+ * Module: library/gcm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
+ * requisites are enabled as well.
+ */
+#define MBEDTLS_GCM_C
+
+/**
+ * \def MBEDTLS_HAVEGE_C
+ *
+ * Enable the HAVEGE random generator.
+ *
+ * Warning: the HAVEGE random generator is not suitable for virtualized
+ * environments
+ *
+ * Warning: the HAVEGE random generator is dependent on timing and specific
+ * processor traits. It is therefore not advised to use HAVEGE as
+ * your applications primary random generator or primary entropy pool
+ * input. As a secondary input to your entropy pool, it IS able add
+ * the (limited) extra entropy it provides.
+ *
+ * Module: library/havege.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_TIMING_C
+ *
+ * Uncomment to enable the HAVEGE random generator.
+ */
+//#define MBEDTLS_HAVEGE_C
+
+/**
+ * \def MBEDTLS_HKDF_C
+ *
+ * Enable the HKDF algorithm (RFC 5869).
+ *
+ * Module: library/hkdf.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the Hashed Message Authentication Code
+ * (HMAC)-based key derivation function (HKDF).
+ */
+#define MBEDTLS_HKDF_C
+
+/**
+ * \def MBEDTLS_HMAC_DRBG_C
+ *
+ * Enable the HMAC_DRBG random generator.
+ *
+ * Module: library/hmac_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * Uncomment to enable the HMAC_DRBG random number geerator.
+ */
+#define MBEDTLS_HMAC_DRBG_C
+
+/**
+ * \def MBEDTLS_NIST_KW_C
+ *
+ * Enable the Key Wrapping mode for 128-bit block ciphers,
+ * as defined in NIST SP 800-38F. Only KW and KWP modes
+ * are supported. At the moment, only AES is approved by NIST.
+ *
+ * Module: library/nist_kw.c
+ *
+ * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C
+ */
+//#define MBEDTLS_NIST_KW_C
+
+/**
+ * \def MBEDTLS_MD_C
+ *
+ * Enable the generic message digest layer.
+ *
+ * Module: library/md.c
+ * Caller:
+ *
+ * Uncomment to enable generic message digest wrappers.
+ */
+#define MBEDTLS_MD_C
+
+/**
+ * \def MBEDTLS_MD2_C
+ *
+ * Enable the MD2 hash algorithm.
+ *
+ * Module: library/md2.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD2-signed X.509 certs.
+ *
+ * \warning MD2 is considered a weak message digest and its use constitutes a
+ * security risk. If possible, we recommend avoiding dependencies on
+ * it, and considering stronger message digests instead.
+ *
+ */
+//#define MBEDTLS_MD2_C
+
+/**
+ * \def MBEDTLS_MD4_C
+ *
+ * Enable the MD4 hash algorithm.
+ *
+ * Module: library/md4.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD4-signed X.509 certs.
+ *
+ * \warning MD4 is considered a weak message digest and its use constitutes a
+ * security risk. If possible, we recommend avoiding dependencies on
+ * it, and considering stronger message digests instead.
+ *
+ */
+//#define MBEDTLS_MD4_C
+
+/**
+ * \def MBEDTLS_MD5_C
+ *
+ * Enable the MD5 hash algorithm.
+ *
+ * Module: library/md5.c
+ * Caller: library/md.c
+ * library/pem.c
+ * library/ssl_tls.c
+ *
+ * This module is required for SSL/TLS up to version 1.1, and for TLS 1.2
+ * depending on the handshake parameters. Further, it is used for checking
+ * MD5-signed certificates, and for PBKDF1 when decrypting PEM-encoded
+ * encrypted keys.
+ *
+ * \warning MD5 is considered a weak message digest and its use constitutes a
+ * security risk. If possible, we recommend avoiding dependencies on
+ * it, and considering stronger message digests instead.
+ *
+ */
+#define MBEDTLS_MD5_C
+
+/**
+ * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Enable the buffer allocator implementation that makes use of a (stack)
+ * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
+ * calls)
+ *
+ * Module: library/memory_buffer_alloc.c
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
+ *
+ * Enable this module to enable the buffer memory allocator.
+ */
+//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+
+/**
+ * \def MBEDTLS_NET_C
+ *
+ * Enable the TCP and UDP over IPv6/IPv4 networking routines.
+ *
+ * \note This module only works on POSIX/Unix (including Linux, BSD and OS X)
+ * and Windows. For other platforms, you'll want to disable it, and write your
+ * own networking callbacks to be passed to \c mbedtls_ssl_set_bio().
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/net_sockets.c
+ *
+ * This module provides networking routines.
+ */
+// #define MBEDTLS_NET_C
+
+/**
+ * \def MBEDTLS_OID_C
+ *
+ * Enable the OID database.
+ *
+ * Module: library/oid.c
+ * Caller: library/asn1write.c
+ * library/pkcs5.c
+ * library/pkparse.c
+ * library/pkwrite.c
+ * library/rsa.c
+ * library/x509.c
+ * library/x509_create.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * This modules translates between OIDs and internal values.
+ */
+#define MBEDTLS_OID_C
+
+/**
+ * \def MBEDTLS_PADLOCK_C
+ *
+ * Enable VIA Padlock support on x86.
+ *
+ * Module: library/padlock.c
+ * Caller: library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the VIA PadLock on x86.
+ */
+#define MBEDTLS_PADLOCK_C
+
+/**
+ * \def MBEDTLS_PEM_PARSE_C
+ *
+ * Enable PEM decoding / parsing.
+ *
+ * Module: library/pem.c
+ * Caller: library/dhm.c
+ * library/pkparse.c
+ * library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for decoding / parsing PEM files.
+ */
+#define MBEDTLS_PEM_PARSE_C
+
+/**
+ * \def MBEDTLS_PEM_WRITE_C
+ *
+ * Enable PEM encoding / writing.
+ *
+ * Module: library/pem.c
+ * Caller: library/pkwrite.c
+ * library/x509write_crt.c
+ * library/x509write_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for encoding / writing PEM files.
+ */
+#define MBEDTLS_PEM_WRITE_C
+
+/**
+ * \def MBEDTLS_PK_C
+ *
+ * Enable the generic public (asymetric) key layer.
+ *
+ * Module: library/pk.c
+ * Caller: library/ssl_tls.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
+ *
+ * Uncomment to enable generic public key wrappers.
+ */
+#define MBEDTLS_PK_C
+
+/**
+ * \def MBEDTLS_PK_PARSE_C
+ *
+ * Enable the generic public (asymetric) key parser.
+ *
+ * Module: library/pkparse.c
+ * Caller: library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key parse functions.
+ */
+#define MBEDTLS_PK_PARSE_C
+
+/**
+ * \def MBEDTLS_PK_WRITE_C
+ *
+ * Enable the generic public (asymetric) key writer.
+ *
+ * Module: library/pkwrite.c
+ * Caller: library/x509write.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key write functions.
+ */
+#define MBEDTLS_PK_WRITE_C
+
+/**
+ * \def MBEDTLS_PKCS5_C
+ *
+ * Enable PKCS#5 functions.
+ *
+ * Module: library/pkcs5.c
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the PKCS#5 functions.
+ */
+#define MBEDTLS_PKCS5_C
+
+/**
+ * \def MBEDTLS_PKCS11_C
+ *
+ * Enable wrapper for PKCS#11 smartcard support.
+ *
+ * Module: library/pkcs11.c
+ * Caller: library/pk.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * This module enables SSL/TLS PKCS #11 smartcard support.
+ * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
+ */
+//#define MBEDTLS_PKCS11_C
+
+/**
+ * \def MBEDTLS_PKCS12_C
+ *
+ * Enable PKCS#12 PBE functions.
+ * Adds algorithms for parsing PKCS#8 encrypted private keys
+ *
+ * Module: library/pkcs12.c
+ * Caller: library/pkparse.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * Can use: MBEDTLS_ARC4_C
+ *
+ * This module enables PKCS#12 functions.
+ */
+#define MBEDTLS_PKCS12_C
+
+/**
+ * \def MBEDTLS_PLATFORM_C
+ *
+ * Enable the platform abstraction layer that allows you to re-assign
+ * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
+ *
+ * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
+ * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
+ * above to be specified at runtime or compile time respectively.
+ *
+ * \note This abstraction layer must be enabled on Windows (including MSYS2)
+ * as other module rely on it for a fixed snprintf implementation.
+ *
+ * Module: library/platform.c
+ * Caller: Most other .c files
+ *
+ * This module enables abstraction of common (libc) functions.
+ */
+#define MBEDTLS_PLATFORM_C
+
+/**
+ * \def MBEDTLS_POLY1305_C
+ *
+ * Enable the Poly1305 MAC algorithm.
+ *
+ * Module: library/poly1305.c
+ * Caller: library/chachapoly.c
+ */
+#define MBEDTLS_POLY1305_C
+
+/**
+ * \def MBEDTLS_PSA_CRYPTO_C
+ *
+ * Enable the Platform Security Architecture cryptography API.
+ *
+ * \warning The PSA Crypto API is still beta status. While you're welcome to
+ * experiment using it, incompatible API changes are still possible, and some
+ * parts may not have reached the same quality as the rest of Mbed TLS yet.
+ *
+ * Module: crypto/library/psa_crypto.c
+ *
+ * Requires: MBEDTLS_CTR_DRBG_C, MBEDTLS_ENTROPY_C
+ *
+ */
+#define MBEDTLS_PSA_CRYPTO_C
+
+/**
+ * \def MBEDTLS_PSA_CRYPTO_STORAGE_C
+ *
+ * Enable the Platform Security Architecture persistent key storage.
+ *
+ * Module: crypto/library/psa_crypto_storage.c
+ *
+ * Requires: MBEDTLS_PSA_CRYPTO_C,
+ * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of
+ * the PSA ITS interface
+ */
+//#define MBEDTLS_PSA_CRYPTO_STORAGE_C
+
+/**
+ * \def MBEDTLS_PSA_ITS_FILE_C
+ *
+ * Enable the emulation of the Platform Security Architecture
+ * Internal Trusted Storage (PSA ITS) over files.
+ *
+ * Module: crypto/library/psa_its_file.c
+ *
+ * Requires: MBEDTLS_FS_IO
+ *
+ */
+//#define MBEDTLS_PSA_ITS_FILE_C
+
+/**
+ * \def MBEDTLS_RIPEMD160_C
+ *
+ * Enable the RIPEMD-160 hash algorithm.
+ *
+ * Module: library/ripemd160.c
+ * Caller: library/md.c
+ *
+ */
+#define MBEDTLS_RIPEMD160_C
+
+/**
+ * \def MBEDTLS_RSA_C
+ *
+ * Enable the RSA public-key cryptosystem.
+ *
+ * Module: library/rsa.c
+ * library/rsa_internal.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509.c
+ *
+ * This module is used by the following key exchanges:
+ * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
+ */
+#define MBEDTLS_RSA_C
+
+/**
+ * \def MBEDTLS_SHA1_C
+ *
+ * Enable the SHA1 cryptographic hash algorithm.
+ *
+ * Module: library/sha1.c
+ * Caller: library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ * library/x509write_crt.c
+ *
+ * This module is required for SSL/TLS up to version 1.1, for TLS 1.2
+ * depending on the handshake parameters, and for SHA1-signed certificates.
+ *
+ * \warning SHA-1 is considered a weak message digest and its use constitutes
+ * a security risk. If possible, we recommend avoiding dependencies
+ * on it, and considering stronger message digests instead.
+ *
+ */
+#define MBEDTLS_SHA1_C
+
+/**
+ * \def MBEDTLS_SHA256_C
+ *
+ * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
+ *
+ * Module: library/sha256.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * This module adds support for SHA-224 and SHA-256.
+ * This module is required for the SSL/TLS 1.2 PRF function.
+ */
+#define MBEDTLS_SHA256_C
+
+/**
+ * \def MBEDTLS_SHA512_C
+ *
+ * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
+ *
+ * Module: library/sha512.c
+ * Caller: library/entropy.c
+ * library/md.c
+ * library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * This module adds support for SHA-384 and SHA-512.
+ */
+#define MBEDTLS_SHA512_C
+
+/**
+ * \def MBEDTLS_SSL_CACHE_C
+ *
+ * Enable simple SSL cache implementation.
+ *
+ * Module: library/ssl_cache.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_CACHE_C
+ */
+#define MBEDTLS_SSL_CACHE_C
+
+/**
+ * \def MBEDTLS_SSL_COOKIE_C
+ *
+ * Enable basic implementation of DTLS cookies for hello verification.
+ *
+ * Module: library/ssl_cookie.c
+ * Caller:
+ */
+#define MBEDTLS_SSL_COOKIE_C
+
+/**
+ * \def MBEDTLS_SSL_TICKET_C
+ *
+ * Enable an implementation of TLS server-side callbacks for session tickets.
+ *
+ * Module: library/ssl_ticket.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_CIPHER_C
+ */
+#define MBEDTLS_SSL_TICKET_C
+
+/**
+ * \def MBEDTLS_SSL_CLI_C
+ *
+ * Enable the SSL/TLS client code.
+ *
+ * Module: library/ssl_cli.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS client support.
+ */
+#define MBEDTLS_SSL_CLI_C
+
+/**
+ * \def MBEDTLS_SSL_SRV_C
+ *
+ * Enable the SSL/TLS server code.
+ *
+ * Module: library/ssl_srv.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS server support.
+ */
+#define MBEDTLS_SSL_SRV_C
+
+/**
+ * \def MBEDTLS_SSL_TLS_C
+ *
+ * Enable the generic SSL/TLS code.
+ *
+ * Module: library/ssl_tls.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * and at least one of the MBEDTLS_SSL_PROTO_XXX defines
+ *
+ * This module is required for SSL/TLS.
+ */
+#define MBEDTLS_SSL_TLS_C
+
+/**
+ * \def MBEDTLS_THREADING_C
+ *
+ * Enable the threading abstraction layer.
+ * By default mbed TLS assumes it is used in a non-threaded environment or that
+ * contexts are not shared between threads. If you do intend to use contexts
+ * between threads, you will need to enable this layer to prevent race
+ * conditions. See also our Knowledge Base article about threading:
+ * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
+ *
+ * Module: library/threading.c
+ *
+ * This allows different threading implementations (self-implemented or
+ * provided).
+ *
+ * You will have to enable either MBEDTLS_THREADING_ALT or
+ * MBEDTLS_THREADING_PTHREAD.
+ *
+ * Enable this layer to allow use of mutexes within mbed TLS
+ */
+//#define MBEDTLS_THREADING_C
+
+/**
+ * \def MBEDTLS_TIMING_C
+ *
+ * Enable the semi-portable timing interface.
+ *
+ * \note The provided implementation only works on POSIX/Unix (including Linux,
+ * BSD and OS X) and Windows. On other platforms, you can either disable that
+ * module and provide your own implementations of the callbacks needed by
+ * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide
+ * your own implementation of the whole module by setting
+ * \c MBEDTLS_TIMING_ALT in the current file.
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module: library/timing.c
+ * Caller: library/havege.c
+ *
+ * This module is used by the HAVEGE random number generator.
+ */
+// #define MBEDTLS_TIMING_C
+
+/**
+ * \def MBEDTLS_VERSION_C
+ *
+ * Enable run-time version information.
+ *
+ * Module: library/version.c
+ *
+ * This module provides run-time version information.
+ */
+// #define MBEDTLS_VERSION_C
+
+/**
+ * \def MBEDTLS_X509_USE_C
+ *
+ * Enable X.509 core for using certificates.
+ *
+ * Module: library/x509.c
+ * Caller: library/x509_crl.c
+ * library/x509_crt.c
+ * library/x509_csr.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
+ * MBEDTLS_PK_PARSE_C
+ *
+ * This module is required for the X.509 parsing modules.
+ */
+#define MBEDTLS_X509_USE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Enable X.509 certificate parsing.
+ *
+ * Module: library/x509_crt.c
+ * Caller: library/ssl_cli.c
+ * library/ssl_srv.c
+ * library/ssl_tls.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 certificate parsing.
+ */
+#define MBEDTLS_X509_CRT_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CRL_PARSE_C
+ *
+ * Enable X.509 CRL parsing.
+ *
+ * Module: library/x509_crl.c
+ * Caller: library/x509_crt.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 CRL parsing.
+ */
+#define MBEDTLS_X509_CRL_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_PARSE_C
+ *
+ * Enable X.509 Certificate Signing Request (CSR) parsing.
+ *
+ * Module: library/x509_csr.c
+ * Caller: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is used for reading X.509 certificate request.
+ */
+#define MBEDTLS_X509_CSR_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CREATE_C
+ *
+ * Enable X.509 core for creating certificates.
+ *
+ * Module: library/x509_create.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
+ *
+ * This module is the basis for creating X.509 certificates and CSRs.
+ */
+#define MBEDTLS_X509_CREATE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_WRITE_C
+ *
+ * Enable creating X.509 certificates.
+ *
+ * Module: library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate creation.
+ */
+#define MBEDTLS_X509_CRT_WRITE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_WRITE_C
+ *
+ * Enable creating X.509 Certificate Signing Requests (CSR).
+ *
+ * Module: library/x509_csr_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate request writing.
+ */
+#define MBEDTLS_X509_CSR_WRITE_C
+
+/**
+ * \def MBEDTLS_XTEA_C
+ *
+ * Enable the XTEA block cipher.
+ *
+ * Module: library/xtea.c
+ * Caller:
+ */
+#define MBEDTLS_XTEA_C
+
+/* \} name SECTION: mbed TLS modules */
+
+/**
+ * \name SECTION: Module configuration options
+ *
+ * This section allows for the setting of module specific sizes and
+ * configuration options. The default values are already present in the
+ * relevant header files and should suffice for the regular use cases.
+ *
+ * Our advice is to enable options and change their values here
+ * only if you have a good reason and know the consequences.
+ *
+ * Please check the respective header file for documentation on these
+ * parameters (to prevent duplicate documentation).
+ * \{
+ */
+
+/* MPI / BIGNUM options */
+//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */
+//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */
+
+/* CTR_DRBG options */
+//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY /**< Use 128-bit key for CTR_DRBG - may reduce security (see ctr_drbg.h) */
+
+/* HMAC_DRBG options */
+//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */
+
+/* ECP options */
+//#define MBEDTLS_ECP_MAX_BITS 521 /**< Maximum bit size of groups */
+//#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< Maximum window size used */
+//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
+
+/* Entropy options */
+//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */
+//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */
+//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */
+
+/* Memory buffer allocator options */
+//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */
+
+/* Platform options */
+//#define MBEDTLS_PLATFORM_STD_MEM_HDR <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
+//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */
+/* Note: your snprintf must correctly zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */
+
+/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
+/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
+//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
+//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */
+/* Note: your snprintf must correctly zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf /**< Default vsnprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+
+/**
+ * \brief This macro is invoked by the library when an invalid parameter
+ * is detected that is only checked with #MBEDTLS_CHECK_PARAMS
+ * (see the documentation of that option for context).
+ *
+ * When you leave this undefined here, the library provides
+ * a default definition. If the macro #MBEDTLS_CHECK_PARAMS_ASSERT
+ * is defined, the default definition is `assert(cond)`,
+ * otherwise the default definition calls a function
+ * mbedtls_param_failed(). This function is declared in
+ * `platform_util.h` for the benefit of the library, but
+ * you need to define in your application.
+ *
+ * When you define this here, this replaces the default
+ * definition in platform_util.h (which no longer declares the
+ * function mbedtls_param_failed()) and it is your responsibility
+ * to make sure this macro expands to something suitable (in
+ * particular, that all the necessary declarations are visible
+ * from within the library - you can ensure that by providing
+ * them in this file next to the macro definition).
+ * If you define this macro to call `assert`, also define
+ * #MBEDTLS_CHECK_PARAMS_ASSERT so that library source files
+ * include `<assert.h>`.
+ *
+ * Note that you may define this macro to expand to nothing, in
+ * which case you don't have to worry about declarations or
+ * definitions. However, you will then be notified about invalid
+ * parameters only in non-void functions, and void function will
+ * just silently return early on invalid parameters, which
+ * partially negates the benefits of enabling
+ * #MBEDTLS_CHECK_PARAMS in the first place, so is discouraged.
+ *
+ * \param cond The expression that should evaluate to true, but doesn't.
+ */
+//#define MBEDTLS_PARAM_FAILED( cond ) assert( cond )
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */
+
+/* SSL options */
+
+/** \def MBEDTLS_SSL_MAX_CONTENT_LEN
+ *
+ * Maximum length (in bytes) of incoming and outgoing plaintext fragments.
+ *
+ * This determines the size of both the incoming and outgoing TLS I/O buffers
+ * in such a way that both are capable of holding the specified amount of
+ * plaintext data, regardless of the protection mechanism used.
+ *
+ * To configure incoming and outgoing I/O buffers separately, use
+ * #MBEDTLS_SSL_IN_CONTENT_LEN and #MBEDTLS_SSL_OUT_CONTENT_LEN,
+ * which overwrite the value set by this option.
+ *
+ * \note When using a value less than the default of 16KB on the client, it is
+ * recommended to use the Maximum Fragment Length (MFL) extension to
+ * inform the server about this limitation. On the server, there
+ * is no supported, standardized way of informing the client about
+ * restriction on the maximum size of incoming messages, and unless
+ * the limitation has been communicated by other means, it is recommended
+ * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN
+ * while keeping the default value of 16KB for the incoming buffer.
+ *
+ * Uncomment to set the maximum plaintext size of both
+ * incoming and outgoing I/O buffers.
+ */
+//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384
+
+/** \def MBEDTLS_SSL_IN_CONTENT_LEN
+ *
+ * Maximum length (in bytes) of incoming plaintext fragments.
+ *
+ * This determines the size of the incoming TLS I/O buffer in such a way
+ * that it is capable of holding the specified amount of plaintext data,
+ * regardless of the protection mechanism used.
+ *
+ * If this option is undefined, it inherits its value from
+ * #MBEDTLS_SSL_MAX_CONTENT_LEN.
+ *
+ * \note When using a value less than the default of 16KB on the client, it is
+ * recommended to use the Maximum Fragment Length (MFL) extension to
+ * inform the server about this limitation. On the server, there
+ * is no supported, standardized way of informing the client about
+ * restriction on the maximum size of incoming messages, and unless
+ * the limitation has been communicated by other means, it is recommended
+ * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN
+ * while keeping the default value of 16KB for the incoming buffer.
+ *
+ * Uncomment to set the maximum plaintext size of the incoming I/O buffer
+ * independently of the outgoing I/O buffer.
+ */
+//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384
+
+/** \def MBEDTLS_SSL_CID_IN_LEN_MAX
+ *
+ * The maximum length of CIDs used for incoming DTLS messages.
+ *
+ */
+//#define MBEDTLS_SSL_CID_IN_LEN_MAX 32
+
+/** \def MBEDTLS_SSL_CID_OUT_LEN_MAX
+ *
+ * The maximum length of CIDs used for outgoing DTLS messages.
+ *
+ */
+//#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32
+
+/** \def MBEDTLS_SSL_CID_PADDING_GRANULARITY
+ *
+ * This option controls the use of record plaintext padding
+ * when using the Connection ID extension in DTLS 1.2.
+ *
+ * The padding will always be chosen so that the length of the
+ * padded plaintext is a multiple of the value of this option.
+ *
+ * Note: A value of \c 1 means that no padding will be used
+ * for outgoing records.
+ *
+ * Note: On systems lacking division instructions,
+ * a power of two should be preferred.
+ *
+ */
+//#define MBEDTLS_SSL_CID_PADDING_GRANULARITY 16
+
+/** \def MBEDTLS_SSL_OUT_CONTENT_LEN
+ *
+ * Maximum length (in bytes) of outgoing plaintext fragments.
+ *
+ * This determines the size of the outgoing TLS I/O buffer in such a way
+ * that it is capable of holding the specified amount of plaintext data,
+ * regardless of the protection mechanism used.
+ *
+ * If this option undefined, it inherits its value from
+ * #MBEDTLS_SSL_MAX_CONTENT_LEN.
+ *
+ * It is possible to save RAM by setting a smaller outward buffer, while keeping
+ * the default inward 16384 byte buffer to conform to the TLS specification.
+ *
+ * The minimum required outward buffer size is determined by the handshake
+ * protocol's usage. Handshaking will fail if the outward buffer is too small.
+ * The specific size requirement depends on the configured ciphers and any
+ * certificate data which is sent during the handshake.
+ *
+ * Uncomment to set the maximum plaintext size of the outgoing I/O buffer
+ * independently of the incoming I/O buffer.
+ */
+//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384
+
+/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING
+ *
+ * Maximum number of heap-allocated bytes for the purpose of
+ * DTLS handshake message reassembly and future message buffering.
+ *
+ * This should be at least 9/8 * MBEDTLSSL_IN_CONTENT_LEN
+ * to account for a reassembled handshake message of maximum size,
+ * together with its reassembly bitmap.
+ *
+ * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default)
+ * should be sufficient for all practical situations as it allows
+ * to reassembly a large handshake message (such as a certificate)
+ * while buffering multiple smaller handshake messages.
+ *
+ */
+//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768
+
+//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */
+//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
+//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+
+/**
+ * Complete list of ciphersuites to use, in order of preference.
+ *
+ * \warning No dependency checking is done on that field! This option can only
+ * be used to restrict the set of available ciphersuites. It is your
+ * responsibility to make sure the needed modules are active.
+ *
+ * Use this to save a few hundred bytes of ROM (default ordering of all
+ * available ciphersuites) and a few to a few hundred bytes of RAM.
+ *
+ * The value below is only an example, not the default.
+ */
+//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+
+/* X509 options */
+//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */
+//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */
+
+/**
+ * Allow SHA-1 in the default TLS configuration for certificate signing.
+ * Without this build-time option, SHA-1 support must be activated explicitly
+ * through mbedtls_ssl_conf_cert_profile. Turning on this option is not
+ * recommended because of it is possible to generate SHA-1 collisions, however
+ * this may be safe for legacy infrastructure where additional controls apply.
+ *
+ * \warning SHA-1 is considered a weak message digest and its use constitutes
+ * a security risk. If possible, we recommend avoiding dependencies
+ * on it, and considering stronger message digests instead.
+ *
+ */
+//#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES
+
+/**
+ * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake
+ * signature and ciphersuite selection. Without this build-time option, SHA-1
+ * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes.
+ * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by
+ * default. At the time of writing, there is no practical attack on the use
+ * of SHA-1 in handshake signatures, hence this option is turned on by default
+ * to preserve compatibility with existing peers, but the general
+ * warning applies nonetheless:
+ *
+ * \warning SHA-1 is considered a weak message digest and its use constitutes
+ * a security risk. If possible, we recommend avoiding dependencies
+ * on it, and considering stronger message digests instead.
+ *
+ */
+#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
+
+/**
+ * Uncomment the macro to let mbed TLS use your alternate implementation of
+ * mbedtls_platform_zeroize(). This replaces the default implementation in
+ * platform_util.c.
+ *
+ * mbedtls_platform_zeroize() is a widely used function across the library to
+ * zero a block of memory. The implementation is expected to be secure in the
+ * sense that it has been written to prevent the compiler from removing calls
+ * to mbedtls_platform_zeroize() as part of redundant code elimination
+ * optimizations. However, it is difficult to guarantee that calls to
+ * mbedtls_platform_zeroize() will not be optimized by the compiler as older
+ * versions of the C language standards do not provide a secure implementation
+ * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to
+ * configure their own implementation of mbedtls_platform_zeroize(), for
+ * example by using directives specific to their compiler, features from newer
+ * C standards (e.g using memset_s() in C11) or calling a secure memset() from
+ * their system (e.g explicit_bzero() in BSD).
+ */
+//#define MBEDTLS_PLATFORM_ZEROIZE_ALT
+
+/**
+ * Uncomment the macro to let Mbed TLS use your alternate implementation of
+ * mbedtls_platform_gmtime_r(). This replaces the default implementation in
+ * platform_util.c.
+ *
+ * gmtime() is not a thread-safe function as defined in the C standard. The
+ * library will try to use safer implementations of this function, such as
+ * gmtime_r() when available. However, if Mbed TLS cannot identify the target
+ * system, the implementation of mbedtls_platform_gmtime_r() will default to
+ * using the standard gmtime(). In this case, calls from the library to
+ * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex
+ * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the
+ * library are also guarded with this mutex to avoid race conditions. However,
+ * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will
+ * unconditionally use the implementation for mbedtls_platform_gmtime_r()
+ * supplied at compile time.
+ */
+//#define MBEDTLS_PLATFORM_GMTIME_R_ALT
+
+/**
+ * Enable the verified implementations of ECDH primitives from Project Everest
+ * (currently only Curve25519). This feature changes the layout of ECDH
+ * contexts and therefore is a compatibility break for applications that access
+ * fields of a mbedtls_ecdh_context structure directly. See also
+ * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h.
+ */
+//#define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED
+
+/* \} name SECTION: Customisation configuration options */
+
+/* Target and application specific configurations
+ *
+ * Allow user to override any previous default.
+ *
+ */
+#if defined(MBEDTLS_USER_CONFIG_FILE)
+#include MBEDTLS_USER_CONFIG_FILE
+#endif
+
+#include "mbedtls/check_config.h"
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/boot/cypress/MCUBootApp/image_ec256_mbedtls.c b/boot/cypress/MCUBootApp/image_ec256_mbedtls.c
new file mode 100644
index 0000000..4053165
--- /dev/null
+++ b/boot/cypress/MCUBootApp/image_ec256_mbedtls.c
@@ -0,0 +1,166 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*******************************************************************************
+* \copyright
+*
+* (c) 2019, Cypress Semiconductor Corporation
+* or a subsidiary of Cypress Semiconductor Corporation. All rights
+* reserved.
+*
+* This software is a port of the open source MCUBoot project.
+*
+* This file was modified to fit PSoC6-based MCUBoot applications.
+*
+* Portions of this software, including source code, documentation and related
+* materials ("Software"), are owned by Cypress Semiconductor
+* Corporation or one of its subsidiaries ("Cypress") and is protected by
+* and subject to worldwide patent protection (United States and foreign),
+* United States copyright laws and international treaty provisions.
+* Therefore, you may use this Software only as provided in the license
+* agreement accompanying the software package from which you
+* obtained this Software ("EULA").
+*
+* If no EULA applies, Cypress hereby grants you a personal, non-
+* exclusive, non-transferable license to copy, modify, and compile the
+* Software source code solely for use in connection with Cypress's
+* integrated circuit products. Any reproduction, modification, translation,
+* compilation, or representation of this Software except as specified
+* above is prohibited without the express written permission of Cypress.
+*
+* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+* PARTICULAR PURPOSE. Cypress reserves the right to make
+* changes to the Software without notice. Cypress does not assume any
+* liability arising out of the application or use of the Software or any
+* product or circuit described in the Software. Cypress does not
+* authorize its products for use in any products where a malfunction or
+* failure of the Cypress product may reasonably be expected to result in
+* significant property damage, injury or death ("High Risk Product"). By
+* including Cypress's product in a High Risk Product, the manufacturer
+* of such system or application assumes all risk of such use and in doing
+* so agrees to indemnify Cypress against all liability.
+*
+********************************************************************************/
+
+#include "mcuboot_config/mcuboot_config.h"
+
+#ifdef MCUBOOT_SIGN_EC256
+
+#include "bootutil/sign_key.h"
+
+#ifdef MCUBOOT_USE_MBED_TLS
+
+#include "mbedtls/oid.h"
+#include "mbedtls/asn1.h"
+#include "mbedtls/ecdsa.h"
+
+#include "bootutil_priv.h"
+
+#include <string.h>
+
+/*
+ * Declaring these like this adds NULL termination.
+ */
+static const uint8_t ec_pubkey_oid[] = MBEDTLS_OID_EC_ALG_UNRESTRICTED;
+static const uint8_t ec_secp256r1_oid[] = MBEDTLS_OID_EC_GRP_SECP256R1;
+
+/*
+ * Parse the public key used for signing.
+ */
+static int
+bootutil_parse_eckey(mbedtls_ecdsa_context *ctx, uint8_t **p, uint8_t *end)
+{
+ size_t len;
+ mbedtls_asn1_buf alg;
+ mbedtls_asn1_buf param;
+
+ if (mbedtls_asn1_get_tag(p, end, &len,
+ MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) {
+ return -1;
+ }
+ end = *p + len;
+
+ if (mbedtls_asn1_get_alg(p, end, &alg, ¶m)) {
+ return -2;
+ }
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+ return -3;
+ }
+ if (param.len != sizeof(ec_secp256r1_oid) - 1||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+ return -4;
+ }
+
+ if (mbedtls_ecp_group_load(&ctx->grp, MBEDTLS_ECP_DP_SECP256R1)) {
+ return -5;
+ }
+
+ if (mbedtls_asn1_get_bitstring_null(p, end, &len)) {
+ return -6;
+ }
+ if (*p + len != end) {
+ return -7;
+ }
+
+ if (mbedtls_ecp_point_read_binary(&ctx->grp, &ctx->Q, *p, end - *p)) {
+ return -8;
+ }
+
+ if (mbedtls_ecp_check_pubkey(&ctx->grp, &ctx->Q)) {
+ return -9;
+ }
+ return 0;
+}
+
+int
+bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen, uint8_t key_id)
+{
+ int rc;
+ uint8_t *cp;
+ uint8_t *end;
+ mbedtls_ecdsa_context ctx;
+
+ mbedtls_ecdsa_init(&ctx);
+
+ cp = (uint8_t *)bootutil_keys[key_id].key;
+ end = cp + *bootutil_keys[key_id].len;
+
+ rc = bootutil_parse_eckey(&ctx, &cp, end);
+ if (rc) {
+ return -1;
+ }
+
+ while (sig[slen - 1] == '\0') {
+ slen--;
+ }
+
+ rc = mbedtls_ecdsa_read_signature(&ctx, hash, hlen, sig, slen);
+
+ mbedtls_ecdsa_free(&ctx);
+
+ return rc;
+}
+
+#endif /* MCUBOOT_USE_MBED_TLS */
+
+#endif /* MCUBOOT_SIGN_EC256 */
diff --git a/boot/cypress/MCUBootApp/keys.c b/boot/cypress/MCUBootApp/keys.c
new file mode 100644
index 0000000..db2bf07
--- /dev/null
+++ b/boot/cypress/MCUBootApp/keys.c
@@ -0,0 +1,165 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************
+*
+* This software is a port of the open source MCUBoot project.
+*
+* This file was modified to fit PSoC6-based MCUBoot applications.
+*
+* Portions of this software, including source code, documentation and related
+* materials ("Software"), are owned by Cypress Semiconductor
+* Corporation or one of its subsidiaries ("Cypress") and is protected by
+* and subject to worldwide patent protection (United States and foreign),
+* United States copyright laws and international treaty provisions.
+* Therefore, you may use this Software only as provided in the license
+* agreement accompanying the software package from which you
+* obtained this Software ("EULA").
+*
+* If no EULA applies, Cypress hereby grants you a personal, non-
+* exclusive, non-transferable license to copy, modify, and compile the
+* Software source code solely for use in connection with Cypress's
+* integrated circuit products. Any reproduction, modification, translation,
+* compilation, or representation of this Software except as specified
+* above is prohibited without the express written permission of Cypress.
+*
+* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+* PARTICULAR PURPOSE. Cypress reserves the right to make
+* changes to the Software without notice. Cypress does not assume any
+* liability arising out of the application or use of the Software or any
+* product or circuit described in the Software. Cypress does not
+* authorize its products for use in any products where a malfunction or
+* failure of the Cypress product may reasonably be expected to result in
+* significant property damage, injury or death ("High Risk Product"). By
+* including Cypress's product in a High Risk Product, the manufacturer
+* of such system or application assumes all risk of such use and in doing
+* so agrees to indemnify Cypress against all liability.
+*
+********************************************************************************/
+#include <bootutil/sign_key.h>
+#include <mcuboot_config/mcuboot_config.h>
+
+#if defined(MCUBOOT_SIGN_RSA)
+const unsigned char rsa_pub_key[] = {
+ 0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01, 0x00, 0xd1, 0x06, 0x08,
+ 0x1a, 0x18, 0x44, 0x2c, 0x18, 0xe8, 0xfb, 0xfd, 0xf7, 0x0d, 0xa3, 0x4f,
+ 0x1f, 0xbb, 0xee, 0x5e, 0xf9, 0xaa, 0xd2, 0x4b, 0x18, 0xd3, 0x5a, 0xe9,
+ 0x6d, 0x18, 0x80, 0x19, 0xf9, 0xf0, 0x9c, 0x34, 0x1b, 0xcb, 0xf3, 0xbc,
+ 0x74, 0xdb, 0x42, 0xe7, 0x8c, 0x7f, 0x10, 0x53, 0x7e, 0x43, 0x5e, 0x0d,
+ 0x57, 0x2c, 0x44, 0xd1, 0x67, 0x08, 0x0f, 0x0d, 0xbb, 0x5c, 0xee, 0xec,
+ 0xb3, 0x99, 0xdf, 0xe0, 0x4d, 0x84, 0x0b, 0xaa, 0x77, 0x41, 0x60, 0xed,
+ 0x15, 0x28, 0x49, 0xa7, 0x01, 0xb4, 0x3c, 0x10, 0xe6, 0x69, 0x8c, 0x2f,
+ 0x5f, 0xac, 0x41, 0x4d, 0x9e, 0x5c, 0x14, 0xdf, 0xf2, 0xf8, 0xcf, 0x3d,
+ 0x1e, 0x6f, 0xe7, 0x5b, 0xba, 0xb4, 0xa9, 0xc8, 0x88, 0x7e, 0x47, 0x3c,
+ 0x94, 0xc3, 0x77, 0x67, 0x54, 0x4b, 0xaa, 0x8d, 0x38, 0x35, 0xca, 0x62,
+ 0x61, 0x7e, 0xb7, 0xe1, 0x15, 0xdb, 0x77, 0x73, 0xd4, 0xbe, 0x7b, 0x72,
+ 0x21, 0x89, 0x69, 0x24, 0xfb, 0xf8, 0x65, 0x6e, 0x64, 0x3e, 0xc8, 0x0e,
+ 0xd7, 0x85, 0xd5, 0x5c, 0x4a, 0xe4, 0x53, 0x0d, 0x2f, 0xff, 0xb7, 0xfd,
+ 0xf3, 0x13, 0x39, 0x83, 0x3f, 0xa3, 0xae, 0xd2, 0x0f, 0xa7, 0x6a, 0x9d,
+ 0xf9, 0xfe, 0xb8, 0xce, 0xfa, 0x2a, 0xbe, 0xaf, 0xb8, 0xe0, 0xfa, 0x82,
+ 0x37, 0x54, 0xf4, 0x3e, 0xe1, 0x2b, 0xd0, 0xd3, 0x08, 0x58, 0x18, 0xf6,
+ 0x5e, 0x4c, 0xc8, 0x88, 0x81, 0x31, 0xad, 0x5f, 0xb0, 0x82, 0x17, 0xf2,
+ 0x8a, 0x69, 0x27, 0x23, 0xf3, 0xab, 0x87, 0x3e, 0x93, 0x1a, 0x1d, 0xfe,
+ 0xe8, 0xf8, 0x1a, 0x24, 0x66, 0x59, 0xf8, 0x1c, 0xab, 0xdc, 0xce, 0x68,
+ 0x1b, 0x66, 0x64, 0x35, 0xec, 0xfa, 0x0d, 0x11, 0x9d, 0xaf, 0x5c, 0x3a,
+ 0xa7, 0xd1, 0x67, 0xc6, 0x47, 0xef, 0xb1, 0x4b, 0x2c, 0x62, 0xe1, 0xd1,
+ 0xc9, 0x02, 0x03, 0x01, 0x00, 0x01
+};
+const unsigned int rsa_pub_key_len = 270;
+#elif defined(MCUBOOT_SIGN_EC)
+/* Format of PEM :
+ * -----BEGIN PUBLIC KEY-----
+ * base64encode(DER)
+ * -----END PUBLIC KEY----- */
+#if defined(ECC224_KEY_FILE)
+#include ECC224_KEY_FILE
+#else
+#warning "Used default ECC224 ecdsa_pub_key"
+/* It is OEM_PUB_KEY at this moment for debug purposes */
+/* Autogenerated by imgtool.py, do not edit. */
+const unsigned char ecdsa_pub_key[] = {
+ 0x30, 0x4e, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86,
+ 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, 0x2b,
+ 0x81, 0x04, 0x00, 0x21, 0x03, 0x3a, 0x00, 0x04,
+ 0xa5, 0x8b, 0x18, 0xa4, 0x60, 0x37, 0xf7, 0x0d,
+ 0x2b, 0x06, 0xba, 0x4b, 0x4c, 0xd7, 0x8d, 0xec,
+ 0x2a, 0x32, 0x5a, 0x0e, 0x52, 0xf4, 0x1b, 0x7c,
+ 0x99, 0xec, 0x68, 0x5d, 0x05, 0xc3, 0x6b, 0x7b,
+ 0x40, 0x9c, 0xaa, 0xac, 0x90, 0xf4, 0xfc, 0xbe,
+ 0x98, 0xe5, 0x3e, 0x86, 0x3d, 0x37, 0xbf, 0x45,
+ 0x78, 0x92, 0x27, 0xca, 0x69, 0xe6, 0xf2, 0xc5,
+};
+const unsigned int ecdsa_pub_key_len = 80;
+#endif
+#elif defined(MCUBOOT_SIGN_EC256)
+/* Format of PEM :
+ * -----BEGIN PUBLIC KEY-----
+ * base64encode(DER)
+ * -----END PUBLIC KEY----- */
+#if defined(ECC256_KEY_FILE)
+#include ECC256_KEY_FILE
+#else
+#warning "Used default ECC256 ecdsa_pub_key"
+/* It is OEM_PUB_KEY at this moment for debug purposes */
+const unsigned char ecdsa_pub_key[] = {
+ 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
+ 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a,
+ 0x86, 0x48, 0xce, 0x3d, 0x03, 0x01, 0x07, 0x03,
+ 0x42, 0x00, 0x04, 0xbd, 0x59, 0x9d, 0x15, 0xe0,
+ 0xff, 0x66, 0x12, 0x37, 0x28, 0xdf, 0x50, 0x38,
+ 0xb1, 0x9a, 0x73, 0x9b, 0xbd, 0xd1, 0xb3, 0x8a,
+ 0x6f, 0xd2, 0x70, 0xed, 0x7f, 0xdb, 0x57, 0x53,
+ 0xde, 0x9e, 0x77, 0x0f, 0x9c, 0x17, 0x22, 0x69,
+ 0xa6, 0x75, 0x48, 0x1f, 0xa4, 0xbc, 0x49, 0xe2,
+ 0x01, 0xe0, 0x5e, 0x3d, 0xec, 0xa8, 0xc1, 0xca,
+ 0xc5, 0x5c, 0xa2, 0xc6, 0xfd, 0xb0, 0x24, 0xb1,
+ 0x0a, 0x46, 0xf5,
+};
+const unsigned int ecdsa_pub_key_len = 91;
+#endif
+#else
+#warning "No public key available for given signing algorithm."
+#endif
+
+#if defined(MCUBOOT_SIGN_RSA) || \
+ defined(MCUBOOT_SIGN_EC) || \
+ defined(MCUBOOT_SIGN_EC256)
+const struct bootutil_key bootutil_keys[] = {
+#if defined(MCUBOOT_SIGN_RSA)
+ {
+ .key = rsa_pub_key,
+ .len = &rsa_pub_key_len,
+ },
+#elif defined(MCUBOOT_SIGN_EC) || \
+ defined(MCUBOOT_SIGN_EC256)
+ {
+ .key = ecdsa_pub_key,
+ .len = &ecdsa_pub_key_len,
+ },
+#else
+ {
+ .key = NULL,
+ .len = 0x00,
+ },
+#endif
+};
+const int bootutil_key_cnt = 1;
+#endif
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
new file mode 100644
index 0000000..96011b1
--- /dev/null
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -0,0 +1,111 @@
+################################################################################
+# \file libs.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe libraries needed for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+################################################################################
+# PDL library
+################################################################################
+PDL_VERSION = 121
+#
+CUR_LIBS_PATH = $(CURDIR)/libs
+MBEDTLS_PATH = $(CURDIR)/../../ext
+
+# Collect source files for PDL
+SOURCES_PDL := $(wildcard $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/source/*.c)
+
+# Collect source files for Retarget-io
+SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
+
+# PDL related include directories
+INCLUDE_DIRS_PDL := $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/include
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/devices/include/ip
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/devices/include
+INCLUDE_DIRS_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/cmsis/include
+
+# Retarget-io related include directories
+INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
+
+# core-libs related include directories
+INCLUDE_DIRS_CORE_LIB := $(CUR_LIBS_PATH)/core-lib/include
+
+# Collected source files for libraries
+SOURCES_LIBS := $(SOURCES_PDL)
+SOURCES_LIBS += $(SOURCES_PLATFORM)
+SOURCES_LIBS += $(SOURCES_RETARGET_IO)
+SOURCES_LIBS += $(SOURCES_HAL)
+
+# Collected include directories for libraries
+INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PLATFORM))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
+
+################################################################################
+# mbedTLS settings
+################################################################################
+# MbedTLS related include directories
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/mbedtls
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/crypto/include
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/crypto/include/mbedtls
+#
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS))
+# Collect source files for MbedTLS
+SOURCES_MBEDTLS := $(wildcard $(MBEDTLS_PATH)/mbedtls/library/*.c)
+SOURCES_MBEDTLS += $(wildcard $(MBEDTLS_PATH)/mbedtls/crypto/library/*.c)
+# Collected source files for libraries
+SOURCES_LIBS += $(SOURCES_MBEDTLS)
+## mbedTLS settings
+
+################################################################################
+# mbedTLS acceleration settings
+################################################################################
+ifeq ($(USE_CRYPTO_HW), 1)
+# cy-mbedtls-acceleration related include directories
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(CUR_LIBS_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO
+# Collect source files for MbedTLS acceleration
+SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(CUR_LIBS_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO/*.c)
+#
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
+# Collected source files for libraries
+SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
+endif
+## mbedTLS acceleration settings
+
+ASM_FILES_PDL :=
+ifeq ($(COMPILER), GCC_ARM)
+ASM_FILES_PDL += $(CUR_LIBS_PATH)/pdl/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+ASM_FILES_LIBS := $(ASM_FILES_PDL)
+ASM_FILES_LIBS += $(ASM_FILES_PLATFORM)
+
+# Add define for PDL version
+DEFINES_PDL += -DPDL_VERSION=$(PDL_VERSION)
+
+DEFINES_LIBS := $(DEFINES_PLATFORM)
+DEFINES_LIBS += $(DEFINES_PDL)
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
new file mode 100644
index 0000000..47f494a
--- /dev/null
+++ b/boot/cypress/MCUBootApp/main.c
@@ -0,0 +1,80 @@
+/***************************************************************************//**
+* \file main.c
+* \version 1.0
+********************************************************************************
+* \copyright
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/* Cypress pdl headers */
+#include "cy_pdl.h"
+#include "cyhal.h"
+#include "cy_retarget_io.h"
+#include "cy_result.h"
+
+#include "sysflash/sysflash.h"
+#include "flash_map_backend/flash_map_backend.h"
+
+#include "bootutil/image.h"
+#include "bootutil/bootutil.h"
+#include "bootutil/sign_key.h"
+
+#include "bootutil/bootutil_log.h"
+
+/* Define pins for UART debug output */
+
+#define CY_DEBUG_UART_TX (P5_1)
+#define CY_DEBUG_UART_RX (P5_0)
+
+static void do_boot(struct boot_rsp *rsp)
+{
+ uint32_t app_addr = 0;
+
+ app_addr = (rsp->br_image_off + rsp->br_hdr->ih_hdr_size);
+
+ BOOT_LOG_INF("Starting User Application on CM4 (wait)...");
+ Cy_SysLib_Delay(100);
+
+ cy_retarget_io_deinit();
+
+ Cy_SysEnableCM4(app_addr);
+
+ while (1)
+ {
+ __WFI() ;
+ }
+}
+
+int main(void)
+{
+ cy_rslt_t rc = !CY_RSLT_SUCCESS;
+ struct boot_rsp rsp ;
+
+ /* enable interrupts */
+ __enable_irq();
+
+ /* Initialize retarget-io to use the debug UART port */
+ cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
+
+ BOOT_LOG_INF("MCUBoot Bootloader Started");
+
+ if (boot_go(&rsp) == 0) {
+ BOOT_LOG_INF("User Application validated successfully");
+ do_boot(&rsp);
+ } else
+ BOOT_LOG_INF("MCUBoot Bootloader found none of bootable images") ;
+
+ return 0;
+}
diff --git a/boot/cypress/MCUBootApp/os/os.h b/boot/cypress/MCUBootApp/os/os.h
new file mode 100644
index 0000000..8d581ca
--- /dev/null
+++ b/boot/cypress/MCUBootApp/os/os.h
@@ -0,0 +1,18 @@
+/***************************************************************************//**
+* \file os.h
+* \version 1.0
+*
+* \brief
+* Objective:
+* Heap init prototype
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+void os_heap_init(void);
diff --git a/boot/cypress/MCUBootApp/os/os_heap.h b/boot/cypress/MCUBootApp/os/os_heap.h
new file mode 100644
index 0000000..0ea954c
--- /dev/null
+++ b/boot/cypress/MCUBootApp/os/os_heap.h
@@ -0,0 +1,37 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_OS_HEAP_
+#define H_OS_HEAP_
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void *os_malloc(size_t size);
+void os_free(void *mem);
+void *os_realloc(void *ptr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/boot/cypress/MCUBootApp/os/os_malloc.h b/boot/cypress/MCUBootApp/os/os_malloc.h
new file mode 100644
index 0000000..249b12c
--- /dev/null
+++ b/boot/cypress/MCUBootApp/os/os_malloc.h
@@ -0,0 +1,42 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_OS_MALLOC_
+#define H_OS_MALLOC_
+
+#include "os/os_heap.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef malloc
+#define malloc os_malloc
+
+#undef free
+#define free os_free
+
+#undef realloc
+#define realloc os_realloc
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/boot/cypress/MCUBootApp/platforms.mk b/boot/cypress/MCUBootApp/platforms.mk
new file mode 100644
index 0000000..fdd5a81
--- /dev/null
+++ b/boot/cypress/MCUBootApp/platforms.mk
@@ -0,0 +1,102 @@
+################################################################################
+# \file targets.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Target platform MCUBootApp is built for. PSOC_064_2M is set by default# Supported:
+# - PSOC_062_2M
+
+# default PLATFORM
+PLATFORM ?= PSOC_062_2M
+#
+PLATFORMS := PSOC_062_2M
+
+# For which core this application is built
+CORE := CM0P
+
+# Set paths for related folders
+CUR_LIBS_PATH := $(CURDIR)/libs
+PLATFORM_PATH := $(CURDIR)/platforms
+
+# MCU device selection, based on target device.
+# Default chips are used for supported platforms
+# This can be redefined in case of other chip usage
+ifeq ($(PLATFORM), PSOC_062_2M)
+DEVICE ?= CY8C624ABZI-D44
+PLATFORM_SUFFIX := 02
+endif
+
+# Additional components supported by the target
+COMPONENTS+=COMPONENT_BSP_DESIGN_MODUS
+# Use CyHAL
+DEFINES:=CY_USING_HAL
+
+# Collect C source files for PLATFORM BSP
+SOURCES_PLATFORM += $(wildcard $(PLATFORM_PATH)/*.c)
+SOURCES_PLATFORM += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/*.c)
+SOURCES_PLATFORM += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/triggers/*.c)
+SOURCES_PLATFORM += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/pin_packages/*.c)
+
+SOURCES_PLATFORM := $(filter-out %/system_psoc6_cm4.c, $(SOURCES_PLATFORM))
+
+# Collect dirrectories containing headers for PLATFORM BSP
+INCLUDE_DIRS_PLATFORM := $(PLATFORM_PATH)
+INCLUDE_DIRS_PLATFORM += $(CUR_LIBS_PATH)/psoc6hal/include
+INCLUDE_DIRS_PLATFORM += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
+INCLUDE_DIRS_PLATFORM += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
+# Collect Assembler files for PLATFORM BSP
+# Include _01_, _02_ or _03_ PLATFORM_SUFFIX depending on device family.
+STARTUP_FILE := $(PLATFORM_PATH)/$(PLATFORM)/$(CORE)/$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_cm0plus
+
+ifeq ($(COMPILER), GCC_ARM)
+ ASM_FILES_PLATFORM := $(STARTUP_FILE).S
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+# Add device name from BSP makefile to defines
+DEFINES += $(DEVICE)
+DEFINES += $(COMPONENTS)
+DEFINES += $(PLATFORM)
+
+# Get defines from BSP makefile and convert it to regular -DMY_NAME style
+ifneq ($(DEFINES),)
+ DEFINES_PLATFORM :=$(addprefix -D, $(subst -,_,$(DEFINES)))
+endif
+
+ifeq ($(COMPILER), GCC_ARM)
+LINKER_SCRIPT ?= $(PLATFORM_PATH)/$(PLATFORM)/$(CORE)/$(COMPILER)/*_cm0plus.ld
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+ifeq ($(MAKEINFO) , 1)
+$(info ==============================================================================)
+$(info = BSP files =)
+$(info ==============================================================================)
+$(info $(SOURCES_PLATFORM))
+$(info $(ASM_FILES_PLATFORM))
+endif
+
+# TODO: include appropriate BSP linker(s)
+# TODO: include appropriate BSP precompiled
diff --git a/boot/cypress/MCUBootApp/sysflash/sysflash.h b/boot/cypress/MCUBootApp/sysflash/sysflash.h
new file mode 100644
index 0000000..2a905ee
--- /dev/null
+++ b/boot/cypress/MCUBootApp/sysflash/sysflash.h
@@ -0,0 +1,75 @@
+/* Manual version of auto-generated version. */
+
+#ifndef __SYSFLASH_H__
+#define __SYSFLASH_H__
+
+#define FLASH_DEVICE_INTERNAL_FLASH (0x7F)
+
+#define FLASH_AREA_BOOTLOADER 0
+#define FLASH_AREA_IMAGE_0 1
+#define FLASH_AREA_IMAGE_1 2
+#define FLASH_AREA_IMAGE_SCRATCH 3
+#define FLASH_AREA_IMAGE_2 5
+#define FLASH_AREA_IMAGE_3 6
+
+#define CY_FLASH_ALIGN (CY_FLASH_SIZEOF_ROW)
+#define CY_FLASH_DEVICE_BASE (CY_FLASH_BASE)
+
+#ifndef CY_BOOT_SCRATCH_SIZE
+#define CY_BOOT_SCRATCH_SIZE (0x1000)
+#endif
+
+#ifndef CY_BOOT_BOOTLOADER_SIZE
+#define CY_BOOT_BOOTLOADER_SIZE (0x18000)
+#endif
+
+#ifndef CY_BOOT_PRIMARY_1_SIZE
+#define CY_BOOT_PRIMARY_1_SIZE (0x10000)
+#endif
+
+#ifndef CY_BOOT_SECONDARY_1_SIZE
+#define CY_BOOT_SECONDARY_1_SIZE (0x10000)
+#endif
+
+#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
+#ifndef CY_BOOT_PRIMARY_2_SIZE
+#define CY_BOOT_PRIMARY_2_SIZE (0x10000)
+#endif
+
+#ifndef CY_BOOT_SECONDARY_2_SIZE
+#define CY_BOOT_SECONDARY_2_SIZE (0x10000)
+#endif
+#endif
+
+#if (MCUBOOT_IMAGE_NUMBER == 1)
+#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
+ FLASH_AREA_IMAGE_0 : \
+ FLASH_AREA_IMAGE_0)
+#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
+ FLASH_AREA_IMAGE_1 : \
+ FLASH_AREA_IMAGE_1)
+
+#elif (MCUBOOT_IMAGE_NUMBER == 2)
+
+#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
+ FLASH_AREA_IMAGE_0 : \
+ ((x) == 1) ? \
+ FLASH_AREA_IMAGE_2 : \
+ 255)
+#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
+ FLASH_AREA_IMAGE_1 : \
+ ((x) == 1) ? \
+ FLASH_AREA_IMAGE_3 : \
+ 255)
+
+#else
+#warning "Image slot and flash area mapping is not defined"
+#endif
+#define CY_IMG_HDR_SIZE 0x400
+
+#ifndef CY_FLASH_MAP_EXT_DESC
+/* Uncomment in case you want to use separately defined table of flash area descriptors */
+/* #define CY_FLASH_MAP_EXT_DESC */
+#endif
+
+#endif /* __SYSFLASH_H__ */
diff --git a/boot/cypress/MCUBootApp/toolchains.mk b/boot/cypress/MCUBootApp/toolchains.mk
new file mode 100644
index 0000000..d250931
--- /dev/null
+++ b/boot/cypress/MCUBootApp/toolchains.mk
@@ -0,0 +1,141 @@
+################################################################################
+# \file toolchains.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported toolchains for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# Compilers
+GCC_ARM := 1
+IAR := 2
+ARM := 3
+OTHER := 4
+
+ifeq ($(MAKEINFO), 1)
+$(info $(COMPILER))
+endif
+# Detect host OS to make resolving compiler pathes easier
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S), Darwin)
+ HOST_OS = osx
+else
+ ifeq ($(UNAME_S), Linux)
+ HOST_OS = linux
+ else
+ HOST_OS = win
+ endif
+endif
+
+# Path to the compiler installation
+# NOTE: Absolute pathes for now for the sake of development
+ifeq ($(HOST_OS), win)
+ ifeq ($(COMPILER), GCC_ARM)
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox_1.0/tools/gcc-7.2.1-1.0
+ MY_TOOLCHAIN_PATH:=$(subst \,/,$(TOOLCHAIN_PATH))
+ TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
+ GCC_PATH := $(TOOLCHAIN_PATH)
+ # executables
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+
+ else ifeq ($(COMPILER), IAR)
+ IAR_PATH := C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0/arm
+ # executables
+ CC := "$(IAR_PATH)/bin/iccarm.exe"
+ AS := "$(IAR_PATH)/bin/iasmarm.exe"
+ LD := "$(IAR_PATH)/bin/ilinkarm.exe"
+ endif
+
+else ifeq ($(HOST_OS), osx)
+ TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
+ GCC_PATH := $(TOOLCHAIN_PATH)
+
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+
+else ifeq ($(HOST_OS), linux)
+ TOOLCHAIN_PATH ?= /usr/bin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc
+ GCC_PATH := $(TOOLCHAIN_PATH)
+ # executables
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+endif
+
+PDL_ELFTOOL := "hal/tools/$(HOST_OS)/elf/cymcuelftool"
+
+# Set executable names for compilers
+ifeq ($(COMPILER), GCC_ARM)
+ CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
+ LD := $(CC)
+else
+ CC := "$(IAR_PATH)/bin/iccarm.exe"
+ AS := "$(IAR_PATH)/bin/iasmarm.exe"
+ LD := "$(IAR_PATH)/bin/ilinkarm.exe"
+endif
+
+OBJDUMP := "$(GCC_PATH)/bin/arm-none-eabi-objdump"
+OBJCOPY := "$(GCC_PATH)/bin/arm-none-eabi-objcopy"
+
+# Set flags for toolchain executables
+
+ifeq ($(COMPILER), GCC_ARM)
+ # set build-in compiler flags
+ CFLAGS_COMMON := -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -fno-stack-protector -ffunction-sections -fdata-sections -ffat-lto-objects -fstrict-aliasing -g -Wall -Wextra
+ ifeq ($(BUILDCFG), Debug)
+ CFLAGS_COMMON += -Og -g3
+ else ifeq ($(BUILDCFG), Release)
+ CFLAGS_COMMON += -Os -g
+ else
+$(error BUILDCFG : '$(BUILDCFG)' is not supported)
+ endif
+ # add defines and includes
+ CFLAGS := $(CFLAGS_COMMON) $(INCLUDES)
+ CC_DEPEND = -MD -MP -MF
+
+ LDFLAGS_COMMON := -mcpu=cortex-m0plus -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -L "$(GCC_PATH)/lib/gcc/arm-none-eabi/7.2.1/thumb/v6-m" -ffat-lto-objects -g --enable-objc-gc
+ ifeq ($(BUILDCFG), Debug)
+ LDFLAGS_COMMON += -Og
+ else ifeq ($(BUILDCFG), Release)
+ LDFLAGS_COMMON += -Os
+ else
+$(error BUILDCFG : '$(BUILDCFG)' is not supported)
+ endif
+ LDFLAGS_NANO := -L "$(GCC_PATH)/arm-none-eabi/lib/thumb/v6-m"
+ # TODO: check .map name
+ LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO)
+
+else ifeq ($(COMPILER), IAR)
+
+ CFLAGS := --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "$(IAR_PATH)\INC\c\DLib_Config_Normal.h"
+ CFLAGS += -Ohz --silent
+# CFLAGS += $(DEFINES) $(INCLUDES)
+ CFLAGS += $(INCLUDES)
+ CC_DEPEND = --dependencies
+
+ AS_FLAGS := -s+ "-M<>" -w+ -r --cpu Cortex-M0+ --fpu None -S
+
+ LINKER_SCRIPT := $(CHIP_SERIES).icf
+
+ #options to extend stack analize: --log call_graph --log_file $(OUT)/stack_usage_$(SUFFIX).txt
+ LDFLAGS_STACK_USAGE := --stack_usage_control $(STACK_CONTROL_FILE) --diag_suppress=Ls015 --diag_suppress=Ls016
+ LDFLAGS_COMMON := --vfe --text_out locale --silent --inline --merge_duplicate_sections
+ LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_STACK_USAGE) --config $(LINKER_SCRIPT) --map $(OUT_APP)/$(APP_NAME).map --entry Cy_FB_ResetHandler --no_exceptions
+endif
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
new file mode 100644
index 0000000..103be53
--- /dev/null
+++ b/boot/cypress/Makefile
@@ -0,0 +1,209 @@
+################################################################################
+# \file Makefile
+# \version 1.0
+#
+# \brief
+# Main Makefile for building MCUBoot application for Cypress target.
+#
+################################################################################
+# \copyright
+# Copyright 2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+# minimum Python 3.7 is required
+# Python path definition
+ifeq ($(OS),Windows_NT)
+PYTHON_PATH?=python
+else
+PYTHON_PATH?=python3
+endif
+
+################################################################################
+# Main settings
+################################################################################
+
+# Defines whether or not show verbose build output
+MAKEINFO ?= 1
+# Application name by default
+APP_NAME ?= MCUBootApp
+# Weather or now execute post build script after build - set to 0 for CI
+POST_BUILD ?= 1
+
+SIGN_KEY_FILE ?= cypress-test-ec-p256
+
+# set this variable to a path, where cysecuretools python package is installed
+# use command `python -m pip show cysecuretools` to find out this path
+# or rely on scripts that automates this action, bit not work for virtual envs
+CY_SEC_TOOLS_PATH ?= $(shell $(PYTHON_PATH) $(CURDIR)/scripts/find_cysectools.py)
+
+BUILDCFG ?= Debug
+
+# Set of supported applications
+APPS := MCUBootApp BlinkyApp CypressBootloader SecureBlinkyApp
+
+HEADER_OFFSET ?= 0
+
+ifneq ($(filter $(APP_NAME), $(APPS)),)
+include ./$(APP_NAME)/$(APP_NAME).mk
+else
+$(error Not supported application: '$(APP_NAME)')
+endif
+
+ASM_FILES := $(ASM_FILES_APP)
+ASM_FILES += $(ASM_FILES_LIBS)
+
+C_FILES := $(SOURCES_APP)
+C_FILES += $(SOURCES_LIBS)
+
+INCLUDE_DIRS := $(INCLUDE_DIRS_APP)
+INCLUDE_DIRS += $(INCLUDES_DIRS_MCUBOOT)
+INCLUDE_DIRS += $(INCLUDE_DIRS_LIBS)
+
+#INCLUDE_FILES := $(INCLUDE_FILES_APP)
+
+#INCLUDES := $(addprefix -include , $(INCLUDE_FILES))
+
+O_FILES := $(notdir $(C_FILES:.c=.o)) $(addsuffix .o, $(notdir $(basename $(ASM_FILES))))
+
+DEFINES := $(DEFINES_APP)
+DEFINES += $(DEFINES_LIBS)
+AS_FLAGS += $(DEFINES)
+
+ifeq ($(MAKEINFO), 1)
+$(info ==============================================================================)
+$(info = Directories to look for header files: =)
+$(info ==============================================================================)
+$(info $(INCLUDE_DIRS))
+
+$(info ==============================================================================)
+$(info = Collected Defines string: =)
+$(info ==============================================================================)
+$(info $(DEFINES))
+endif
+
+# updating CFLAGS at this point as DEFINES are completed
+CFLAGS += $(DEFINES)
+
+VPATH = $(dir $(C_FILES) $(ASM_FILES))
+
+#
+# STDE: For cygwin, adjust paths for compiler
+#
+MY_FILES := $(subst /cygdrive/c,c:,$(C_FILES))
+#$(info MY_FILES $(MY_FILES))
+C_FILES=$(MY_FILES)
+
+MY_DIRS := $(subst /cygdrive/c,c:,$(INCLUDE_DIRS))
+#$(info MY_DIRS $(MY_DIRS))
+INCLUDE_DIRS=$(MY_DIRS)
+
+MY_ASM_FILES := $(subst /cygdrive/c,c:,$(ASM_FILES))
+#$(info MY_ASM_FILES $(MY_ASM_FILES))
+ASM_FILES=$(MY_ASM_FILES)
+
+MY_LDFLAGS := $(subst /cygdrive/c,c:,$(LDFLAGS))
+#$(info MY_LDFLAGS $(MY_LDFLAGS))
+LDFLAGS=$(MY_LDFLAGS)
+
+# Default name pattern for output files
+# may be modified in %Application%.mk file
+OUT_FILE_NAME ?= $(OUT_APP)/$(APP_NAME)
+
+OUT_OBJ := $(OUT_CFG)/obj
+OUT_APP := $(OUT_CFG)
+
+.PHONY: all app build clean pre_build post_build
+
+all: clean app
+
+app:
+ @`mkdir -p ./$(OUT)`
+ @`mkdir -p ./$(OUT_TARGET)`
+ @`mkdir -p ./$(OUT_CFG)`
+ @`mkdir -p ./$(OUT_OBJ)`
+ $(MAKE) pre_build
+ $(MAKE) build -j8
+ $(MAKE) post_build
+
+build: $(OUT_APP)/$(APP_NAME).hex
+ $(GCC_PATH)/bin/arm-none-eabi-objdump $(OUT_APP)/$(APP_NAME).hex -s > $(OUT_APP)/$(APP_NAME).lst
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -h $(OUT_APP)/$(APP_NAME).elf
+ $(GCC_PATH)/bin/arm-none-eabi-size --format=SysV $(OUT_APP)/$(APP_NAME).elf
+
+$(OUT_APP)/$(APP_NAME).hex: $(OUT_APP)/$(APP_NAME).elf
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-addresses=$(HEADER_OFFSET) -O ihex $(OUT_APP)/$(APP_NAME).elf $(OUT_APP)/$(APP_NAME).hex
+
+$(OUT_APP)/$(APP_NAME).elf: $(addprefix $(OUT_OBJ)/, $(O_FILES))
+ @echo "LD $@"
+ifeq ($(MAKEINFO), 1)
+ @echo $(LD) $(O_FILES) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
+endif
+ @$(LD) $(addprefix $(OUT_OBJ)/, $(O_FILES)) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
+
+
+$(OUT_OBJ)/%.o: %.c
+ @echo "CC $<"
+ifeq ($(MAKEINFO), 1)
+ @echo $(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+endif
+ @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+ifeq ($(MAKEINFO), 1)
+ @echo
+endif
+
+$(OUT_OBJ)/%.o: %.S
+ @echo "AS $<"
+ifeq ($(COMPILER), GCC_ARM)
+ifeq ($(MAKEINFO), 1)
+ @echo @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+endif
+ @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+else
+ @echo $(AS) $< -o $@ $(AS_FLAGS)
+ @$(AS) $< -o $@ $(AS_FLAGS)
+endif
+ifeq ($(MAKEINFO), 1)
+ @echo
+endif
+
+clean:
+ @echo "Cleanup out directory..."
+ rm -rf $(OUT_TARGET)/$(BUILDCFG)
+
+clean_boot:
+ @echo "Cleanup out BOOT directory of $(APP_NAME)..."
+ rm -rf $(OUT_TARGET)/$(BUILDCFG)/boot
+
+clean_upgrade:
+ @echo "Cleanup out UPGRADE directory of $(APP_NAME)..."
+ rm -rf $(OUT_TARGET)/$(BUILDCFG)/upgrade
+
+run_cppcheck:
+ @echo "Performing static code analysis with Cppcheck tool..."
+ ../../scripts/cpp_check.sh ../../scripts/cpp_check.dat
+
+gen_key_ecc256:
+ @echo Generate ECC256 keys: $(SIGN_KEY_FILE).pem and $(SIGN_KEY_FILE).pub
+ ../../scripts/imgtool.py keygen -k keys/$(SIGN_KEY_FILE).pem -t ecdsa-p256
+ ../../scripts/imgtool.py getpub -k keys/$(SIGN_KEY_FILE).pem > keys/$(SIGN_KEY_FILE).pub
+
+ifeq ($(MAKEINFO) , 1)
+$(info ASM_FILES: $(ASM_FILES))
+$(info C_FILES: $(C_FILES))
+$(info INCLUDE_DIRS: $(INCLUDE_DIRS))
+$(info DEFINES: $(DEFINES))
+$(info CC: $(CC))
+endif
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
new file mode 100644
index 0000000..50a3403
--- /dev/null
+++ b/boot/cypress/README.md
@@ -0,0 +1,77 @@
+### Port of MCUBoot library to be used with Cypress targets
+
+**Solution Description**
+
+Given solution demonstrates operation of MCUBoot on Cypress' PSoC6 device.
+
+There are four applications implemented:
+* MCUBootApp - PSoC6 MCUBoot-based bootloading application;
+* CypressBootloader - PSoC6 MCUBoot-based Cypress' Secure Boot application;
+* SecureBlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE, running on CM0p and playing a role of SPE;
+* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
+
+The default flash map for MCUBootApp implemented is next:
+
+* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
+* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
+* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
+* [0x10038000, 0x10039000] - scratch area;
+
+The flash map is defined through sysflash.h and cy_flash_map.c.
+
+MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses completely SW implementation of cryptographic functions based on mbedTLS Library.
+
+**Downloading Solution's Assets**
+
+There is a set assets required:
+
+* MCUBooot Library (root repository)
+* PSoC6 BSP Library
+* PSoC6 Peripheral Drivers Library (PDL)
+* mbedTLS Cryptographic Library
+
+Those are represented as submodules.
+
+To retrieve source code with subsequent submodules pull:
+
+ git clone --recursive http://git-ore.aus.cypress.com/repo/cy_mcuboot_project/cy_mcuboot.git
+
+Submodules can also be updated and initialized separately:
+
+ cd cy_mcuboot
+ git submodule update --init --recursive
+
+
+
+**Building Solution**
+
+This folder contains make files infrastructure for building both MCUBoot Bootloader, CypressBootloader and sample SecureBlinkyApp and BlinkyApp applications used for Bootloader demo functionality.
+
+Instructions on how to build and upload Bootloader and sample image are located in `Readme.md` files in corresponding folders.
+
+Root directory for build is **boot/cypress.**
+
+**Currently supported platforms:**
+
+* PSOC_062_2M - for MCUBoot, BlinkyApp;
+
+* PSOC_064_2M, PSOC_064_1M, PSOC_064_512K - for CypressBootloader, SecureBlinkyApp;
+
+* PSOC_062_2M, PSOC_064_2M, PSOC_064_1M, PSOC_064_512K - for BlinkyApp;
+
+**Build environment troubleshooting:**
+
+Following CLI / IDE are supported for project build:
+
+* Cygwin on Windows systems
+* unix style sheels on *nix systems
+* Eclipse / ModusToolbox ("makefile project from existing source")
+
+*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
+
+*Python/Python3* - make sure you have correct path referenced in `PATH`;
+
+*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
+
+This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+
diff --git a/boot/cypress/cy_flash_pal/cy_flash_map.c b/boot/cypress/cy_flash_pal/cy_flash_map.c
new file mode 100644
index 0000000..2b51795
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/cy_flash_map.c
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifdef MCUBOOT_HAVE_ASSERT_H
+#include "mcuboot_config/mcuboot_assert.h"
+#else
+#include <assert.h>
+#endif
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#include "flash_map_backend/flash_map_backend.h"
+#include <sysflash/sysflash.h>
+#include "cy_flash_psoc6.h"
+
+#include "bootutil/bootutil_log.h"
+
+#include "cy_pdl.h"
+
+/*
+ * For now, we only support one flash device.
+ *
+ * Pick a random device ID for it that's unlikely to collide with
+ * anything "real".
+ */
+#define FLASH_DEVICE_ID 111
+#define FLASH_MAP_ENTRY_MAGIC 0xd00dbeef
+
+#define FLASH_AREA_IMAGE_SECTOR_SIZE FLASH_AREA_IMAGE_SCRATCH_SIZE
+
+#ifndef CY_BOOTLOADER_START_ADDRESS
+#define CY_BOOTLOADER_START_ADDRESS (0x10000000)
+#endif
+
+#ifndef CY_BOOT_INTERNAL_FLASH_ERASE_VALUE
+/* This is the value of internal flash bytes after an erase */
+#define CY_BOOT_INTERNAL_FLASH_ERASE_VALUE (0x00)
+#endif
+
+#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
+/* This is the value of external flash bytes after an erase */
+#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xff)
+#endif
+
+#ifdef CY_FLASH_MAP_EXT_DESC
+/* Nothing to be there when external FlashMap Descriptors are used */
+#else
+static struct flash_area bootloader =
+{
+ .fa_id = FLASH_AREA_BOOTLOADER,
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+ .fa_off = CY_BOOTLOADER_START_ADDRESS,
+ .fa_size = CY_BOOT_BOOTLOADER_SIZE
+};
+
+static struct flash_area primary_1 =
+{
+ .fa_id = FLASH_AREA_IMAGE_PRIMARY(0),
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+ .fa_off = CY_FLASH_BASE + CY_BOOT_BOOTLOADER_SIZE,
+ .fa_size = CY_BOOT_PRIMARY_1_SIZE
+};
+
+static struct flash_area secondary_1 =
+{
+ .fa_id = FLASH_AREA_IMAGE_SECONDARY(0),
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+ .fa_off = CY_FLASH_BASE +\
+ CY_BOOT_BOOTLOADER_SIZE +\
+ CY_BOOT_PRIMARY_1_SIZE,
+ .fa_size = CY_BOOT_SECONDARY_1_SIZE
+};
+
+#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
+static struct flash_area primary_2 =
+{
+ .fa_id = FLASH_AREA_IMAGE_PRIMARY(1),
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+ .fa_off = CY_FLASH_BASE +\
+ CY_BOOT_BOOTLOADER_SIZE +\
+ CY_BOOT_PRIMARY_1_SIZE +\
+ CY_BOOT_SECONDARY_1_SIZE,
+ .fa_size = CY_BOOT_PRIMARY_2_SIZE
+};
+
+static struct flash_area secondary_2 =
+{
+ .fa_id = FLASH_AREA_IMAGE_SECONDARY(1),
+ /* TODO: it is for external flash memory
+ .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX), */
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+ .fa_off = CY_FLASH_BASE +\
+ CY_BOOT_BOOTLOADER_SIZE +\
+ CY_BOOT_PRIMARY_1_SIZE +\
+ CY_BOOT_SECONDARY_1_SIZE +\
+ CY_BOOT_PRIMARY_2_SIZE,
+ .fa_size = CY_BOOT_SECONDARY_2_SIZE
+};
+#endif
+static struct flash_area scratch =
+{
+ .fa_id = FLASH_AREA_IMAGE_SCRATCH,
+ .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
+#if (MCUBOOT_IMAGE_NUMBER == 1) /* if single-image */
+ .fa_off = CY_FLASH_BASE +\
+ CY_BOOT_BOOTLOADER_SIZE +\
+ CY_BOOT_PRIMARY_1_SIZE +\
+ CY_BOOT_SECONDARY_1_SIZE,
+#elif (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
+ .fa_off = CY_FLASH_BASE +\
+ CY_BOOT_BOOTLOADER_SIZE +\
+ CY_BOOT_PRIMARY_1_SIZE +\
+ CY_BOOT_SECONDARY_1_SIZE +\
+ CY_BOOT_PRIMARY_2_SIZE +\
+ CY_BOOT_SECONDARY_2_SIZE,
+#endif
+ .fa_size = CY_BOOT_SCRATCH_SIZE
+};
+#endif
+
+#ifdef CY_FLASH_MAP_EXT_DESC
+/* Use external Flash Map Descriptors */
+extern struct flash_area *boot_area_descs[];
+#else
+struct flash_area *boot_area_descs[] =
+{
+ &bootloader,
+ &primary_1,
+ &secondary_1,
+#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
+ &primary_2,
+ &secondary_2,
+#endif
+ &scratch,
+ NULL
+};
+#endif
+
+/* Returns device flash start based on supported fa_id */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret)
+{
+ if (fd_id != FLASH_DEVICE_INTERNAL_FLASH) {
+ BOOT_LOG_ERR("invalid flash ID %d; expected %d",
+ fd_id, FLASH_DEVICE_INTERNAL_FLASH);
+ return -1;
+ }
+ *ret = CY_FLASH_BASE;
+ return 0;
+}
+
+/* Opens the area for use. id is one of the `fa_id`s */
+int flash_area_open(uint8_t id, const struct flash_area **fa)
+{
+ int ret = -1;
+ uint32_t i = 0;
+
+ while(NULL != boot_area_descs[i])
+ {
+ if(id == boot_area_descs[i]->fa_id)
+ {
+ *fa = boot_area_descs[i];
+ ret = 0;
+ break;
+ }
+ i++;
+ }
+
+
+ return ret;
+}
+
+void flash_area_close(const struct flash_area *fa)
+{
+ (void)fa;/* Nothing to do there */
+}
+
+/* Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
+int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
+ uint32_t len)
+{
+ int rc = 0;
+ size_t addr;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ assert(off < fa->fa_off);
+ assert(off + len < fa->fa_off);
+
+ addr = fa->fa_off + off;
+
+ rc = psoc6_flash_read(addr, dst, len);
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement/split into psoc6_smif_read()
+ }
+#endif
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
+
+ if (rc != 0) {
+ BOOT_LOG_ERR("Flash area read error, rc = %d", (int)rc);
+ }
+
+ return rc;
+}
+
+/* Writes `len` bytes of flash memory at `off` from the buffer at `src` */
+int flash_area_write(const struct flash_area *fa, uint32_t off,
+ const void *src, uint32_t len)
+{
+ int rc = 0;
+ size_t addr;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ assert(off < fa->fa_off);
+ assert(off + len < fa->fa_off);
+
+ addr = fa->fa_off + off;
+ rc = psoc6_flash_write(addr, src, len);
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement/split into psoc6_smif_write()
+ }
+#endif
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
+
+ return rc;
+}
+
+/* Erases `len` bytes of flash memory at `off` */
+int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
+{
+ int rc = 0;
+ size_t addr;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ assert(off < fa->fa_off);
+ assert(off + len < fa->fa_off);
+
+ addr = fa->fa_off + off;
+ rc = psoc6_flash_erase(addr, len);
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement/split into psoc6_smif_erase()
+ }
+#endif
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
+ return rc;
+}
+
+/* Returns this `flash_area`s alignment */
+size_t flash_area_align(const struct flash_area *fa)
+{
+ uint8_t ret = -1;
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ ret = CY_FLASH_ALIGN;
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement for SMIF WR/ERASE size
+ }
+#endif
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ ret = -1;
+ }
+ return ret;
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+/* Initializes an array of flash_area elements for the slot's sectors */
+int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
+{
+ int rc = 0;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ // TODO:
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement/split into psoc6_smif_erase()
+ }
+#endif
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
+
+ return rc;
+}
+#endif
+
+/*
+ * This depends on the mappings defined in sysflash.h.
+ * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
+ * and the scratch while zephyr might number it differently.
+ */
+int flash_area_id_from_multi_image_slot(int image_index, int slot)
+{
+ switch (slot) {
+ case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
+ case 1: return FLASH_AREA_IMAGE_SECONDARY(image_index);
+ case 2: return FLASH_AREA_IMAGE_SCRATCH;
+ }
+
+ return -1; /* flash_area_open will fail on that */
+}
+
+int flash_area_id_from_image_slot(int slot)
+{
+ return flash_area_id_from_multi_image_slot(0, slot);
+}
+
+int flash_area_id_to_multi_image_slot(int image_index, int area_id)
+{
+ if (area_id == FLASH_AREA_IMAGE_PRIMARY(image_index)) {
+ return 0;
+ }
+ if (area_id == FLASH_AREA_IMAGE_SECONDARY(image_index)) {
+ return 1;
+ }
+
+ return -1;
+}
+
+int flash_area_id_to_image_slot(int area_id)
+{
+ return flash_area_id_to_multi_image_slot(0, area_id);
+}
+
+uint8_t flash_area_erased_val(const struct flash_area *fap)
+{
+ int ret = 0;
+
+ if (fap->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ ret = CY_BOOT_INTERNAL_FLASH_ERASE_VALUE ;
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if ((fap->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ ret = CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE ;
+ }
+#endif
+ else
+ {
+ assert(false) ;
+ }
+
+ return ret ;
+}
+
+int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
+ void *dst, uint32_t len)
+{
+ uint8_t i = 0;
+ uint8_t *mem_dest;
+ int rc;
+
+ mem_dest = (uint8_t *)dst;
+ rc = flash_area_read(fa, off, dst, len);
+ if (rc) {
+ return -1;
+ }
+
+ for (i = 0; i < len; i++) {
+ if (mem_dest[i] != flash_area_erased_val(fa)) {
+ return 0;
+ }
+ }
+ return 1;
+}
+
+int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
+{
+ int rc = 0;
+ uint32_t i = 0;
+ struct flash_area *fa;
+ size_t sector_size = 0;
+ size_t sectors_n = 0;
+ uint32_t addr = 0;
+
+ while(NULL != boot_area_descs[i])
+ {
+ if(idx == boot_area_descs[i]->fa_id)
+ {
+ fa = boot_area_descs[i];
+ break;
+ }
+ i++;
+ }
+
+
+ if(NULL != boot_area_descs[i])
+ {
+ if(fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
+ {
+ sector_size = CY_FLASH_SIZEOF_ROW;
+ }
+#ifdef CY_USE_EXTERNAL_FLASH
+ else if((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
+ {
+ // TODO: implement for SMIF
+ }
+#endif
+ else
+ {
+ rc = -1;
+ }
+
+ if(0 == rc)
+ {
+ sectors_n = (fa->fa_size + (sector_size - 1)) / sector_size;
+ assert(sectors_n <= *cnt);
+
+ addr = fa->fa_off;
+ for(i = 0; i < sectors_n; i++)
+ {
+ ret[i].fs_size = sector_size ;
+ ret[i].fs_off = addr ;
+ addr += sector_size ;
+ }
+
+ *cnt = sectors_n;
+ }
+ }
+ else
+ {
+ rc = -1;
+ }
+
+ return rc;
+}
diff --git a/boot/cypress/cy_flash_pal/cy_flash_psoc6.c b/boot/cypress/cy_flash_pal/cy_flash_psoc6.c
new file mode 100644
index 0000000..35dc30f
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/cy_flash_psoc6.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2020 Cypress Semiconductors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#include "string.h"
+#include "stdlib.h"
+#include "stdbool.h"
+
+#ifdef MCUBOOT_HAVE_ASSERT_H
+#include "mcuboot_config/mcuboot_assert.h"
+#else
+#include <assert.h>
+#endif
+
+#include "cy_device_headers.h"
+#include "cy_flash_psoc6.h"
+
+#include "cy_flash.h"
+#include "cy_syspm.h"
+
+#define PSOC6_WR_SUCCESS 0
+#define PSOC6_WR_ERROR_INVALID_PARAMETER 1
+#define PSOC6_WR_ERROR_FLASH_WRITE 2
+
+#define PSOC6_FLASH_ERASE_BLOCK_SIZE CY_FLASH_SIZEOF_ROW /* PSoC6 Flash erases by Row */
+
+int psoc6_flash_read(off_t addr, void *data, size_t len)
+{
+ /* flash read by simple memory copying */
+ memcpy((void *)data, (const void*)addr, (size_t)len);
+
+ return 0;
+}
+
+int psoc6_flash_write(off_t addr,
+ const void *data, size_t len)
+{
+ int rc;
+
+ rc = psoc6_flash_write_hal((uint8_t *)data, addr, len);
+
+ return rc;
+}
+
+int psoc6_flash_erase(off_t addr, size_t size)
+{
+ int rc = 0;
+
+ uint32_t addrStart, addrEnd, address;
+ uint32_t remStart, remEnd;
+ uint32_t rowIdxStart, rowIdxEnd, rowNum;
+ uint8_t buff[CY_FLASH_SIZEOF_ROW];
+
+ addrStart = addr;
+ addrEnd = addrStart + size;
+
+ /* find if area bounds are aligned to rows */
+ remStart = addrStart%CY_FLASH_SIZEOF_ROW;
+ remEnd = addrEnd%CY_FLASH_SIZEOF_ROW;
+
+ /* find which row numbers are affected for full Erase */
+ rowIdxStart = addrStart/CY_FLASH_SIZEOF_ROW;
+ rowIdxEnd = addrEnd/CY_FLASH_SIZEOF_ROW;
+
+ if(remStart != 0)
+ {/* first row is fragmented, move to next */
+ rowIdxStart++;
+ }
+
+ /* total number of rows for full erase */
+ rowNum = rowIdxEnd - rowIdxStart;
+ address = rowIdxStart*CY_FLASH_SIZEOF_ROW;
+
+ while(rowNum>0)
+ {
+ rc = Cy_Flash_EraseRow(address);
+ assert(rc == 0);
+ address += CY_FLASH_SIZEOF_ROW;
+ rowNum--;
+ }
+
+ /* if Start of erase area is unaligned */
+ if(remStart != 0)
+ {
+ /* first row is fragmented, shift left by one*/
+ rowIdxStart--;
+
+ /* find start address of fragmented row */
+ address = rowIdxStart*CY_FLASH_SIZEOF_ROW;
+
+ /* store fragmented row contents first */
+ memcpy((void *)buff, (const void*)address, remStart);
+
+ /* erase fragmented row */
+ rc = Cy_Flash_EraseRow(address);
+ assert(rc == 0);
+
+ /* write stored back */
+ rc = psoc6_flash_write_hal(buff, address, remStart);
+ assert(rc == 0);
+ }
+ /* if End of erase area is unaligned */
+ if(remEnd != 0)
+ {
+ /* find start address of fragmented row */
+ address = rowIdxEnd*CY_FLASH_SIZEOF_ROW;
+
+ /* store fragmented row contents first */
+ memcpy((void *)buff, (const void*)addrEnd, CY_FLASH_SIZEOF_ROW-remEnd);
+
+ /* erase fragmented row */
+ rc = Cy_Flash_EraseRow(address);
+ assert(rc == 0);
+
+ /* write stored back */
+ rc = psoc6_flash_write_hal(buff, addrEnd, CY_FLASH_SIZEOF_ROW-remEnd);
+ assert(rc == 0);
+ }
+ return rc;
+}
+
+/*******************************************************************************
+* Function Name: psoc6_flash_write_hal
+****************************************************************************//**
+*
+* This function writes the data to the PSOC6's Flash. It will check the
+* appropriate alignment of a start address and also perform an address range
+* check based on the length before performing the write operation.
+* This function performs memory compare and writes only row where there are new
+* data to write.
+*
+* \param addr: Pointer to the buffer containing the data to be stored.
+* \param data: Pointer to the array or variable in the flash.
+* \param len: The length of the data in bytes.
+*
+* \return
+* PSOC6_WR_SUCCESS A successful write
+* PSOC6_WR_ERROR_INVALID_PARAMETER At least one of the input parameters is invalid
+* PSOC6_WR__ERROR_FLASH_WRITE Error in flash Write
+*
+*******************************************************************************/
+int psoc6_flash_write_hal(uint8_t data[],
+ uint32_t address,
+ uint32_t len)
+{
+ int retCode;
+ cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
+
+ uint32_t writeBuffer[CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)];
+ uint32_t rowId;
+ uint32_t dstIndex;
+ uint32_t srcIndex = 0u;
+ uint32_t eeOffset;
+ uint32_t byteOffset;
+ uint32_t rowsNotEqual;
+ uint8_t *writeBufferPointer;
+
+ eeOffset = (uint32_t)address;
+ writeBufferPointer = (uint8_t*)writeBuffer;
+
+ bool cond1;
+
+ /* Make sure, that varFlash[] points to Flash */
+ cond1 = ((eeOffset >= CY_FLASH_BASE) &&
+ ((eeOffset + len) <= (CY_FLASH_BASE + CY_FLASH_SIZE)));
+
+ if(cond1)
+ {
+ eeOffset -= CY_FLASH_BASE;
+ rowId = eeOffset / CY_FLASH_SIZEOF_ROW;
+ byteOffset = CY_FLASH_SIZEOF_ROW * rowId;
+
+ while((srcIndex < len) && (rc == CY_FLASH_DRV_SUCCESS))
+ {
+ rowsNotEqual = 0u;
+ /* Copy data to the write buffer either from the source buffer or from the flash */
+ for(dstIndex = 0u; dstIndex < CY_FLASH_SIZEOF_ROW; dstIndex++)
+ {
+ if((byteOffset >= eeOffset) && (srcIndex < len))
+ {
+ writeBufferPointer[dstIndex] = data[srcIndex];
+ /* Detect that row programming is required */
+ if((rowsNotEqual == 0u) && (CY_GET_REG8(CY_FLASH_BASE + byteOffset) != data[srcIndex]))
+ {
+ rowsNotEqual = 1u;
+ }
+ srcIndex++;
+ }
+ else
+ {
+ writeBufferPointer[dstIndex] = CY_GET_REG8(CY_FLASH_BASE + byteOffset);
+ }
+ byteOffset++;
+ }
+
+ if(rowsNotEqual != 0u)
+ {
+ /* Write flash row */
+ rc = Cy_Flash_WriteRow((rowId * CY_FLASH_SIZEOF_ROW) + CY_FLASH_BASE, writeBuffer);
+ }
+
+ /* Go to the next row */
+ rowId++;
+ }
+ }
+ else
+ {
+ rc = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ }
+
+ /* Return error code */
+ switch(rc)
+ {
+ case CY_FLASH_DRV_SUCCESS:
+ retCode = PSOC6_WR_SUCCESS;
+ break;
+
+ case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ case CY_FLASH_DRV_INVALID_FLASH_ADDR:
+ retCode = PSOC6_WR_ERROR_INVALID_PARAMETER;
+ break;
+
+ default:
+ retCode = PSOC6_WR_ERROR_FLASH_WRITE;
+ break;
+ }
+ return(retCode);
+}
diff --git a/boot/cypress/cy_flash_pal/include/cy_flash_psoc6.h b/boot/cypress/cy_flash_pal/include/cy_flash_psoc6.h
new file mode 100644
index 0000000..09cea98
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/include/cy_flash_psoc6.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifndef CY_FLASH_PSOC6_H_
+#define CY_FLASH_PSOC6_H_
+
+#include "stddef.h"
+#include "stdbool.h"
+
+#ifndef off_t
+typedef long int off_t;
+#endif
+
+int psoc6_flash_read(off_t addr, void *data, size_t len);
+int psoc6_flash_write(off_t addr, const void *data, size_t len);
+int psoc6_flash_erase(off_t addr, size_t size);
+
+int psoc6_flash_write_hal(uint8_t data[],
+ uint32_t address,
+ uint32_t len);
+#endif /* CY_FLASH_PSOC6_H_ */
diff --git a/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h b/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
new file mode 100644
index 0000000..5357232
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifndef __FLASH_MAP_BACKEND_H__
+#define __FLASH_MAP_BACKEND_H__
+
+#include <mcuboot_config/mcuboot_config.h>
+#include "cy_flash.h"
+
+/**
+ *
+ * Provides abstraction of flash regions for type of use.
+ * I.e. dude where's my image?
+ *
+ * System will contain a map which contains flash areas. Every
+ * region will contain flash identifier, offset within flash and length.
+ *
+ * 1. This system map could be in a file within filesystem (Initializer
+ * must know/figure out where the filesystem is at).
+ * 2. Map could be at fixed location for project (compiled to code)
+ * 3. Map could be at specific place in flash (put in place at mfg time).
+ *
+ * Note that the map you use must be valid for BSP it's for,
+ * match the linker scripts when platform executes from flash,
+ * and match the target offset specified in download script.
+ */
+#include <inttypes.h>
+
+/**
+ * @brief Structure describing an area on a flash device.
+ *
+ * Multiple flash devices may be available in the system, each of
+ * which may have its own areas. For this reason, flash areas track
+ * which flash device they are part of.
+ */
+struct flash_area {
+ /**
+ * This flash area's ID; unique in the system.
+ */
+ uint8_t fa_id;
+
+ /**
+ * ID of the flash device this area is a part of.
+ */
+ uint8_t fa_device_id;
+
+ uint16_t pad16;
+
+ /**
+ * This area's offset, relative to the beginning of its flash
+ * device's storage.
+ */
+ uint32_t fa_off;
+
+ /**
+ * This area's size, in bytes.
+ */
+ uint32_t fa_size;
+};
+
+/**
+ * @brief Structure describing a sector within a flash area.
+ *
+ * Each sector has an offset relative to the start of its flash area
+ * (NOT relative to the start of its flash device), and a size. A
+ * flash area may contain sectors with different sizes.
+ */
+struct flash_sector {
+ /**
+ * Offset of this sector, from the start of its flash area (not device).
+ */
+ uint32_t fs_off;
+
+ /**
+ * Size of this sector, in bytes.
+ */
+ uint32_t fs_size;
+};
+
+struct flash_map_entry {
+ uint32_t magic;
+ struct flash_area area;
+ unsigned int ref_count;
+};
+
+/*
+ * Retrieve a memory-mapped flash device's base address.
+ * On success, the address will be stored in the value pointed to by
+ * ret.
+ * Returns 0 on success, or an error code on failure.
+ */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret);
+
+/*< Opens the area for use. id is one of the `fa_id`s */
+int flash_area_open(uint8_t id, const struct flash_area **);
+void flash_area_close(const struct flash_area *);
+/*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
+int flash_area_read(const struct flash_area *, uint32_t off, void *dst,
+ uint32_t len);
+/*< Writes `len` bytes of flash memory at `off` from the buffer at `src` */
+int flash_area_write(const struct flash_area *, uint32_t off,
+ const void *src, uint32_t len);
+/*< Erases `len` bytes of flash memory at `off` */
+int flash_area_erase(const struct flash_area *, uint32_t off, uint32_t len);
+/*< Returns this `flash_area`s alignment */
+size_t flash_area_align(const struct flash_area *);
+/*< Initializes an array of flash_area elements for the slot's sectors */
+int flash_area_to_sectors(int idx, int *cnt, struct flash_area *ret);
+/*< Returns the `fa_id` for slot, where slot is 0 (primary) or 1 (secondary) */
+int flash_area_id_from_image_slot(int slot);
+/*< Returns the slot, for the `fa_id` supplied */
+int flash_area_id_to_image_slot(int area_id);
+
+int flash_area_id_from_multi_image_slot(int image_index, int slot);
+int flash_area_id_to_multi_image_slot(int image_index, int area_id);
+
+/*
+ * Returns the value expected to be read when accesing any erased
+ * flash byte.
+ */
+uint8_t flash_area_erased_val(const struct flash_area *fap);
+
+/*
+ * Reads len bytes from off, and checks if the read data is erased.
+ *
+ * Returns 1 if erased, 0 if non-erased, and -1 on failure.
+ */
+int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
+ void *dst, uint32_t len);
+
+#endif /* __FLASH_MAP_BACKEND_H__ */
diff --git a/boot/cypress/keys/cypress-test-ec-p256.pem b/boot/cypress/keys/cypress-test-ec-p256.pem
new file mode 100644
index 0000000..e1f8e15
--- /dev/null
+++ b/boot/cypress/keys/cypress-test-ec-p256.pem
@@ -0,0 +1,5 @@
+-----BEGIN PRIVATE KEY-----
+MIGHAgEAMBMGByqGSM49AgEGCCqGSM49AwEHBG0wawIBAQQguR/Jq6LjMgp8DVtE
+7pKguttNo6L239aEcijzGOr5C72hRANCAAT/NroNASdTGo6bS8r0+C+30YcG0WLV
+chWs+99DnOr3SZoalv6/pCNIVrwFv3KkJsmsZUbNNmxeMPr+IlfGGPg0
+-----END PRIVATE KEY-----
diff --git a/boot/cypress/keys/cypress-test-ec-p256.pub b/boot/cypress/keys/cypress-test-ec-p256.pub
new file mode 100644
index 0000000..8174b5d
--- /dev/null
+++ b/boot/cypress/keys/cypress-test-ec-p256.pub
@@ -0,0 +1,16 @@
+/* Autogenerated by imgtool.py, do not edit. */
+const unsigned char ecdsa_pub_key[] = {
+ 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
+ 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a,
+ 0x86, 0x48, 0xce, 0x3d, 0x03, 0x01, 0x07, 0x03,
+ 0x42, 0x00, 0x04, 0xff, 0x36, 0xba, 0x0d, 0x01,
+ 0x27, 0x53, 0x1a, 0x8e, 0x9b, 0x4b, 0xca, 0xf4,
+ 0xf8, 0x2f, 0xb7, 0xd1, 0x87, 0x06, 0xd1, 0x62,
+ 0xd5, 0x72, 0x15, 0xac, 0xfb, 0xdf, 0x43, 0x9c,
+ 0xea, 0xf7, 0x49, 0x9a, 0x1a, 0x96, 0xfe, 0xbf,
+ 0xa4, 0x23, 0x48, 0x56, 0xbc, 0x05, 0xbf, 0x72,
+ 0xa4, 0x26, 0xc9, 0xac, 0x65, 0x46, 0xcd, 0x36,
+ 0x6c, 0x5e, 0x30, 0xfa, 0xfe, 0x22, 0x57, 0xc6,
+ 0x18, 0xf8, 0x34,
+};
+const unsigned int ecdsa_pub_key_len = 91;
diff --git a/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/cy8c6xxa_cm0plus.ld b/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/cy8c6xxa_cm0plus.ld
new file mode 100644
index 0000000..1f3a5a9
--- /dev/null
+++ b/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/cy8c6xxa_cm0plus.ld
@@ -0,0 +1,418 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm0plus.ld
+* \version 2.70
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
+ */
+ ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ /* Cortex-M0+ application flash area */
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/startup_psoc6_02_cm0plus.S b/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/startup_psoc6_02_cm0plus.S
new file mode 100644
index 0000000..2641f62
--- /dev/null
+++ b/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/startup_psoc6_02_cm0plus.S
@@ -0,0 +1,372 @@
+/**************************************************************************//**
+ * @file startup_psoc6_02_cm0plus.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ .long Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ .long Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ .long Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ .long Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ .long Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ .long Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ .long Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ .long Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/cy8c6xxa_cm4_dual.ld b/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/cy8c6xxa_cm4_dual.ld
new file mode 100644
index 0000000..ec70309
--- /dev/null
+++ b/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/cy8c6xxa_cm4_dual.ld
@@ -0,0 +1,436 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm4_dual.ld
+* \version 2.70
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+/* The size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE = 0x2000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+ */
+ ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ /* Cortex-M0+ application flash image area */
+ .cy_m0p_image ORIGIN(flash) :
+ {
+ . = ALIGN(4);
+ __cy_m0p_code_start = . ;
+ KEEP(*(.cy_m0p_image))
+ __cy_m0p_code_end = . ;
+ } > flash
+
+ /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+ ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+ /* Cortex-M4 application flash area */
+ .text ORIGIN(flash) + FLASH_CM0P_SIZE :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK application.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/startup_psoc6_02_cm4.S b/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/startup_psoc6_02_cm4.S
new file mode 100644
index 0000000..3eb9dab
--- /dev/null
+++ b/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/startup_psoc6_02_cm4.S
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file startup_psoc6_02_cm4.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* OS-specific low-level initialization */
+ .weak cy_toolchain_init
+ .func cy_toolchain_init, cy_toolchain_init
+ .type cy_toolchain_init, %function
+
+cy_toolchain_init:
+ bx lr
+ .size cy_toolchain_init, . - cy_toolchain_init
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ /* OS-specific low-level initialization */
+ bl cy_toolchain_init
+
+ /* Call C/C++ static constructors */
+ bl __libc_init_array
+
+ /* Execute main application */
+ bl main
+
+ /* Call C/C++ static destructors */
+ bl __libc_fini_array
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/cycfg.c b/boot/cypress/platforms/cycfg.c
new file mode 100644
index 0000000..ede3da0
--- /dev/null
+++ b/boot/cypress/platforms/cycfg.c
@@ -0,0 +1,33 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+ init_cycfg_system();
+ init_cycfg_clocks();
+}
diff --git a/boot/cypress/platforms/cycfg.h b/boot/cypress/platforms/cycfg.h
new file mode 100644
index 0000000..9b74187
--- /dev/null
+++ b/boot/cypress/platforms/cycfg.h
@@ -0,0 +1,45 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_system.h"
+#include "cycfg_clocks.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */
diff --git a/boot/cypress/platforms/cycfg_clocks.c b/boot/cypress/platforms/cycfg_clocks.c
new file mode 100644
index 0000000..7f720f7
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_clocks.c
@@ -0,0 +1,47 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+ {
+ .type = CYHAL_RSC_CLOCK,
+ .block_num = CYBSP_CSD_CLK_DIV_HW,
+ .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_clocks.h b/boot/cypress/platforms/cycfg_clocks.h
new file mode 100644
index 0000000..5766ab5
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_clocks.h
@@ -0,0 +1,54 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */
diff --git a/boot/cypress/platforms/cycfg_system.c b/boot/cypress/platforms/cycfg_system.c
new file mode 100644
index 0000000..57ab013
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_system.c
@@ -0,0 +1,537 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+{
+ .fllMult = 500U,
+ .refDiv = 20U,
+ .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+ .enableOutputDiv = true,
+ .lockTolerance = 10U,
+ .igain = 9U,
+ .pgain = 5U,
+ .settlingCount = 8U,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+ .cco_Freq = 355U,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 0U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 1U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 2U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+ .feedbackDiv = 36,
+ .referenceDiv = 1,
+ .outputDiv = 2,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
+{
+ .feedbackDiv = 30,
+ .referenceDiv = 1,
+ .outputDiv = 5,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+ (void)error; /* Suppress the compiler warning */
+ while(1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+ Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkBakInit()
+{
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkFastInit()
+{
+ Cy_SysClk_ClkFastSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_FllInit()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+{
+ Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+{
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+{
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+}
+__STATIC_INLINE void Cy_SysClk_IloInit()
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_IloEnable();
+ Cy_SysClk_IloHibernateOn(true);
+}
+__STATIC_INLINE void Cy_SysClk_ClkLfInit()
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+{
+ Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+{
+ Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+{
+ Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+{
+ Cy_SysClk_ClkPeriSetDivider(1U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_Pll1Init()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+{
+ Cy_SysClk_ClkSlowSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+{
+ Cy_SysClk_ClkTimerDisable();
+ Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+ Cy_SysClk_ClkTimerSetDivider(0U);
+ Cy_SysClk_ClkTimerEnable();
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit()
+{
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+ }
+}
+
+
+void init_cycfg_system(void)
+{
+ /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+ Cy_SysLib_SetWaitStates(false, 150UL);
+ #ifdef CY_CFG_PWR_ENABLED
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
+
+ /* Reset the core clock path to default and disable all the FLLs/PLLs */
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkFastSetDivider(0U);
+ Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkSlowSetDivider(0U);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+ (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+ {
+ Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ }
+
+ Cy_SysClk_FllDisable();
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
+ #endif
+
+
+ /* Enable all source clocks */
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ Cy_SysClk_PiloInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ Cy_SysClk_WcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ Cy_SysClk_ClkLfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ Cy_SysClk_AltHfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ Cy_SysClk_EcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
+ #endif
+
+ /* Configure CPU clock dividers */
+ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+ Cy_SysClk_ClkFastInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+ Cy_SysClk_ClkPeriInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+ Cy_SysClk_ClkSlowInit();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ #else
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ Cy_SysClk_ClkPath2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ Cy_SysClk_ClkPath3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ Cy_SysClk_ClkPath4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ Cy_SysClk_ClkPath5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+ Cy_SysClk_ClkPath6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+ Cy_SysClk_ClkPath7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+ Cy_SysClk_ClkPath8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+ Cy_SysClk_ClkPath9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+ Cy_SysClk_ClkPath10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+ Cy_SysClk_ClkPath11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+ Cy_SysClk_ClkPath12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+ Cy_SysClk_ClkPath13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+ Cy_SysClk_ClkPath14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+ Cy_SysClk_ClkPath15Init();
+ #endif
+
+ /* Configure and enable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllInit();
+ #endif
+
+ Cy_SysClk_ClkHf0Init();
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ /* Apply the ClkPath1 user setting */
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure and enable PLLs */
+ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+ Cy_SysClk_Pll0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+ Cy_SysClk_Pll1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+ Cy_SysClk_Pll2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+ Cy_SysClk_Pll3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+ Cy_SysClk_Pll4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+ Cy_SysClk_Pll5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+ Cy_SysClk_Pll6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+ Cy_SysClk_Pll7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+ Cy_SysClk_Pll8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+ Cy_SysClk_Pll9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+ Cy_SysClk_Pll10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+ Cy_SysClk_Pll11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+ Cy_SysClk_Pll12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+ Cy_SysClk_Pll13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+ Cy_SysClk_Pll14Init();
+ #endif
+
+ /* Configure HF clocks */
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ Cy_SysClk_ClkHf1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ Cy_SysClk_ClkHf2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ Cy_SysClk_ClkHf3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ Cy_SysClk_ClkHf4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ Cy_SysClk_ClkHf5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+ Cy_SysClk_ClkHf6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+ Cy_SysClk_ClkHf7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+ Cy_SysClk_ClkHf8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+ Cy_SysClk_ClkHf9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+ Cy_SysClk_ClkHf10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+ Cy_SysClk_ClkHf11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+ Cy_SysClk_ClkHf12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+ Cy_SysClk_ClkHf13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+ Cy_SysClk_ClkHf14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+ Cy_SysClk_ClkHf15Init();
+ #endif
+
+ /* Configure miscellaneous clocks */
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+ Cy_SysClk_ClkTimerInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ Cy_SysClk_ClkPumpInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ Cy_SysClk_ClkBakInit();
+ #endif
+
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #else
+ Cy_SysClk_IloDisable();
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
+ /* Set accurate flash wait states */
+ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+ Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+ #endif
+
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_system.h b/boot/cypress/platforms/cycfg_system.h
new file mode 100644
index 0000000..581aeda
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_system.h
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/boot/cypress/platforms/system_psoc6.h b/boot/cypress/platforms/system_psoc6.h
new file mode 100644
index 0000000..ee2bb38
--- /dev/null
+++ b/boot/cypress/platforms/system_psoc6.h
@@ -0,0 +1,657 @@
+/***************************************************************************//**
+* \file system_psoc6.h
+* \version 2.70
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_PSOC6_H_
+#define _SYSTEM_PSOC6_H_
+
+/**
+* \addtogroup group_system_config
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - See \ref group_system_config_device_initialization for the:
+* * \ref group_system_config_dual_core_device_initialization
+* * \ref group_system_config_single_core_device_initialization
+* - \ref group_system_config_device_memory_definition
+* - \ref group_system_config_heap_stack_config
+* - \ref group_system_config_merge_apps
+* - \ref group_system_config_default_handlers
+* - \ref group_system_config_device_vector_table
+* - \ref group_system_config_cm4_functions
+*
+* \section group_system_config_configuration Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition Device Memory Definition
+* The flash and RAM allocation for each CPU is defined by the linker scripts.
+* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
+* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
+* For Single-Core devices the system reserves additional 80 bytes of RAM.
+* Using the reserved memory area for other purposes will lead to unexpected behavior.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
+* \endcode
+* - 'xx_cm4_dual.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
+* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
+* by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>ARM MDK</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10000000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08000000
+* #define RAM_SIZE 0x00024000
+* \endcode
+* - 'xx_cm4_dual.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10080000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08024000
+* #define RAM_SIZE 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
+* value in the 'xx_cm4_dual.scat' file,
+* where 'xx' is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
+* \endcode
+* - 'xx_cm4_dual.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
+* is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* \subsection group_system_config_device_initialization Device Initialization
+* After a power-on-reset (POR), the boot process is handled by the boot code
+* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
+* code passes the control to the Cortex-M0+ startup code located in flash.
+*
+* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
+* The Cortex-M0+ startup code performs the device initialization by a call to
+* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
+* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
+* See \ref group_system_config_cm4_functions for more details.
+* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
+* The function has a separate implementation on each core.
+* Both function implementations unlock and disable the WDT.
+* Therefore enable the WDT after both cores have been initialized.
+*
+* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
+* The Cortex-M0+ core is not user-accessible on these devices. In this case the
+* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
+*
+* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
+* There are two ways to adjust heap and stack configurations:
+* -# Editing source code files
+* -# Specifying via command line
+*
+* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files
+* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code .equ Stack_Size, 0x00001000 \endcode
+* \code .equ Heap_Size, 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the compiler:\n
+* \code -D __STACK_SIZE=0x000000400 \endcode
+* \code -D __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files
+* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the assembler:\n
+* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
+* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar IAR
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the
+* linker (including quotation marks):\n
+* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
+* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
+* The CM0+ project and linker script build the CM0+ application image. Similarly,
+* the CM4 linker script builds the CM4 application image. Each specifies
+* locations, sizes, and contents of sections in memory. See
+* \ref group_system_config_device_memory_definition for the symbols and default
+* values.
+*
+* The cymcuelftool is invoked by a post-build command. The precise project
+* setting is IDE-specific.
+*
+* The cymcuelftool combines the two executables. The tool examines the
+* executables to ensure that memory regions either do not overlap, or contain
+* identical bytes (shared). If there are no problems, it creates a new ELF file
+* with the merged image, without changing any of the addresses or data.
+*
+* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
+* The default interrupt handler functions are defined as weak functions to a dummy
+* handler in the startup file. The naming convention for the interrupt handler names
+* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
+* user code by defining the handler function using the same name. For example:
+* \code
+* void scb_0_interrupt_IRQHandler(void)
+*{
+* ...
+*}
+* \endcode
+*
+* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
+* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
+* It defines sections and locations in memory.\n
+* Copy interrupt vectors from flash to RAM: \n
+* From: \code LONG (__Vectors) \endcode
+* To: \code LONG (__ram_vectors_start__) \endcode
+* Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* The code in these files copies the vector table from Flash to RAM.
+* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
+* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
+* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the assembler startup
+* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar IAR
+* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* This file defines the .intvec_ram section and its location.
+* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \section group_system_config_more_information More Information
+* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
+* more details.
+*
+* \section group_system_config_MISRA MISRA Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>R</td>
+* <td>The character sequence // shall not be used within a comment.</td>
+* <td>The comments provide a useful WEB link to the documentation.</td>
+* </tr>
+* </table>
+*
+* \section group_system_config_changelog Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td rowspan="4">2.70</td>
+* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
+* <td>Code optimization.</td>
+* </tr>
+* <tr>
+* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
+* <td>Provided support for SysPM driver updates.</td>
+* </tr>
+* <tr>
+* <td>Updated the linker scripts.</td>
+* <td>Reserved FLASH area for the MCU boot headers.</td>
+* </tr>
+* <tr>
+* <td>Added System Pipe initialization for all devices. </td>
+* <td>Improved PDL usability according to user experience.</td>
+* </tr>
+* <tr>
+* <td>2.60</td>
+* <td>Updated linker scripts.</td>
+* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
+* </tr>
+* <tr>
+* <td>2.50</td>
+* <td>Updated assembler files, C files, linker scripts.</td>
+* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
+* </tr>
+* <tr>
+* <td>2.40</td>
+* <td>Updated assembler files, C files, linker scripts.</td>
+* <td>Added Arm Compiler 6 support.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">2.30</td>
+* <td>Added assembler files, linker scripts for Mbed OS.</td>
+* <td>Added Arm Mbed OS embedded operating system support.</td>
+* </tr>
+* <tr>
+* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
+* <td>Enhanced PDL usability.</td>
+* </tr>
+* <tr>
+* <td>2.20</td>
+* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
+* <td>Changed the IPC driver configuration method from compile time to run time.</td>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.10</td>
+* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
+* Removed $Sub$$main symbol for ARM MDK compiler.
+* </td>
+* <td>uVision Debugger support.</td>
+* </tr>
+* <tr>
+* <td>Updated description of the Startup behavior for Single-Core Devices. \n
+* Added note about WDT disabling by SystemInit() function.
+* </td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
+* Single core device support.
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
+* Renamed 'wflash' memory region to 'em_eeprom'.
+* </td>
+* <td>Linker scripts usability improvement.</td>
+* </tr>
+* <tr>
+* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
+* <td>Reserved system resources for internal operations.</td>
+* </tr>
+* <tr>
+* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
+* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro Macro
+* \{
+* \defgroup group_system_config_system_macro System
+* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
+* \defgroup group_system_config_user_settings_macro User Settings
+* \}
+* \defgroup group_system_config_functions Functions
+* \{
+* \defgroup group_system_config_system_functions System
+* \defgroup group_system_config_cm4_functions Cortex-M4 Control
+* \}
+* \defgroup group_system_config_globals Global Variables
+*
+* \}
+*/
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+* \details
+* The following system functions implement CMSIS Core functions.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* \}
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
+ #define CY_SYSTEM_CPU_CM0P 1UL
+#else
+ #define CY_SYSTEM_CPU_CM0P 0UL
+#endif
+
+
+/*******************************************************************************
+*
+* START OF USER SETTINGS HERE
+* ===========================
+*
+* All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_user_settings_macro
+* \{
+*/
+
+
+/***************************************************************************//**
+* \brief Start address of the Cortex-M4 application ([address]UL)
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#if !defined (CY_CORTEX_M4_APPL_ADDR)
+ #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
+#endif /* (CY_CORTEX_M4_APPL_ADDR) */
+
+
+/***************************************************************************//**
+* \brief IPC Semaphores allocation ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
+
+
+/***************************************************************************//**
+* \brief IPC Pipe definitions ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
+
+
+/*******************************************************************************
+*
+* END OF USER SETTINGS HERE
+* =========================
+*
+*******************************************************************************/
+
+/** \} group_system_config_user_settings_macro */
+
+
+/**
+* \addtogroup group_system_config_system_macro
+* \{
+*/
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M0+ startup driver identifier */
+ #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M4 startup driver identifier */
+ #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
+
+/** \} group_system_config_system_macro */
+
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+*/
+#if defined(__ARMCC_VERSION)
+ extern void SystemInit(void) __attribute__((constructor));
+#else
+ extern void SystemInit(void);
+#endif /* (__ARMCC_VERSION) */
+
+extern void SystemCoreClockUpdate(void);
+/** \} group_system_config_system_functions */
+
+
+/**
+* \addtogroup group_system_config_cm4_functions
+* \{
+*/
+extern uint32_t Cy_SysGetCM4Status(void);
+extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
+extern void Cy_SysDisableCM4(void);
+extern void Cy_SysRetainCM4(void);
+extern void Cy_SysResetCM4(void);
+/** \} group_system_config_cm4_functions */
+
+
+/** \cond */
+extern void Default_Handler (void);
+
+void Cy_SysIpcPipeIsrCm0(void);
+void Cy_SysIpcPipeIsrCm4(void);
+
+extern void Cy_SystemInit(void);
+extern void Cy_SystemInitFpuEnable(void);
+
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+extern uint32_t cy_delay32kMs;
+/** \endcond */
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/**
+* \addtogroup group_system_config_cm4_status_macro
+* \{
+*/
+#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+/** \} group_system_config_cm4_status_macro */
+
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+
+/*******************************************************************************
+* IPC Configuration
+* =========================
+*******************************************************************************/
+/* IPC CY_PIPE default configuration */
+#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
+
+#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
+
+#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
+
+
+/******************************************************************************/
+/*
+ * The System pipe configuration defines the IPC channel number, interrupt
+ * number, and the pipe interrupt mask for the endpoint.
+ *
+ * The format of the endPoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+
+/* System Pipe addresses */
+/* CyPipe defines */
+
+#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
+
+#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP1)
+
+/******************************************************************************/
+
+
+/** \addtogroup group_system_config_globals
+* \{
+*/
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_BleEcoClockFreqHz;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+
+/** \} group_system_config_globals */
+
+
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Backward compatibility macros. The following code is DEPRECATED and must
+* not be used in new projects
+*******************************************************************************/
+
+/* BWC defines for functions related to enter/exit critical section */
+#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
+#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
+#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
+#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
+#define cy_delayFreqHz (SystemCoreClock)
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_PSOC6_H_ */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/system_psoc6_cm0plus.c b/boot/cypress/platforms/system_psoc6_cm0plus.c
new file mode 100644
index 0000000..18cc197
--- /dev/null
+++ b/boot/cypress/platforms/system_psoc6_cm0plus.c
@@ -0,0 +1,526 @@
+/***************************************************************************//**
+* \file system_psoc6_cm0plus.c
+* \version 2.70
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
+
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+
+uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+
+/*******************************************************************************
+* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
+*******************************************************************************/
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+*
+* Initializes the system:
+* - Restores FLL registers to the default state.
+* - Unlocks and disables WDT.
+* - Calls Cy_PDL_Init() function to define the driver library.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+*
+*******************************************************************************/
+void SystemInit(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+ /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* Allocate and initialize semaphores for the system operations. */
+ CY_SECTION(".cy_sharedmem")
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+
+
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
+ };
+
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
+
+ if (0UL != locHf0Clock)
+ {
+ cy_Hfclk0FreqHz = locHf0Clock;
+ cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
+ SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+ }
+}
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+ uint32_t regValue;
+
+ /* Get current power mode */
+ regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+ return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+ uint32_t regValue;
+ uint32_t interruptState;
+ uint32_t cpuState;
+
+ CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ cpuState = Cy_SysGetCM4Status();
+ if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+ {
+ Cy_SysResetCM4();
+ }
+
+ CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_ENABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_DISABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RETAINED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RESET;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm0
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm0(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/system_psoc6_cm4.c b/boot/cypress/platforms/system_psoc6_cm4.c
new file mode 100644
index 0000000..7800d6b
--- /dev/null
+++ b/boot/cypress/platforms/system_psoc6_cm4.c
@@ -0,0 +1,390 @@
+/***************************************************************************//**
+* \file system_psoc6_cm4.c
+* \version 2.70
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default FastClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
+
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+/* IPC_STRUCT7->DATA configuration */
+#define CY_STARTUP_CM0_DP_STATE (0x2uL)
+#define CY_STARTUP_IPC7_DP_OFFSET (0x28u)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+
+uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+* \cond
+* Initializes the system:
+* - Restores FLL registers to the default state for single core devices.
+* - Unlocks and disables WDT.
+* - Calls Cy_PDL_Init() function to define the driver library.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+* \endcond
+*******************************************************************************/
+void SystemInit(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+ #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
+ CY_STARTUP_IPC7_DP_OFFSET);
+
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+ #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Allocate and initialize semaphores for the system operations. */
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+ #else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+ #endif /* (__CM0P_PRESENT) */
+#else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+#endif /* __CM0P_PRESENT */
+
+
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
+ };
+
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
+
+ if (0UL != locHf0Clock)
+ {
+ cy_Hfclk0FreqHz = locHf0Clock;
+ cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
+ SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInitFpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void Cy_SystemInitFpuEnable(void)
+{
+ #if defined (__FPU_USED) && (__FPU_USED == 1U)
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+ __DSB();
+ __ISB();
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm4
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm4(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/* [] END OF FILE */