commit 70af708b85b3cc316632e4e4258e092c0f4fd8a4
author Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no> Thu Oct 22 15:14:48 2020 +0200
committer Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no> Wed Oct 28 22:02:15 2020 +0100
tree 529e8c0d9c28f853338c07c3ba841adb77350727
parent 518d93a6b600c585d4e8628779180b5222cfd285

boot: zephyr: clean ARM core configuration only when selected by user

Clean up the ARM core configuration only when
the CONFIG_MCUBOOT_CLEANUP_ARM_CORE is selected.
This involves cache and stack pointer limit registers.

Add also an MPU cleanup in platforms with the ARM MPU
supported.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>

boot/zephyr/main.c

diff --git a/boot/zephyr/main.c b/boot/zephyr/main.c
index 0082069..a57fba5 100644
--- a/boot/zephyr/main.c
+++ b/boot/zephyr/main.c
@@ -131,12 +131,6 @@
                                      rsp->br_image_off +
                                      rsp->br_hdr->ih_hdr_size);
 
-#ifdef CONFIG_CPU_CORTEX_M7
-    /* Disable instruction cache and data cache before chain-load the application */
-    SCB_DisableDCache();
-    SCB_DisableICache();
-#endif
-
     irq_lock();
 #ifdef CONFIG_SYS_CLOCK_EXISTS
     sys_clock_disable();
@@ -147,6 +141,15 @@
 #endif
 #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
     cleanup_arm_nvic(); /* cleanup NVIC registers */
+
+#ifdef CONFIG_CPU_CORTEX_M7
+    /* Disable instruction cache and data cache before chain-load the application */
+    SCB_DisableDCache();
+    SCB_DisableICache();
+#endif
+
+#if CONFIG_CPU_HAS_ARM_MPU
+    z_arm_clear_arm_mpu_config();
 #endif
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD) && \
@@ -158,6 +161,8 @@
     __set_MSPLIM(0);
 #endif
 
+#endif /* CONFIG_MCUBOOT_CLEANUP_ARM_CORE */
+
 #ifdef CONFIG_BOOT_INTR_VEC_RELOC
 #if defined(CONFIG_SW_VECTOR_RELAY)
     _vector_table_pointer = vt;