espressif: esp32c2: remove unsupported configs
Remove unsupported USB JTAG configuration
Remove unsupported Secure Boot V2 configuration
Signed-off-by: Almir Okato <almir.okato@espressif.com>
diff --git a/boot/espressif/port/esp32c2/bootloader.conf b/boot/espressif/port/esp32c2/bootloader.conf
index 5c5307c..286b1a1 100644
--- a/boot/espressif/port/esp32c2/bootloader.conf
+++ b/boot/espressif/port/esp32c2/bootloader.conf
@@ -21,14 +21,12 @@
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
-# Use Serial through USB JTAG Serial port for Serial Recovery
-# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
-# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
+# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=18
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
@@ -38,9 +36,9 @@
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
-# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=8
+# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=2
# GPIO for Serial TX signal
-# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=9
+# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=3
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
@@ -48,10 +46,8 @@
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
-# CONFIG_ESP_CONSOLE_UART_TX_GPIO=9
-# CONFIG_ESP_CONSOLE_UART_RX_GPIO=8
-# Use USB JTAG Serial for console printing
-# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
+# CONFIG_ESP_CONSOLE_UART_TX_GPIO=3
+# CONFIG_ESP_CONSOLE_UART_RX_GPIO=2
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
@@ -67,13 +63,6 @@
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
-# Hardware Secure Boot related options
-# CONFIG_SECURE_SIGNED_ON_BOOT=1
-# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
-# CONFIG_SECURE_BOOT=1
-# CONFIG_SECURE_BOOT_V2_ENABLED=1
-# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
-
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
diff --git a/boot/espressif/port/esp32c2/serial_adapter.c b/boot/espressif/port/esp32c2/serial_adapter.c
index f40fa41..d10c0d6 100644
--- a/boot/espressif/port/esp32c2/serial_adapter.c
+++ b/boot/espressif/port/esp32c2/serial_adapter.c
@@ -18,13 +18,12 @@
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
-#include <hal/usb_serial_jtag_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
-#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
+#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_18
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
@@ -46,8 +45,6 @@
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
-#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
-
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
@@ -57,31 +54,21 @@
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
-#define SERIAL_BOOT_GPIO_RX GPIO_NUM_8
+#define SERIAL_BOOT_GPIO_RX GPIO_NUM_2
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
-#define SERIAL_BOOT_GPIO_TX GPIO_NUM_9
+#define SERIAL_BOOT_GPIO_TX GPIO_NUM_3
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
-#endif
-
void console_write(const char *str, int cnt)
{
-#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
- usb_serial_jtag_ll_txfifo_flush();
- while (!usb_serial_jtag_ll_txfifo_writable()) {
- MCUBOOT_WATCHDOG_FEED();
- }
- usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
- usb_serial_jtag_ll_txfifo_flush();
-#else
uint32_t tx_len;
uint32_t write_len;
@@ -95,27 +82,10 @@
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
-#endif
}
int console_read(char *str, int cnt, int *newline)
{
-#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
- uint32_t read_len = 0;
-
- esp_rom_delay_us(1000);
- do {
- if (usb_serial_jtag_ll_rxfifo_data_available()) {
- usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
- read_len++;
- }
- MCUBOOT_WATCHDOG_FEED();
- esp_rom_delay_us(1000);
- } while (!(read_len == cnt || str[read_len - 1] == '\n'));
- *newline = (str[read_len - 1] == '\n') ? 1 : 0;
-
- return read_len;
-#else
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
@@ -140,17 +110,12 @@
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
-#endif
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
-#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
- usb_serial_jtag_ll_txfifo_flush();
- esp_rom_uart_tx_wait_idle(0);
-#else
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
@@ -167,9 +132,9 @@
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
- uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
+ uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_DEFAULT);
uart_ll_set_mode_normal(serial_boot_uart_dev);
- uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_APB);
+ uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_DEFAULT);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
@@ -181,7 +146,6 @@
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
-#endif
return 0;
}
diff --git a/docs/readme-espressif.md b/docs/readme-espressif.md
index d8d4065..d07cc05 100644
--- a/docs/readme-espressif.md
+++ b/docs/readme-espressif.md
@@ -238,6 +238,8 @@
The Secure Boot implementation is based on [IDF's Secure Boot V2](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/security/secure-boot-v2.html), is hardware-assisted and RSA based, and has the role for ensuring that only authorized code will be executed on the device. This is done through bootloader signature checking by the ROM bootloader. \
***Note***: ROM bootloader is the First Stage Bootloader, while the Espressif MCUboot port is the Second Stage Bootloader.
+***Note***: Currently on MCUboot Espressif Port, the Secure Boot V2 for ESP32-C2 is not supported yet.
+
### [Building bootloader with Secure Boot](#building-bootloader-with-secure-boot)
In order to build the bootloader with the feature on, the following configurations must be enabled: