blob: 866c42ecbbb8d80a3cb8693ccfd7d047cc26236a [file] [log] [blame]
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02001option(SEMIHOSTING "Test trace using printf" ON)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02002
3if (PLATFORM STREQUAL "FVP")
Christophe Favergeonec574202019-08-09 06:54:05 +01004SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +02005SET(PLATFORMID "FVP")
6list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
7endif()
8
GorgonMeducerf8d8ec82019-11-05 14:09:36 +00009if (PLATFORM STREQUAL "MPS3")
10SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3)
11SET(PLATFORMID "MPS3")
12list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3)
13endif()
14
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020015if (PLATFORM STREQUAL "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010016SET(PLATFORMFOLDER ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020017SET(PLATFORMID "SDSIM")
Christophe Favergeonec574202019-08-09 06:54:05 +010018list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT})
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020019endif()
20
21SET(CORE ARMCM7)
22
Christophe Favergeon512b1482020-02-07 11:25:11 +010023
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020024include(platform)
25
26function(set_platform_core)
Christophe Favergeon26c2f682019-09-06 14:43:32 +010027
28 if(EXPERIMENTAL)
29 experimental_set_platform_core()
30 SET(CORE ${CORE} PARENT_SCOPE)
31 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020032 ###################
33 #
34 # Cortex cortex-m7
35 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020036 if (ARM_CPU MATCHES "^[cC]ortex-[mM]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020037 SET(CORE ARMCM7 PARENT_SCOPE)
38 endif()
39
40 ###################
41 #
42 # Cortex cortex-m4
43 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020044 if (ARM_CPU MATCHES "^[cC]ortex-[mM]4([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020045 SET(CORE ARMCM4 PARENT_SCOPE)
46 endif()
47
48 ###################
49 #
50 # Cortex cortex-m35p
51 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020052 if (ARM_CPU MATCHES "^[cC]ortex-[mM]35([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020053 SET(CORE ARMCM35P PARENT_SCOPE)
54
55 endif()
56
57 ###################
58 #
59 # Cortex cortex-m33
60 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020061 if (ARM_CPU MATCHES "^[cC]ortex-[mM]33([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020062 SET(CORE ARMCM33 PARENT_SCOPE)
63
64 endif()
Christophe Favergeon512b1482020-02-07 11:25:11 +010065
66 ###################
67 #
68 # Cortex cortex-m55
69 #
70 if (ARM_CPU MATCHES "^[cC]ortex-[mM]55([^0-9].*)?$")
71 SET(CORE ARMv81MML PARENT_SCOPE)
72 endif()
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020073
74 ###################
75 #
76 # Cortex cortex-m23
77 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020078 if (ARM_CPU MATCHES "^[cC]ortex-[mM]23([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020079 SET(CORE ARMCM23 PARENT_SCOPE)
80
81 endif()
82
83 ###################
84 #
85 # Cortex cortex-m0+
86 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020087 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0p([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020088 SET(CORE ARMCM0plus PARENT_SCOPE)
89
90 endif()
91
92 ###################
93 #
94 # Cortex cortex-m0
95 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +020096 if (ARM_CPU MATCHES "^[cC]ortex-[mM]0([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +020097 SET(CORE ARMCM0 PARENT_SCOPE)
98
99 endif()
100
101 ###################
102 #
103 # Cortex cortex-a5
104 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200105 if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200106 SET(CORE ARMCA5 PARENT_SCOPE)
107
108 endif()
109
110 ###################
111 #
112 # Cortex cortex-a7
113 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200114 if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200115 SET(CORE ARMCA7 PARENT_SCOPE)
116
117 endif()
118
119 ###################
120 #
121 # Cortex cortex-a9
122 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200123 if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200124 SET(CORE ARMCA9 PARENT_SCOPE)
125
126 endif()
127
128 ###################
129 #
130 # Cortex cortex-a15
131 #
Christophe Favergeonc4c34802019-09-24 14:05:01 +0200132 if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$")
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200133 SET(CORE ARMCA15 PARENT_SCOPE)
134 endif()
135endfunction()
136
137function(core_includes PROJECTNAME)
Christophe Favergeonec574202019-08-09 06:54:05 +0100138 target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include)
Christophe Favergeon3b2a0ee2019-06-12 13:29:14 +0200139endfunction()
140
141function (configplatformForLib PROJECTNAME ROOT)
142 if (SEMIHOSTING)
143 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
144 endif()
145 if (CORTEXM)
146 compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} )
147 else()
148 compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} )
149 endif()
150
151endfunction()
152
153function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER)
154 if (SEMIHOSTING)
155 target_compile_definitions(${PROJECTNAME} PRIVATE SEMIHOSTING)
156 endif()
157
158 configure_platform(${PROJECTNAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
159 SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
160
161 if (CORTEXM)
162 compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} )
163 else()
164 compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} )
165 endif()
166
167endfunction()