Updated version histories in preparation for release 5.4.0.
Change-Id: I4b47d7e0e267d727687ebd8acba5274ec492b2df
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index e0a9a94..e071222 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,48 +8,24 @@
<url>http://www.keil.com/pack/</url>
<releases>
- <release version="5.3.1-dev8">
- Cortex-M1:
- - Added beta ARMCM1 support.
- </release>
- <release version="5.3.1-dev7">
- Generic Arm Device:
- - Reworked ARM device support files.
- - Updated RTOS2 examples.
- - Updated DSP examples.
- - Updated CoreValidation examples.
- </release>
- <release version="5.3.1-dev6">
- Utilities:
- - updated SVDConv and PackChk for Win32 and Linux
- </release>
- <release version="5.3.1-dev5">
+ <release version="5.4.0-rc0">
Aligned pack structure with repository.
The following folders are deprecated:
- - CMSIS/Include/
- - CMSIS/DSP_Lib/
- </release>
- <release version="5.3.1-dev4">
- CMSIS-RTOS2:
- - API 2.1.3 (see revision history for details)
- </release>
- <release version="5.3.1-dev3">
- RTX5 (Cortex-A): updated exception handling
- </release>
- <release version="5.3.1-dev2">
- CMSIS-RTOS2:
- - RTX 5.4.0 (see revision history for details)
- </release>
- <release version="5.3.1-dev1">
+ - CMSIS/Include/
+ - CMSIS/DSP_Lib/
+
CMSIS-Core(M): 5.1.2 (see revision history for details)
+ - Added Cortex-M1 support (beta).
CMSIS-Core(A): 1.1.2 (see revision history for details)
CMSIS-RTOS2:
- - RTX 5.3.1 (see revision history for details)
+ - API 2.1.3 (see revision history for details)
+ - RTX 5.4.0 (see revision history for details)
+ * Updated exception handling on Cortex-A
CMSIS-Driver:
- Flash Driver API V2.2.0
- </release>
- <release version="5.3.1-dev0">
- Patch release scheduled for after EW18.
+ Utilities:
+ - SVDConv 3.3.21
+ - PackChk 1.3.71
</release>
<release version="5.3.0" date="2018-02-22">
Updated Arm company brand.
@@ -103,7 +79,7 @@
- OS Tick API 1.0.0
CMSIS-DSP: 1.5.2 (see revision history for details)
- Fixed GNU Compiler specific diagnostics.
- CMSIS-PACK: 1.5.0 (see revision history for details)
+ CMSIS-Pack: 1.5.0 (see revision history for details)
- added System Description File (*.SDF) Format
CMSIS-Zone: 0.0.1 (Preview)
- Initial specification draft
@@ -122,7 +98,7 @@
- Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
CMSIS-DSP: 1.5.1 (see revision history for details)
- added ARMv8M DSP libraries.
- CMSIS-PACK:1.4.9 (see revision history for details)
+ CMSIS-Pack:1.4.9 (see revision history for details)
- added Pack Index File specification and schema file
</release>
<release version="5.0.0" date="2016-11-11">
@@ -153,14 +129,14 @@
- CMSIS-DAP 1.1.0 (unchanged)
- CMSIS-Driver 2.04.0 (see revision history for details)
- CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details)
- - CMSIS-PACK 1.4.1 (see revision history for details)
+ - CMSIS-Pack 1.4.1 (see revision history for details)
- CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
- CMSIS-SVD 1.3.1 (see revision history for details)
</release>
<release version="4.4.0" date="2015-09-11">
- CMSIS-Core 4.20 (see revision history for details)
- CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details)
- - CMSIS-PACK 1.4.0 (adding memory attributes, algorithm style)
+ - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style)
- CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API)
- CMSIS-RTOS
-- API 1.02 (unchanged)
@@ -172,7 +148,7 @@
- CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions)
- CMSIS-DSP 1.4.5 (see revision history for details)
- CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API)
- - CMSIS-PACK 1.3.3 (Semantic Versioning, Generator extensions)
+ - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions)
- CMSIS-RTOS
-- API 1.02 (unchanged)
-- RTX 4.78 (see revision history for details)
@@ -182,7 +158,7 @@
Adding Cortex-M7 support
- CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files)
- CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues)
- - CMSIS-PACK 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
+ - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
- CMSIS-SVD 1.2 (Cortex-M7 extensions)
- CMSIS-RTOS RTX 4.75 (see revision history for details)
</release>
@@ -2193,7 +2169,7 @@
<components>
<!-- CMSIS-Core component -->
- <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.1" condition="ARMv6_7_8-M Device" >
+ <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2" condition="ARMv6_7_8-M Device" >
<description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
<files>
<!-- CPU independent -->
@@ -2206,7 +2182,7 @@
</files>
</component>
- <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.1" condition="ARMv7-A Device" >
+ <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.2" condition="ARMv7-A Device" >
<description>CMSIS-CORE for Cortex-A</description>
<files>
<!-- CPU independent -->
diff --git a/CMSIS/DoxyGen/Core/src/Overview.txt b/CMSIS/DoxyGen/Core/src/Overview.txt
index 187a7d6..c2a8969 100644
--- a/CMSIS/DoxyGen/Core/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core/src/Overview.txt
@@ -87,6 +87,10 @@
<td>
Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.\n
Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.\n
+ Added support for Cortex-M1 (beta). \n
+ Removed usage of register keyword. \n
+ Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. \n
+ Enhanced MPUv7 API with defines for memory access attributes.\n
</td>
</tr>
<tr>
@@ -106,112 +110,112 @@
<tr>
<td>V5.0.2</td>
<td>
- Added macros \ref \__UNALIGNED_UINT16_READ, \ref \__UNALIGNED_UINT16_WRITE.\n
- Added macros \ref \__UNALIGNED_UINT32_READ, \ref \__UNALIGNED_UINT32_WRITE.\n
- Deprecated macro \ref \__UNALIGNED_UINT32.\n
- Changed \ref version_control_gr macros to be core agnostic. \n
- Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.
+ Added macros \ref \__UNALIGNED_UINT16_READ, \ref \__UNALIGNED_UINT16_WRITE.\n
+ Added macros \ref \__UNALIGNED_UINT32_READ, \ref \__UNALIGNED_UINT32_WRITE.\n
+ Deprecated macro \ref \__UNALIGNED_UINT32.\n
+ Changed \ref version_control_gr macros to be core agnostic. \n
+ Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.
</td>
</tr>
<tr>
<td>V5.0.1</td>
<td>
- Added: macro \ref \__PACKED_STRUCT. \n
- Added: uVisor support. \n
+ Added: macro \ref \__PACKED_STRUCT. \n
+ Added: uVisor support. \n
</td>
</tr>
<tr>
<td>V5.00</td>
<td>
- Added: Cortex-M23, Cortex-M33 support.\n
- Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. \n
- Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. \n
- Reworked: SAU register and functions. \n
- Added: macro \ref \__ALIGNED. \n
- Updated: function \ref SCB_EnableICache. \n
- Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. \n
- Added: macro \ref \__PACKED. \n
- Updated: compiler specific include files. \n
- Updated: core dependant include files. \n
- Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.
+ Added: Cortex-M23, Cortex-M33 support.\n
+ Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. \n
+ Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. \n
+ Reworked: SAU register and functions. \n
+ Added: macro \ref \__ALIGNED. \n
+ Updated: function \ref SCB_EnableICache. \n
+ Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. \n
+ Added: macro \ref \__PACKED. \n
+ Updated: compiler specific include files. \n
+ Updated: core dependant include files. \n
+ Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.
</td>
</tr>
<tr>
<td>V5.00<br>Beta 6</td>
<td>
- Added: SCB_CFSR register bit definitions. \n
- Added: function \ref NVIC_GetEnableIRQ. \n
- Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.
+ Added: SCB_CFSR register bit definitions. \n
+ Added: function \ref NVIC_GetEnableIRQ. \n
+ Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.
</td>
</tr>
<tr>
<td>V5.00<br>Beta 5</td>
<td>
- Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. \n
- Added: DSP libraries build projects to CMSIS pack.
+ Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. \n
+ Added: DSP libraries build projects to CMSIS pack.
</td>
</tr>
<tr>
<td>V5.00<br>Beta 4</td>
<td>
- Updated: ARMv8M device files. \n
- Corrected: ARMv8MBL interrupts. \n
- Reworked: NVIC functions.
+ Updated: ARMv8M device files. \n
+ Corrected: ARMv8MBL interrupts. \n
+ Reworked: NVIC functions.
</td>
</tr>
<tr>
<td>V5.00<br>Beta 2</td>
<td>
- Changed: ARMv8M SAU regions to 8. \n
- Changed: moved function \ref TZ_SAU_Setup to file partition_<device>.h. \n
- Changed: license under Apache-2.0. \n
- Added: check if macro is defined before use. \n
- Corrected: function \ref SCB_DisableDCache. \n
- Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL. \n
- Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.
+ Changed: ARMv8M SAU regions to 8. \n
+ Changed: moved function \ref TZ_SAU_Setup to file partition_<device>.h. \n
+ Changed: license under Apache-2.0. \n
+ Added: check if macro is defined before use. \n
+ Corrected: function \ref SCB_DisableDCache. \n
+ Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL. \n
+ Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.
</td>
</tr>
<tr>
<td>V5.00<br>Beta 1</td>
<td>
- Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.\n
- Renamed: core\_*.h to lower case.\n
- Added: function \ref SCB_GetFPUType to all CMSIS cores.\n
- Added: ARMv8-M support.
- </td>
+ Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.\n
+ Renamed: core\_*.h to lower case.\n
+ Added: function \ref SCB_GetFPUType to all CMSIS cores.\n
+ Added: ARMv8-M support.
+ </td>
</tr>
<tr>
<td>V4.30</td>
<td>
- Corrected: DoxyGen function parameter comments.\n
- Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).\n
- Corrected: GCC toolchain: suppressed irrelevant compiler warnings.\n
- Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
+ Corrected: DoxyGen function parameter comments.\n
+ Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).\n
+ Corrected: GCC toolchain: suppressed irrelevant compiler warnings.\n
+ Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
</td>
</tr>
<tr>
<td>V4.20</td>
<td>
- Corrected: MISRA-C:2004 violations. \n
- Corrected: predefined macro for TI CCS Compiler. \n
- Corrected: function \ref __SHADD16 in arm_math.h. \n
- Updated: cache functions for Cortex-M7. \n
- Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h. \n
- Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX. \n
+ Corrected: MISRA-C:2004 violations. \n
+ Corrected: predefined macro for TI CCS Compiler. \n
+ Corrected: function \ref __SHADD16 in arm_math.h. \n
+ Updated: cache functions for Cortex-M7. \n
+ Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h. \n
+ Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX. \n
Corrected: potential bug in function \ref __SHADD16.
</td>
</tr>
<tr>
<td>V4.10</td>
<td>
- Corrected: MISRA-C:2004 violations. \n
- Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB. \n
- Corrected: register definitions for ITCMCR register. \n
- Corrected: register definitions for \ref CONTROL_Type register. \n
- Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h. \n
- Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register. \n
- Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h. \n
- Added: intrinsic functions \ref __RBIT, \ref __CLZ for Cortex-M0/CortexM0+. \n
+ Corrected: MISRA-C:2004 violations. \n
+ Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB. \n
+ Corrected: register definitions for ITCMCR register. \n
+ Corrected: register definitions for \ref CONTROL_Type register. \n
+ Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h. \n
+ Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register. \n
+ Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h. \n
+ Added: intrinsic functions \ref __RBIT, \ref __CLZ for Cortex-M0/CortexM0+. \n
</td>
</tr>
<tr>
@@ -227,20 +231,22 @@
</tr>
<tr>
<td>V3.30</td>
- <td>Added: COSMIC tool chain support.\n
- Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.\n
- Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.\n
- Corrected: GCC/CLang warnings.\n
+ <td>
+ Added: COSMIC tool chain support.\n
+ Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.\n
+ Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.\n
+ Corrected: GCC/CLang warnings.\n
</td>
</tr>
<tr>
<td>V3.20</td>
- <td>Added: \ref __BKPT instruction intrinsic.\n
- Added: \ref __SMMLA instruction intrinsic for Cortex-M4.\n
- Corrected: \ref ITM_SendChar.\n
- Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.\n
- Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. \n
- Corrected: rework of in-line assembly functions to remove potential compiler warnings.\n
+ <td>
+ Added: \ref __BKPT instruction intrinsic.\n
+ Added: \ref __SMMLA instruction intrinsic for Cortex-M4.\n
+ Corrected: \ref ITM_SendChar.\n
+ Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.\n
+ Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. \n
+ Corrected: rework of in-line assembly functions to remove potential compiler warnings.\n
</td>
</tr>
<tr>
@@ -249,7 +255,8 @@
</tr>
<tr>
<td>V3.00</td>
- <td>Added support for GNU GCC ARM Embedded Compiler. \n
+ <td>
+ Added support for GNU GCC ARM Embedded Compiler. \n
Added function \ref __ROR.\n
Added \ref regMap_pg for TPIU, DWT. \n
Added support for \ref core_config_sect "SC000 and SC300 processors".\n
@@ -260,11 +267,12 @@
</tr>
<tr>
<td>V2.10</td>
- <td>Updated documentation.\n
- Updated CMSIS core include files.\n
- Changed CMSIS/Device folder structure.\n
- Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.\n
- Reworked CMSIS DSP library examples.
+ <td>
+ Updated documentation.\n
+ Updated CMSIS core include files.\n
+ Changed CMSIS/Device folder structure.\n
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.\n
+ Reworked CMSIS DSP library examples.
</td>
</tr>
<tr>
@@ -273,11 +281,12 @@
</tr>
<tr>
<td>V1.30</td>
- <td>Reworked Startup Concept.\n
- Added additional Debug Functionality.\n
- Changed folder structure.\n
- Added doxygen comments.\n
- Added definitions for bit.
+ <td>
+ Reworked Startup Concept.\n
+ Added additional Debug Functionality.\n
+ Changed folder structure.\n
+ Added doxygen comments.\n
+ Added definitions for bit.
</td>
</tr>
<tr>
diff --git a/CMSIS/DoxyGen/Core_A/src/Overview.txt b/CMSIS/DoxyGen/Core_A/src/Overview.txt
index 6deac40..b91fd72 100644
--- a/CMSIS/DoxyGen/Core_A/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Overview.txt
@@ -71,6 +71,7 @@
<td>
<ul>
<li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
+ <li>Fixed co-processor register access macros for Arm Compiler 5.</li>
</ul>
</td>
</tr>
diff --git a/CMSIS/DoxyGen/General/general.dxy b/CMSIS/DoxyGen/General/general.dxy
index 7e7c9a8..778728d 100644
--- a/CMSIS/DoxyGen/General/general.dxy
+++ b/CMSIS/DoxyGen/General/general.dxy
@@ -38,7 +38,7 @@
# could be handy for archiving the generated documentation or if some version
# control system is used.
-PROJECT_NUMBER = "Version 5.3.0"
+PROJECT_NUMBER = "Version 5.4.0"
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
diff --git a/CMSIS/DoxyGen/General/src/introduction.txt b/CMSIS/DoxyGen/General/src/introduction.txt
index 16ad107..6f54254 100644
--- a/CMSIS/DoxyGen/General/src/introduction.txt
+++ b/CMSIS/DoxyGen/General/src/introduction.txt
@@ -194,6 +194,22 @@
<th>Description</th>
</tr>
<tr>
+ <td>5.4.0</td>
+ <td>
+ - CMSIS-Core (Cortex-M) 5.1.2 Minor fixes and slight enhancements, e.g. beta for Cortex-M1.
+ - CMSIS-Core (Cortex-A) 1.1.2 Minor fixes.
+ - CMSIS-Driver 2.6.0 (unchanged)
+ - CMSIS-DSP 1.5.2 (unchanged)
+ - CMSIS-NN 1.0.0 Initial contribution of Neural Network Library.
+ - CMSIS-RTOS 2.1.3 Relaxed interrupt usage.
+ - RTX 5.4.0 (see revision history)
+ - CMSIS-Pack 1.5.0 (unchanged)
+ - CMSIS-SVD 1.3.3 (unchanged)
+ - CMSIS-DAP 2.0.0 Communication via WinUSB to achieve high-speed transfer rates.
+ - CMSIS-Zone 0.0.1 (unchanged)
+ </td>
+ </tr>
+ <tr>
<td>5.3.0</td>
<td>
- CMSIS-Core (Cortex-M) 5.1.1
diff --git a/README.md b/README.md
index b968374..c90c9a6 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
# CMSIS Version 5
-The branch *master* of this GitHub repository contains the CMSIS Version 5.3.0. The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
+The branch *master* of this GitHub repository contains the CMSIS Version 5.4.0. The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5.
diff --git a/linter.py b/linter.py
index 2873116..bb03ee3 100644
--- a/linter.py
+++ b/linter.py
@@ -94,15 +94,16 @@
return self._revhistory_(file, skip)
def introduction_txt(self, file, component = None):
- if not component:
- return None
-
table = self._cmtable_(file)
- if table is not None:
+ if table is None:
+ return None
+
+ if component:
m = re.search(re.escape(component)+"\s+[Vv]?(\d+.\d+(.\d+)?)", table[1][1].text, re.MULTILINE)
if m:
return SemanticVersion(m.group(1))
- return None
+ else:
+ return SemanticVersion(table[1][0].text)
def dap_txt(self, file, skip = 0):
return self._revhistory_(file, skip)
@@ -158,6 +159,7 @@
v = self.pack_version()
self.verify_version("README.md", v)
self.verify_version("CMSIS/DoxyGen/General/general.dxy", v)
+ self.verify_version("CMSIS/DoxyGen/General/src/introduction.txt", v)
def check_corem(self):
"""CMSIS-Core(M) version"""
@@ -245,9 +247,9 @@
if not hv:
self.verify_version(f.location(), cv)
if hv:
- self.verify_version(f.location(), hv)
+ self.verify_version(f.location(), SemanticVersion(hv))
- def check_doc(self, pattern="./gen_pack/CMSIS/Documentation/**/*.html"):
+ def check_doc(self, pattern="./CMSIS/Documentation/**/*.html"):
"""Documentation"""
self.debug("Using pattern '%s'", pattern)
for html in iglob(pattern, recursive=True):