CMSIS-DSP: Add MPS3 Cortex-M33 support to Testing platform
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/ARMCM33_DSP_FP_config.txt b/CMSIS/DSP/Platforms/MPS3/ARMCM33/ARMCM33_DSP_FP_config.txt
new file mode 100644
index 0000000..d52478f
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/ARMCM33_DSP_FP_config.txt
@@ -0,0 +1,169 @@
+# Parameters:
+# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
+cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
+cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
+cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
+cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
+cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
+cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
+cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
+cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
+cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
+idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
+cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
+cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
+cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
+cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
+cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
+fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
+fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
+fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
+fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
+fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
+fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
+fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
+fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
+fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
+fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
+fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
+fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
+fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
+fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
+fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
+fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
+fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
+fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
+#----------------------------------------------------------------------------------------------
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33.h
new file mode 100644
index 0000000..9593c61
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33.h
@@ -0,0 +1,130 @@
+/**************************************************************************//**
+ * @file ARMCM33.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, without TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM33_H
+#define ARMCM33_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 0U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+
+#include "core_cm33.h" /* Processor and core peripherals */
+#include "system_ARMCM33.h" /* System Header */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM33_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP.h
new file mode 100644
index 0000000..d303bea
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP.h
@@ -0,0 +1,130 @@
+/**************************************************************************//**
+ * @file ARMCM33_DSP_FP.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension)
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM33_DSP_FP_H
+#define ARMCM33_DSP_FP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 0U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+
+#include "core_cm33.h" /* Processor and core peripherals */
+#include "system_ARMCM33.h" /* System Header */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM33_DSP_FP_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
new file mode 100644
index 0000000..0d78c79
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
@@ -0,0 +1,130 @@
+/**************************************************************************//**
+ * @file ARMCM33_DSP_FP_TZ.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM33_DSP_FP_TZ_H
+#define ARMCM33_DSP_FP_TZ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+
+#include "core_cm33.h" /* Processor and core peripherals */
+#include "system_ARMCM33.h" /* System Header */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM33_DSP_FP_TZ_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_TZ.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_TZ.h
new file mode 100644
index 0000000..3912a11
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/ARMCM33_TZ.h
@@ -0,0 +1,130 @@
+/**************************************************************************//**
+ * @file ARMCM33_TZ.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM33_TZ_H
+#define ARMCM33_TZ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+
+#include "core_cm33.h" /* Processor and core peripherals */
+#include "system_ARMCM33.h" /* System Header */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM33_TZ_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/system_ARMCM33.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/system_ARMCM33.h
new file mode 100644
index 0000000..42d07ec
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Include/system_ARMCM33.h
@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file system_ARMCM33.h
+ * @brief CMSIS Device System Header File for
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMCM33_H
+#define SYSTEM_ARMCM33_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM33_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/lnk.sct b/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/lnk.sct
new file mode 100644
index 0000000..eb3cdf3
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/lnk.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> RAM1 Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM1 Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM1_BASE 0x10000000
+#define __RAM1_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM1 Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM1 Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM2_BASE 0x20000000
+#define __RAM2_SIZE 0x00008000
+
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00040000
+#define RW_RAM2_SIZE (__RAM2_SIZE - __STACK_SIZE)
+
+LR_ROM1 __RAM1_BASE __RAM1_SIZE { ; load region size_region
+ ER_ROM1 +0 { ; load address = execution address
+ *.o (RESET, +First)
+ * (InRoot$$Sections)
+ ; *(Veneer$$CMSE) ; uncomment for secure applications
+ * (+RO)
+ }
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __RAM2_BASE ALIGN 8 EMPTY __STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAM2 +0 RW_RAM2_SIZE {
+ * (+RW +ZI)
+ }
+
+
+
+}
+
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/mem_ARMCM33.h b/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/mem_ARMCM33.h
new file mode 100644
index 0000000..19ec60e
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/LinkScripts/AC6/mem_ARMCM33.h
@@ -0,0 +1,38 @@
+/**************************************************************************//**
+ * @file mem_ARMCM7.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.1.0
+ * @date 15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCM33_H
+#define __MEM_ARMCM33_H
+
+
+
+#define STACK_SIZE 0x00003000
+#define HEAP_SIZE 0x00100000
+
+
+
+#endif /* __MEM_ARMCM33_H */
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/Startup/AC6/startup_ARMCM33.s b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Startup/AC6/startup_ARMCM33.s
new file mode 100644
index 0000000..8dfdb25
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/Startup/AC6/startup_ARMCM33.s
@@ -0,0 +1,125 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM33.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM33 Device
+; * @version V5.4.0
+; * @date 12. December 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD SecureFault_Handler ; -9 Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+ END
diff --git a/CMSIS/DSP/Platforms/MPS3/ARMCM33/system_ARMCM33.c b/CMSIS/DSP/Platforms/MPS3/ARMCM33/system_ARMCM33.c
new file mode 100644
index 0000000..2988f34
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/ARMCM33/system_ARMCM33.c
@@ -0,0 +1,722 @@
+/**************************************************************************//**
+ * @file system_ARMCM33.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <rt_sys.h>
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+#include <stdio.h>
+
+
+#include "cmsis_compiler.h"
+
+//! \name The macros to identify the compiler
+//! @{
+
+//! \note for IAR
+#ifdef __IS_COMPILER_IAR__
+# undef __IS_COMPILER_IAR__
+#endif
+#if defined(__IAR_SYSTEMS_ICC__)
+# define __IS_COMPILER_IAR__ 1
+#endif
+
+
+
+
+//! \note for arm compiler 5
+#ifdef __IS_COMPILER_ARM_COMPILER_5__
+# undef __IS_COMPILER_ARM_COMPILER_5__
+#endif
+#if ((__ARMCC_VERSION >= 5000000) && (__ARMCC_VERSION < 6000000))
+# define __IS_COMPILER_ARM_COMPILER_5__ 1
+#endif
+//! @}
+
+//! \note for arm compiler 6
+#ifdef __IS_COMPILER_ARM_COMPILER_6__
+# undef __IS_COMPILER_ARM_COMPILER_6__
+#endif
+#if ((__ARMCC_VERSION >= 6000000) && (__ARMCC_VERSION < 7000000))
+# define __IS_COMPILER_ARM_COMPILER_6__ 1
+#endif
+
+#ifdef __IS_COMPILER_LLVM__
+# undef __IS_COMPILER_LLVM__
+#endif
+#if defined(__clang__) && !__IS_COMPILER_ARM_COMPILER_6__
+# define __IS_COMPILER_LLVM__ 1
+#else
+//! \note for gcc
+#ifdef __IS_COMPILER_GCC__
+# undef __IS_COMPILER_GCC__
+#endif
+#if defined(__GNUC__) && !(__IS_COMPILER_ARM_COMPILER_6__ || __IS_COMPILER_LLVM__)
+# define __IS_COMPILER_GCC__ 1
+#endif
+//! @}
+#endif
+//! @}
+
+#define SAFE_ATOM_CODE(...) \
+{ \
+ uint32_t wOrig = __disable_irq(); \
+ __VA_ARGS__; \
+ __set_PRIMASK(wOrig); \
+}
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M */
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+//#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (32000000UL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __VECTOR_TABLE;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+
+/*----------------------------------------------------------------------------
+ UART functions
+ *----------------------------------------------------------------------------*/
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
+
+/* CMSDK_UART STATE Register Definitions */
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
+
+/* CMSDK_UART CTRL Register Definitions */
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+/* CMSDK_UART BAUDDIV Register Definitions */
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define CMSDK_UART0_BASE_ADDRESS (0x41303000ul)
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE_ADDRESS)
+
+
+
+void uart_config(uint32_t wUARTFrequency)
+{
+ CMSDK_UART0->CTRL = 0; /* Disable UART when changing configuration */
+ CMSDK_UART0->BAUDDIV = wUARTFrequency / 115200ul; /* 25MHz / 38400 = 651 */
+ CMSDK_UART0->CTRL = CMSDK_UART_CTRL_TXEN_Msk|CMSDK_UART_CTRL_RXEN_Msk;
+}
+
+int stdout_putchar(char txchar)
+{
+ if (txchar == 10) stdout_putchar((char) 13);
+
+ while(CMSDK_UART0->STATE & CMSDK_UART_STATE_TXBF_Msk);
+ CMSDK_UART0->DATA = (uint32_t)txchar;
+
+ return (int) txchar;
+}
+
+int stderr_putchar(char txchar)
+{
+ return stdout_putchar(txchar);
+}
+
+void ttywrch (int ch)
+{
+ stdout_putchar(ch);
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__VECTOR_TABLE;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+ uart_config(SYSTEM_CLOCK);
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+
+__attribute__((constructor(255)))
+void platform_init(void)
+{
+ printf("\r\nYamin Cortex-M33 Generic Template...\r\n");
+ printf("\r\n_[TEST START]____________________________________________________\r\n");
+}
+
+
+#if __IS_COMPILER_ARM_COMPILER_6__
+__asm(".global __use_no_semihosting\n\t");
+# ifndef __MICROLIB
+__asm(".global __ARM_use_no_argv\n\t");
+# endif
+#endif
+
+/**
+ Writes the character specified by c (converted to an unsigned char) to
+ the output stream pointed to by stream, at the position indicated by the
+ associated file position indicator (if defined), and advances the
+ indicator appropriately. If the file position indicator is not defined,
+ the character is appended to the output stream.
+
+ \param[in] c Character
+ \param[in] stream Stream handle
+
+ \return The character written. If a write error occurs, the error
+ indicator is set and fputc returns EOF.
+*/
+__attribute__((weak))
+int fputc (int c, FILE * stream)
+{
+ if (stream == &__stdout) {
+ return (stdout_putchar(c));
+ }
+
+ if (stream == &__stderr) {
+ return (stderr_putchar(c));
+ }
+
+ return (-1);
+}
+
+/* IO device file handles. */
+#define FH_STDIN 0x8001
+#define FH_STDOUT 0x8002
+#define FH_STDERR 0x8003
+
+const char __stdin_name[] = ":STDIN";
+const char __stdout_name[] = ":STDOUT";
+const char __stderr_name[] = ":STDERR";
+
+#define RETARGET_SYS 1
+#define RTE_Compiler_IO_STDOUT 1
+#define RTE_Compiler_IO_STDERR 1
+/**
+ Defined in rt_sys.h, this function opens a file.
+
+ The _sys_open() function is required by fopen() and freopen(). These
+ functions in turn are required if any file input/output function is to
+ be used.
+ The openmode parameter is a bitmap whose bits mostly correspond directly to
+ the ISO mode specification. Target-dependent extensions are possible, but
+ freopen() must also be extended.
+
+ \param[in] name File name
+ \param[in] openmode Mode specification bitmap
+
+ \return The return value is ?1 if an error occurs.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+FILEHANDLE _sys_open (const char *name, int openmode) {
+#if (!defined(RTE_Compiler_IO_File))
+ (void)openmode;
+#endif
+
+ if (name == NULL) {
+ return (-1);
+ }
+
+ if (name[0] == ':') {
+ if (strcmp(name, ":STDIN") == 0) {
+ return (FH_STDIN);
+ }
+ if (strcmp(name, ":STDOUT") == 0) {
+ return (FH_STDOUT);
+ }
+ if (strcmp(name, ":STDERR") == 0) {
+ return (FH_STDERR);
+ }
+ return (-1);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_open(name, openmode));
+#endif
+#else
+ return (-1);
+#endif
+}
+#endif
+
+
+/**
+ Defined in rt_sys.h, this function closes a file previously opened
+ with _sys_open().
+
+ This function must be defined if any input/output function is to be used.
+
+ \param[in] fh File handle
+
+ \return The return value is 0 if successful. A nonzero value indicates
+ an error.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_close (FILEHANDLE fh) {
+
+ switch (fh) {
+ case FH_STDIN:
+ return (0);
+ case FH_STDOUT:
+ return (0);
+ case FH_STDERR:
+ return (0);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_close(fh));
+#endif
+#else
+ return (-1);
+#endif
+}
+#endif
+
+
+/**
+ Defined in rt_sys.h, this function writes the contents of a buffer to a file
+ previously opened with _sys_open().
+
+ \note The mode parameter is here for historical reasons. It contains
+ nothing useful and must be ignored.
+
+ \param[in] fh File handle
+ \param[in] buf Data buffer
+ \param[in] len Data length
+ \param[in] mode Ignore this parameter
+
+ \return The return value is either:
+ - a positive number representing the number of characters not
+ written (so any nonzero return value denotes a failure of
+ some sort)
+ - a negative number indicating an error.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) {
+#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR))
+ int ch;
+#elif (!defined(RTE_Compiler_IO_File))
+ (void)buf;
+ (void)len;
+#endif
+ (void)mode;
+
+ switch (fh) {
+ case FH_STDIN:
+ return (-1);
+ case FH_STDOUT:
+#ifdef RTE_Compiler_IO_STDOUT
+ for (; len; len--) {
+ ch = *buf++;
+#if (STDOUT_CR_LF != 0)
+ if (ch == '\n') stdout_putchar('\r');
+#endif
+ stdout_putchar(ch);
+ }
+#endif
+ return (0);
+ case FH_STDERR:
+#ifdef RTE_Compiler_IO_STDERR
+ for (; len; len--) {
+ ch = *buf++;
+#if (STDERR_CR_LF != 0)
+ if (ch == '\n') stderr_putchar('\r');
+#endif
+ stderr_putchar(ch);
+ }
+#endif
+ return (0);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_write(fh, buf, len));
+#endif
+#else
+ return (-1);
+#endif
+}
+#endif
+
+
+/**
+ Defined in rt_sys.h, this function reads the contents of a file into a buffer.
+
+ Reading up to and including the last byte of data does not turn on the EOF
+ indicator. The EOF indicator is only reached when an attempt is made to read
+ beyond the last byte of data. The target-independent code is capable of
+ handling:
+ - the EOF indicator being returned in the same read as the remaining bytes
+ of data that precede the EOF
+ - the EOF indicator being returned on its own after the remaining bytes of
+ data have been returned in a previous read.
+
+ \note The mode parameter is here for historical reasons. It contains
+ nothing useful and must be ignored.
+
+ \param[in] fh File handle
+ \param[in] buf Data buffer
+ \param[in] len Data length
+ \param[in] mode Ignore this parameter
+
+ \return The return value is one of the following:
+ - The number of bytes not read (that is, len - result number of
+ bytes were read).
+ - An error indication.
+ - An EOF indicator. The EOF indication involves the setting of
+ 0x80000000 in the normal result.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) {
+#ifdef RTE_Compiler_IO_STDIN
+ int ch;
+#elif (!defined(RTE_Compiler_IO_File))
+ (void)buf;
+ (void)len;
+#endif
+ (void)mode;
+
+ switch (fh) {
+ case FH_STDIN:
+#ifdef RTE_Compiler_IO_STDIN
+ ch = stdin_getchar();
+ if (ch < 0) {
+ return ((int)(len | 0x80000000U));
+ }
+ *buf++ = (uint8_t)ch;
+#if (STDIN_ECHO != 0)
+ stdout_putchar(ch);
+#endif
+ len--;
+ return ((int)(len));
+#else
+ return ((int)(len | 0x80000000U));
+#endif
+ case FH_STDOUT:
+ return (-1);
+ case FH_STDERR:
+ return (-1);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_read(fh, buf, len));
+#endif
+#else
+ return (-1);
+#endif
+}
+#endif
+
+
+
+
+
+/**
+ Defined in rt_sys.h, this function determines if a file handle identifies
+ a terminal.
+
+ When a file is connected to a terminal device, this function is used to
+ provide unbuffered behavior by default (in the absence of a call to
+ set(v)buf) and to prohibit seeking.
+
+ \param[in] fh File handle
+
+ \return The return value is one of the following values:
+ - 0: There is no interactive device.
+ - 1: There is an interactive device.
+ - other: An error occurred.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_istty (FILEHANDLE fh) {
+
+ switch (fh) {
+ case FH_STDIN:
+ return (1);
+ case FH_STDOUT:
+ return (1);
+ case FH_STDERR:
+ return (1);
+ }
+
+ return (0);
+}
+#endif
+
+
+/**
+ Defined in rt_sys.h, this function puts the file pointer at offset pos from
+ the beginning of the file.
+
+ This function sets the current read or write position to the new location pos
+ relative to the start of the current file fh.
+
+ \param[in] fh File handle
+ \param[in] pos File pointer offset
+
+ \return The result is:
+ - non-negative if no error occurs
+ - negative if an error occurs
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_seek (FILEHANDLE fh, long pos) {
+#if (!defined(RTE_Compiler_IO_File))
+ (void)pos;
+#endif
+
+ switch (fh) {
+ case FH_STDIN:
+ return (-1);
+ case FH_STDOUT:
+ return (-1);
+ case FH_STDERR:
+ return (-1);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_seek(fh, (uint32_t)pos));
+#endif
+#else
+ return (-1);
+#endif
+}
+#endif
+
+
+/**
+ Defined in rt_sys.h, this function returns the current length of a file.
+
+ This function is used by _sys_seek() to convert an offset relative to the
+ end of a file into an offset relative to the beginning of the file.
+ You do not have to define _sys_flen() if you do not intend to use fseek().
+ If you retarget at system _sys_*() level, you must supply _sys_flen(),
+ even if the underlying system directly supports seeking relative to the
+ end of a file.
+
+ \param[in] fh File handle
+
+ \return This function returns the current length of the file fh,
+ or a negative error indicator.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+long _sys_flen (FILEHANDLE fh) {
+
+ switch (fh) {
+ case FH_STDIN:
+ return (0);
+ case FH_STDOUT:
+ return (0);
+ case FH_STDERR:
+ return (0);
+ }
+
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+ return (__sys_flen(fh));
+#endif
+#else
+ return (0);
+#endif
+}
+#endif
+
+#define log_str(...) \
+ do { \
+ const char *pchSrc = __VA_ARGS__; \
+ uint_fast16_t hwSize = sizeof(__VA_ARGS__); \
+ do { \
+ stdout_putchar(*pchSrc++); \
+ } while(--hwSize); \
+ } while(0)
+
+
+void _sys_exit(int n)
+{
+ (void)n;
+ log_str("\r\n");
+ log_str("_[TEST COMPLETE]_________________________________________________\r\n");
+ log_str("\r\n\r\n");
+
+ while(1);
+}
+
+extern void ttywrch (int ch);
+__attribute__((weak))
+void _ttywrch (int ch)
+{
+ ttywrch(ch);
+}
+
diff --git a/CMSIS/DSP/Platforms/MPS3/platform.cmake b/CMSIS/DSP/Platforms/MPS3/platform.cmake
new file mode 100644
index 0000000..8a097de
--- /dev/null
+++ b/CMSIS/DSP/Platforms/MPS3/platform.cmake
@@ -0,0 +1,2 @@
+function(configure_platform PROJECTNAME ROOT CORE PLATFORMFOLDER)
+endfunction()
\ No newline at end of file
diff --git a/CMSIS/DSP/configPlatform.cmake b/CMSIS/DSP/configPlatform.cmake
index 95b2443..d6ca4e8 100644
--- a/CMSIS/DSP/configPlatform.cmake
+++ b/CMSIS/DSP/configPlatform.cmake
@@ -6,6 +6,12 @@
list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/FVP)
endif()
+if (PLATFORM STREQUAL "MPS3")
+SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/MPS3)
+SET(PLATFORMID "MPS3")
+list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/MPS3)
+endif()
+
if (PLATFORM STREQUAL "SDSIM")
SET(PLATFORMFOLDER ${SDSIMROOT})
SET(PLATFORMID "SDSIM")