Added Cortex-M35P device Support.
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index f95bd99..0bf0dc9 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -10,6 +10,7 @@
<releases>
<release version="5.4.1-dev0">
Active development ...
+ Added Cortex-M35P device support.
</release>
<release version="5.4.0" date="2018-08-01">
Aligned pack structure with repository.
@@ -458,6 +459,54 @@
</device>
</family>
+ <!-- ****************************** Cortex-M35P ****************************** -->
+ <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
+ <!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
+ <description>
+The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
+class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
+ </description>
+
+ <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
+ <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
+ <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
+ <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
+ <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
+ <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
+
+ <device Dname="ARMCM35P">
+ <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
+ <description>
+ no DSP Instructions, no Floating Point Unit, no TrustZone
+ </description>
+ <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
+ </device>
+
+ <device Dname="ARMCM35P_TZ">
+ <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
+ <description>
+ no DSP Instructions, no Floating Point Unit, TrustZone
+ </description>
+ <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
+ </device>
+
+ <device Dname="ARMCM35P_DSP_FP">
+ <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
+ <description>
+ DSP Instructions, Single Precision Floating Point Unit, no TrustZone
+ </description>
+ <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
+ </device>
+
+ <device Dname="ARMCM35P_DSP_FP_TZ">
+ <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
+ <description>
+ DSP Instructions, Single Precision Floating Point Unit, TrustZone
+ </description>
+ <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
+ </device>
+ </family>
+
<!-- ****************************** ARMSC000 ****************************** -->
<family Dfamily="ARM SC000" Dvendor="ARM:82">
<description>
@@ -808,6 +857,7 @@
<accept Dcore="ARMV8MML"/>
<accept Dcore="Cortex-M23"/>
<accept Dcore="Cortex-M33"/>
+ <accept Dcore="Cortex-M35P"/>
</condition>
<condition id="ARMv8-M TZ Device">
<description>Armv8-M architecture based device with TrustZone</description>
@@ -887,6 +937,14 @@
<description>Cortex-M33 processor based device using Floating Point Unit</description>
<require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
</condition>
+ <condition id="CM35P">
+ <description>Cortex-M35P processor based device</description>
+ <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="CM35P_FP">
+ <description>Cortex-M35P processor based device using Floating Point Unit</description>
+ <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
+ </condition>
<condition id="ARMv8MBL">
<description>Armv8-M Baseline processor based device</description>
<require Dcore="ARMV8MBL"/>
@@ -918,6 +976,23 @@
<require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
</condition>
+ <condition id="CM35P_NODSP_NOFPU">
+ <description>CM35P, no DSP, no FPU</description>
+ <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU">
+ <description>CM35P, DSP, no FPU</description>
+ <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP">
+ <description>CM35P, no DSP, SP FPU</description>
+ <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
+ </condition>
+ <condition id="CM35P_DSP_SP">
+ <description>CM35P, DSP, SP FPU</description>
+ <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
+ </condition>
+
<condition id="ARMv8MML_NODSP_NOFPU">
<description>Armv8-M Mainline, no DSP, no FPU</description>
<require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
@@ -1191,6 +1266,79 @@
<require Dendian="Little-endian"/>
</condition>
+ <condition id="CM35P_ARMCC">
+ <description>Cortex-M35P processor based device for the Arm Compiler</description>
+ <require condition="CM35P"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_LE_ARMCC">
+ <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
+ <require condition="CM35P_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_BE_ARMCC">
+ <description>Cortex-M35P processor based device in big endian mode for the Arm Compiler</description>
+ <require condition="CM35P_ARMCC"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_FP_ARMCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
+ <require condition="CM35P_FP"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_FP_LE_ARMCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
+ <require condition="CM35P_FP_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_FP_BE_ARMCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
+ <require condition="CM35P_FP_ARMCC"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_NODSP_NOFPU_ARMCC">
+ <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_ARMCC">
+ <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
+ <require condition="CM35P_DSP_NOFPU"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_ARMCC">
+ <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
+ <require condition="CM35P_NODSP_SP"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_ARMCC">
+ <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
+ <require condition="CM35P_DSP_SP"/>
+ <require Tcompiler="ARMCC"/>
+ </condition>
+ <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
+ <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
+ <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
+ <require condition="CM35P_DSP_NOFPU_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_LE_ARMCC">
+ <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
+ <require condition="CM35P_NODSP_SP_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_LE_ARMCC">
+ <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
+ <require condition="CM35P_DSP_SP_ARMCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+
<condition id="ARMv8MBL_ARMCC">
<description>Armv8-M Baseline processor based device for the Arm Compiler</description>
<require condition="ARMv8MBL"/>
@@ -1520,6 +1668,79 @@
<require Dendian="Little-endian"/>
</condition>
+ <condition id="CM35P_GCC">
+ <description>Cortex-M35P processor based device for the GCC Compiler</description>
+ <require condition="CM35P"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_LE_GCC">
+ <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
+ <require condition="CM35P_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_BE_GCC">
+ <description>Cortex-M35P processor based device in big endian mode for the GCC Compiler</description>
+ <require condition="CM35P_GCC"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_FP_GCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
+ <require condition="CM35P_FP"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_FP_LE_GCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+ <require condition="CM35P_FP_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_FP_BE_GCC">
+ <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+ <require condition="CM35P_FP_GCC"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_NODSP_NOFPU_GCC">
+ <description>CM35P, no DSP, no FPU, GCC Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_GCC">
+ <description>CM35P, DSP, no FPU, GCC Compiler</description>
+ <require condition="CM35P_DSP_NOFPU"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_GCC">
+ <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
+ <require condition="CM35P_NODSP_SP"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_GCC">
+ <description>CM35P, DSP, SP FPU, GCC Compiler</description>
+ <require condition="CM35P_DSP_SP"/>
+ <require Tcompiler="GCC"/>
+ </condition>
+ <condition id="CM35P_NODSP_NOFPU_LE_GCC">
+ <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_LE_GCC">
+ <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
+ <require condition="CM35P_DSP_NOFPU_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_LE_GCC">
+ <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
+ <require condition="CM35P_NODSP_SP_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_LE_GCC">
+ <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
+ <require condition="CM35P_DSP_SP_GCC"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+
<condition id="ARMv8MBL_GCC">
<description>Armv8-M Baseline processor based device for the GCC Compiler</description>
<require condition="ARMv8MBL"/>
@@ -1849,6 +2070,79 @@
<require Dendian="Little-endian"/>
</condition>
+ <condition id="CM35P_IAR">
+ <description>Cortex-M35P processor based device for the IAR Compiler</description>
+ <require condition="CM35P"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_LE_IAR">
+ <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
+ <require condition="CM35P_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_BE_IAR">
+ <description>Cortex-M35P processor based device in big endian mode for the IAR Compiler</description>
+ <require condition="CM35P_IAR"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_FP_IAR">
+ <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
+ <require condition="CM35P_FP"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_FP_LE_IAR">
+ <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+ <require condition="CM35P_FP_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_FP_BE_IAR">
+ <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+ <require condition="CM35P_FP_IAR"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+
+ <condition id="CM35P_NODSP_NOFPU_IAR">
+ <description>CM35P, no DSP, no FPU, IAR Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_IAR">
+ <description>CM35P, DSP, no FPU, IAR Compiler</description>
+ <require condition="CM35P_DSP_NOFPU"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_IAR">
+ <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
+ <require condition="CM35P_NODSP_SP"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_IAR">
+ <description>CM35P, DSP, SP FPU, IAR Compiler</description>
+ <require condition="CM35P_DSP_SP"/>
+ <require Tcompiler="IAR"/>
+ </condition>
+ <condition id="CM35P_NODSP_NOFPU_LE_IAR">
+ <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
+ <require condition="CM35P_NODSP_NOFPU_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_NOFPU_LE_IAR">
+ <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
+ <require condition="CM35P_DSP_NOFPU_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_NODSP_SP_LE_IAR">
+ <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
+ <require condition="CM35P_NODSP_SP_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="CM35P_DSP_SP_LE_IAR">
+ <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
+ <require condition="CM35P_DSP_SP_IAR"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+
<condition id="ARMv8MBL_IAR">
<description>Armv8-M Baseline processor based device for the IAR Compiler</description>
<require condition="ARMv8MBL"/>
@@ -2028,6 +2322,17 @@
<require condition="GCC"/>
</condition>
+ <condition id="ARMCM35P CMSIS">
+ <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
+ <require Dvendor="ARM:82" Dname="ARMCM35P*"/>
+ <require Cclass="CMSIS" Cgroup="CORE"/>
+ </condition>
+ <condition id="ARMCM35P CMSIS GCC">
+ <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core requiring GCC</description>
+ <require condition="ARMCM35P CMSIS"/>
+ <require condition="GCC"/>
+ </condition>
+
<condition id="ARMSC000 CMSIS">
<description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC000"/>
@@ -2413,6 +2718,36 @@
</files>
</component>
+ <!-- Cortex-M35P -->
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS">
+ <description>System and Startup for Generic Arm Cortex-M35P device</description>
+ <files>
+ <!-- include folder / device header file -->
+ <file category="include" name="Device/ARM/ARMCM35P/Include/"/>
+ <!-- startup / system file -->
+ <file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.s" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S" version="1.0.0" attr="config" condition="GCC"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>
+ <file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s" version="1.0.0" attr="config" condition="IAR"/>
+ <file category="sourceC" name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c" version="1.0.0" attr="config"/>
+ <!-- SAU configuration -->
+ <file category="header" name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
+ </files>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS GCC">
+ <description>System and Startup for Generic Arm Cortex-M35P device</description>
+ <files>
+ <!-- include folder / device header file -->
+ <file category="include" name="Device/ARM/ARMCM35P/Include/"/>
+ <!-- startup / system file -->
+ <file category="sourceC" name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.c" version="1.0.0" attr="config" condition="GCC"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c" version="1.0.0" attr="config"/>
+ <!-- SAU configuration -->
+ <file category="header" name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
+ </files>
+ </component>
+
<!-- Cortex-SC000 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS">
<description>System and Startup for Generic Arm SC000 device</description>
@@ -2645,6 +2980,10 @@
<file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_NODSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_DSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
+ <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
+ <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
+ <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
+ <file category="library" condition="CM35P_DSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
@@ -2668,6 +3007,10 @@
<file category="library" condition="CM33_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_NODSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_DSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
+ <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
+ <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
+ <file category="library" condition="CM35P_NODSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
+ <file category="library" condition="CM35P_DSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
@@ -2695,18 +3038,20 @@
<file category="library" condition="CM7_SP_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM23_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="CM33_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <!--file category="library" condition="CM33_DSP_DP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
+ <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="CM35P_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="CM35P_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
+ <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
<!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
</files>
@@ -2936,6 +3281,8 @@
<file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
@@ -2950,6 +3297,8 @@
<file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
@@ -3002,6 +3351,8 @@
<file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
@@ -3009,6 +3360,8 @@
<file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
@@ -3071,6 +3424,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s" condition="CM23_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM33_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM33_FP_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM35P_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM35P_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s" condition="ARMv8MBL_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_FP_ARMCC"/>
@@ -3085,6 +3440,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
@@ -3099,6 +3456,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="CM23_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_FP_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="ARMv8MBL_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_FP_IAR"/>
@@ -3214,6 +3573,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s" condition="CM23_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM33_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM33_FP_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM35P_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM35P_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s" condition="ARMv8MBL_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="ARMv8MML_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="ARMv8MML_FP_ARMCC"/>
@@ -3221,6 +3582,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S" condition="CM23_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM33_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM35P_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S" condition="ARMv8MBL_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="ARMv8MML_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
@@ -3228,6 +3591,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s" condition="CM23_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM33_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM33_FP_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM35P_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM35P_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s" condition="ARMv8MBL_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="ARMv8MML_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="ARMv8MML_FP_IAR"/>
@@ -3261,6 +3626,10 @@
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
</board>
<board name="Fixed Virtual Platform" vendor="ARM">