Added logical operators + sorting + spline
- Added NEON bitwise AND, NOT, OR, XOR (q7, q15, q31)
- Added Sorting algorithms f32 (NEON bitonic sort)
- Added cubic spline interpolation function
- Added test patterns for all
diff --git a/CMSIS/DSP/Include/arm_math.h b/CMSIS/DSP/Include/arm_math.h
index 2ac1003..4f3f68f 100644
--- a/CMSIS/DSP/Include/arm_math.h
+++ b/CMSIS/DSP/Include/arm_math.h
@@ -617,7 +617,6 @@
#endif
-
#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
/**
* @brief 32-bit floating-point 128-bit vector type
@@ -2034,6 +2033,278 @@
/**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_BITONIC = 0,
+ /**< Bitonic sort */
+ ARM_SORT_BUBBLE = 1,
+ /**< Bubble sort */
+ ARM_SORT_HEAP = 2,
+ /**< Heap sort */
+ ARM_SORT_INSERTION = 3,
+ /**< Insertion sort */
+ ARM_SORT_MERGE = 4,
+ /**< Merge sort */
+ ARM_SORT_QUICK = 5,
+ /**< Quick sort */
+ ARM_SORT_SELECTION = 6
+ /**< Selection sort */
+ } arm_sort_alg;
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_DESCENDING = 0,
+ /**< Descending order (9 to 0) */
+ ARM_SORT_ASCENDING = 1
+ /**< Ascending order (0 to 9) */
+ } arm_sort_dir;
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_alg alg; /**< Sorting algorithm selected */
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ } arm_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] alg Selected algorithm.
+ * @param[in] dir Sorting order.
+ * @param[in] inPlaceFlag In place flag.
+ */
+ void arm_sort_init_f32(
+ arm_sort_instance_f32 * S,
+ arm_sort_alg alg,
+ arm_sort_dir dir);
+
+ /**
+ * @brief Struct for specifying cubic spline type
+ */
+ typedef enum
+ {
+ ARM_SPLINE_NATURAL = 0, /**< Natural spline */
+ ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
+ } arm_spline_type;
+
+ /**
+ * @brief Instance structure for the floating-point cubic spline interpolation.
+ */
+ typedef struct
+ {
+ uint32_t n_x; /**< Number of known data points */
+ arm_spline_type type; /**< Type (boundary conditions) */
+ } arm_spline_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+ void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * x,
+ const float32_t * y,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] n number of known data points.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ */
+ void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ uint32_t n,
+ arm_spline_type type);
+
+ /**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
@@ -2042,9 +2313,8 @@
uint16_t numCols; /**< number of columns of the matrix. */
float32_t *pData; /**< points to the data of the matrix. */
} arm_matrix_instance_f32;
-
-
- /**
+
+ /**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
@@ -7473,9 +7743,8 @@
q15_t * pDst,
uint32_t blockSize);
- /**
+/**
* @brief Struct for specifying SVM Kernel
- *
*/
typedef enum
{
@@ -7490,7 +7759,6 @@
} arm_ml_kernel_type;
-
/**
* @brief Instance structure for linear SVM prediction function.
*/
diff --git a/CMSIS/DSP/PrivateInclude/arm_sorting.h b/CMSIS/DSP/PrivateInclude/arm_sorting.h
new file mode 100644
index 0000000..4266674
--- /dev/null
+++ b/CMSIS/DSP/PrivateInclude/arm_sorting.h
@@ -0,0 +1,232 @@
+/******************************************************************************
+ * @file arm_sorting.h
+ * @brief Private header file for CMSIS DSP Library
+ * @version V1.7.0
+ * @date 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_SORTING_H_
+#define _ARM_SORTING_H_
+
+#include "arm_math.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_bubble_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_heap_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_insertion_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t* pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_merge_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_quick_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_selection_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_bitonic_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir);
+#if defined(ARM_MATH_NEON)
+ static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir);
+ static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir);
+ static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir);
+ static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir);
+ static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir);
+ static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir);
+ static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir);
+ static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2,
+ float32x4x2_t cd1, float32x4x2_t cd2, uint8_t dir);
+ static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir);
+ static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir);
+ static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir);
+#endif
+ static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir);
+ static void arm_merge_sort_core_f32(float32_t *B, uint32_t iBegin, uint32_t iEnd, float32_t *A, uint8_t dir);
+ static void topDownMerge(float32_t *A, uint32_t iBegin, uint32_t iMiddle, uint32_t iEnd, float32_t *B, uint8_t dir);
+ static void arm_quick_sort_core_f32(float32_t *pSrc, uint32_t first, uint32_t last, uint8_t dir);
+
+#if defined(ARM_MATH_NEON)
+
+#define vtrn256_128q(a, b) \
+do { \
+ float32x4_t vtrn128_temp = a.val[1]; \
+ a.val[1] = b.val[0]; \
+ b.val[0] = vtrn128_temp ; \
+} while (0)
+
+#define vtrn128_64q(a, b) \
+do { \
+ float32x2_t ab, cd, ef, gh; \
+ ab = vget_low_f32(a); \
+ ef = vget_low_f32(b); \
+ cd = vget_high_f32(a); \
+ gh = vget_high_f32(b); \
+ a = vcombine_f32(ab, ef); \
+ b = vcombine_f32(cd, gh); \
+} while (0)
+
+#define vtrn256_64q(a, b) \
+do { \
+ float32x2_t a_0, a_1, a_2, a_3; \
+ float32x2_t b_0, b_1, b_2, b_3; \
+ a_0 = vget_low_f32(a.val[0]); \
+ a_1 = vget_high_f32(a.val[0]); \
+ a_2 = vget_low_f32(a.val[1]); \
+ a_3 = vget_high_f32(a.val[1]); \
+ b_0 = vget_low_f32(b.val[0]); \
+ b_1 = vget_high_f32(b.val[0]); \
+ b_2 = vget_low_f32(b.val[1]); \
+ b_3 = vget_high_f32(b.val[1]); \
+ a.val[0] = vcombine_f32(a_0, b_0); \
+ a.val[1] = vcombine_f32(a_2, b_2); \
+ b.val[0] = vcombine_f32(a_1, b_1); \
+ b.val[1] = vcombine_f32(a_3, b_3); \
+} while (0)
+
+#define vtrn128_32q(a, b) \
+do { \
+ float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \
+ (a) = vtrn32_tmp.val[0]; \
+ (b) = vtrn32_tmp.val[1]; \
+} while (0)
+
+#define vtrn256_32q(a, b) \
+do { \
+ float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \
+ float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \
+ a.val[0] = vtrn32_tmp_1.val[0]; \
+ a.val[1] = vtrn32_tmp_2.val[0]; \
+ b.val[0] = vtrn32_tmp_1.val[1]; \
+ b.val[1] = vtrn32_tmp_2.val[1]; \
+} while (0)
+
+#define vminmaxq(a, b) \
+ do { \
+ float32x4_t minmax_tmp = (a); \
+ (a) = vminq_f32((a), (b)); \
+ (b) = vmaxq_f32(minmax_tmp, (b)); \
+} while (0)
+
+#define vminmax256q(a, b) \
+ do { \
+ float32x4x2_t minmax256_tmp = (a); \
+ a.val[0] = vminq_f32(a.val[0], b.val[0]); \
+ a.val[1] = vminq_f32(a.val[1], b.val[1]); \
+ b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \
+ b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \
+} while (0)
+
+#define vrev128q_f32(a) \
+ vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a)))
+
+#define vrev256q_f32(a) \
+ do { \
+ float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \
+ a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \
+ a.val[1] = rev_tmp; \
+} while (0)
+
+#define vldrev128q_f32(a, p) \
+ do { \
+ a = vld1q_f32(p); \
+ a = vrev128q_f32(a); \
+} while (0)
+
+#endif /* ARM_MATH_NEON */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARM_SORTING_H */
diff --git a/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h b/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h
index 5721cdd..65fc752 100755
--- a/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h
+++ b/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h
@@ -1658,4 +1658,4 @@
#endif
-#endif /* _ARM_VEC_MATH_H */
+#endif /* _ARM_VEC_FILTERING_H_ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q15.c
new file mode 100644
index 0000000..e53706f
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q15.c
@@ -0,0 +1,104 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_and_q15.c
+ * Description: Q15 bitwise AND
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup And Vector bitwise AND
+
+ Compute the logical bitwise AND.
+
+ There are separate functions for Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup And
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise AND of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_and_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int16x8_t vecA, vecB;
+
+ /* Compute 8 outputs at a time */
+ blkCnt = blockSize >> 3U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s16(pSrcA);
+ vecB = vld1q_s16(pSrcB);
+
+ vst1q_s16(pDst, vandq_s16(vecA, vecB) );
+
+ pSrcA += 8;
+ pSrcB += 8;
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 7;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)&(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of And group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q31.c
new file mode 100644
index 0000000..0348a59
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_and_q31.c
+ * Description: Q31 bitwise AND
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup And
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise AND of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_and_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int32x4_t vecA, vecB;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s32(pSrcA);
+ vecB = vld1q_s32(pSrcB);
+
+ vst1q_s32(pDst, vandq_s32(vecA, vecB) );
+
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)&(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of And group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q7.c
new file mode 100644
index 0000000..97734a8
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_and_q7.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_and_q7.c
+ * Description: Q7 bitwise AND
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup And
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise AND of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_and_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int8x16_t vecA, vecB;
+
+ /* Compute 16 outputs at a time */
+ blkCnt = blockSize >> 4U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s8(pSrcA);
+ vecB = vld1q_s8(pSrcB);
+
+ vst1q_s8(pDst, vandq_s8(vecA, vecB) );
+
+ pSrcA += 16;
+ pSrcB += 16;
+ pDst += 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0xF;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)&(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of And group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q15.c
new file mode 100644
index 0000000..7cfe07e
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q15.c
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_not_q15.c
+ * Description: Q15 bitwise NOT
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup Not Vector bitwise NOT
+
+ Compute the logical bitwise NOT.
+
+ There are separate functions for Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Not
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise NOT of a fixed-point vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_not_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int16x8_t inV;
+
+ /* Compute 8 outputs at a time */
+ blkCnt = blockSize >> 3U;
+
+ while (blkCnt > 0U)
+ {
+ inV = vld1q_s16(pSrc);
+
+ vst1q_s16(pDst, vmvnq_s16(inV) );
+
+ pSrc += 8;
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 7;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = ~(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Not group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q31.c
new file mode 100644
index 0000000..c6b08bd
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q31.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_not_q31.c
+ * Description: Q31 bitwise NOT
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Not
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise NOT of a fixed-point vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_not_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int32x4_t inV;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ inV = vld1q_s32(pSrc);
+
+ vst1q_s32(pDst, vmvnq_s32(inV) );
+
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = ~(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Not group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q7.c
new file mode 100644
index 0000000..46baf2c
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_not_q7.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_not_q7.c
+ * Description: Q7 bitwise NOT
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Not
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise NOT of a fixed-point vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_not_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int8x16_t inV;
+
+ /* Compute 16 outputs at a time */
+ blkCnt = blockSize >> 4U;
+
+ while (blkCnt > 0U)
+ {
+ inV = vld1q_s8(pSrc);
+
+ vst1q_s8(pDst, vmvnq_s8(inV) );
+
+ pSrc += 16;
+ pDst += 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0xF;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = ~(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Not group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q15.c
new file mode 100644
index 0000000..d092071
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q15.c
@@ -0,0 +1,104 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_or_q15.c
+ * Description: Q15 bitwise inclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup Or Vector bitwise inclusive OR
+
+ Compute the logical bitwise OR.
+
+ There are separate functions for Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Or
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise OR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_or_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int16x8_t vecA, vecB;
+
+ /* Compute 8 outputs at a time */
+ blkCnt = blockSize >> 3U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s16(pSrcA);
+ vecB = vld1q_s16(pSrcB);
+
+ vst1q_s16(pDst, vorrq_s16(vecA, vecB) );
+
+ pSrcA += 8;
+ pSrcB += 8;
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 7;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)|(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Or group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q31.c
new file mode 100644
index 0000000..749165a
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q31.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_or_q31.c
+ * Description: Q31 bitwise inclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Or
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise OR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_or_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int32x4_t vecA, vecB;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s32(pSrcA);
+ vecB = vld1q_s32(pSrcB);
+
+ vst1q_s32(pDst, vorrq_s32(vecA, vecB) );
+
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)|(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+/**
+ @} end of Or group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q7.c
new file mode 100644
index 0000000..1b563d2
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_or_q7.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_or_q7.c
+ * Description: Q7 bitwise inclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Or
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise OR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_or_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int8x16_t vecA, vecB;
+
+ /* Compute 16 outputs at a time */
+ blkCnt = blockSize >> 4U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s8(pSrcA);
+ vecB = vld1q_s8(pSrcB);
+
+ vst1q_s8(pDst, vorrq_s8(vecA, vecB) );
+
+ pSrcA += 16;
+ pSrcB += 16;
+ pDst += 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0xF;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)|(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+/**
+ @} end of Or group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q15.c
new file mode 100644
index 0000000..d0a6a72
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q15.c
@@ -0,0 +1,104 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_xor_q15.c
+ * Description: Q15 bitwise exclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup Xor Vector bitwise exclusive OR
+
+ Compute the logical bitwise XOR.
+
+ There are separate functions for Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Xor
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+#include "arm_math.h"
+
+void arm_xor_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int16x8_t vecA, vecB;
+
+ /* Compute 8 outputs at a time */
+ blkCnt = blockSize >> 3U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s16(pSrcA);
+ vecB = vld1q_s16(pSrcB);
+
+ vst1q_s16(pDst, veorq_s16(vecA, vecB) );
+
+ pSrcA += 8;
+ pSrcB += 8;
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 7;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)^(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Xor group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q31.c
new file mode 100644
index 0000000..51cba23
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_xor_q31.c
+ * Description: Q31 bitwise exclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Xor
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+#include "arm_math.h"
+
+void arm_xor_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int32x4_t vecA, vecB;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s32(pSrcA);
+ vecB = vld1q_s32(pSrcB);
+
+ vst1q_s32(pDst, veorq_s32(vecA, vecB) );
+
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)^(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Xor group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q7.c
new file mode 100644
index 0000000..4c75e22
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_q7.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_xor_q7.c
+ * Description: Q7 bitwise exclusive OR
+ *
+ * $Date: 14 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Xor
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+#include "arm_math.h"
+
+void arm_xor_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ int8x16_t vecA, vecB;
+
+ /* Compute 16 outputs at a time */
+ blkCnt = blockSize >> 4U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_s8(pSrcA);
+ vecB = vld1q_s8(pSrcB);
+
+ vst1q_s8(pDst, veorq_s8(vecA, vecB) );
+
+ pSrcA += 16;
+ pSrcB += 16;
+ pDst += 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0xF;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)^(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Xor group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c
new file mode 100644
index 0000000..67ecc8f
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c
@@ -0,0 +1,1032 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_bitonic_sort_f32.c
+ * Description: Floating point bitonic sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup Sorting Vector sorting algorithms
+
+ Sort the elements of a vector
+
+ There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+
+static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir)
+{
+ uint32_t step;
+ uint32_t k, j;
+ float32_t *leftPtr, *rightPtr;
+ float32_t temp;
+
+ step = n>>1;
+ leftPtr = pSrc;
+ rightPtr = pSrc+n-1;
+
+ for(k=0; k<step; k++)
+ {
+ if(dir == (*leftPtr > *rightPtr))
+ {
+ // Swap
+ temp=*leftPtr;
+ *leftPtr=*rightPtr;
+ *rightPtr=temp;
+ }
+
+ leftPtr++; // Move right
+ rightPtr--; // Move left
+ }
+
+ // Merge
+ for(step=(n>>2); step>0; step/=2)
+ {
+ for(j=0; j<n; j=j+step*2)
+ {
+ leftPtr = pSrc+j;
+ rightPtr = pSrc+j+step;
+
+ for(k=0; k<step; k++)
+ {
+ if(*leftPtr > *rightPtr)
+ {
+ // Swap
+ temp=*leftPtr;
+ *leftPtr=*rightPtr;
+ *rightPtr=temp;
+ }
+
+ leftPtr++;
+ rightPtr++;
+ }
+ }
+ }
+}
+
+#ifdef ARM_MATH_NEON
+
+static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir)
+{
+ float32x4_t a;
+ float32x4_t b;
+ float32x4_t c;
+ float32x4_t d;
+
+ // Load 16 samples
+ a = vld1q_f32(pSrc);
+ b = vld1q_f32(pSrc+4);
+ c = vld1q_f32(pSrc+8);
+ d = vld1q_f32(pSrc+12);
+
+ // Bitonic sorting network for 4 samples x 4 times
+ if(dir)
+ {
+ vminmaxq(a, b);
+ vminmaxq(c, d);
+
+ vminmaxq(a, d);
+ vminmaxq(b, c);
+
+ vminmaxq(a, b);
+ vminmaxq(c, d);
+ }
+ else
+ {
+ vminmaxq(b, a);
+ vminmaxq(d, c);
+
+ vminmaxq(d, a);
+ vminmaxq(c, b);
+
+ vminmaxq(b, a);
+ vminmaxq(d, c);
+ }
+
+ float32x4x2_t ab = vtrnq_f32 (a, b);
+ float32x4x2_t cd = vtrnq_f32 (c, d);
+
+ // Transpose 4 ordered arrays of 4 samples
+ a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0]));
+ b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1]));
+ c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0]));
+ d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1]));
+
+ // Merge pairs of arrays of 4 samples
+ ab = arm_bitonic_merge_8_f32(a, b, dir);
+ cd = arm_bitonic_merge_8_f32(c, d, dir);
+
+ // Merge arrays of 8 samples
+ arm_bitonic_merge_16_f32(pDst, ab, cd, dir);
+}
+
+static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir)
+{
+ // Merge two preordered float32x4x2_t
+ vrev256q_f32(b);
+
+ if(dir)
+ vminmax256q(a, b);
+ else
+ vminmax256q(b, a);
+
+ arm_bitonic_resort_16_f32(pOut, a, b, dir);
+}
+
+static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir)
+{
+ /* Start with two vectors:
+ * +---+---+---+---+---+---+---+---+
+ * | a | b | c | d | e | f | g | h |
+ * +---+---+---+---+---+---+---+---+
+ * +---+---+---+---+---+---+---+---+
+ * | i | j | k | l | m | n | o | p |
+ * +---+---+---+---+---+---+---+---+
+ * All the elements of the first are guaranteed to be less than or equal to
+ * all of the elements in the second, and both vectors are bitonic.
+ * We need to perform these operations to completely sort both lists:
+ * vminmax([abcd],[efgh]) vminmax([ijkl],[mnop])
+ * vminmax([abef],[cdgh]) vminmax([ijmn],[klop])
+ * vminmax([acef],[bdfh]) vminmax([ikmo],[jlmp])
+ */
+
+ vtrn256_128q(a, b);
+ /* +---+---+---+---+---+---+---+---+
+ * | a | b | c | d | i | j | k | l |
+ * +---+---+---+---+---+---+---+---+
+ * +---+---+---+---+---+---+---+---+
+ * | e | f | g | h | m | n | o | p |
+ * +---+---+---+---+---+---+---+---+
+ */
+ if(dir)
+ vminmax256q(a, b);
+ else
+ vminmax256q(b, a);
+
+ vtrn256_64q(a, b);
+
+ /* +---+---+---+---+---+---+---+---+
+ * | a | b | e | f | i | j | m | n |
+ * +---+---+---+---+---+---+---+---+
+ * +---+---+---+---+---+---+---+---+
+ * | c | d | g | h | k | l | o | p |
+ * +---+---+---+---+---+---+---+---+
+ */
+ if(dir)
+ vminmax256q(a, b);
+ else
+ vminmax256q(b, a);
+
+ vtrn256_32q(a, b);
+ /* We now have:
+ * +---+---+---+---+---+---+---+---+
+ * | a | c | e | g | i | k | m | o |
+ * +---+---+---+---+---+---+---+---+
+ * +---+---+---+---+---+---+---+---+
+ * | b | d | f | h | j | l | n | p |
+ * +---+---+---+---+---+---+---+---+
+ */
+ if(dir)
+ vminmax256q(a, b);
+ else
+ vminmax256q(b, a);
+
+ float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]);
+ float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]);
+
+ vst1q_f32(pOut, out1.val[0]);
+ vst1q_f32(pOut+4, out1.val[1]);
+ vst1q_f32(pOut+8, out2.val[0]);
+ vst1q_f32(pOut+12, out2.val[1]);
+}
+
+static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
+{
+ /* a and b are guaranteed to be bitonic */
+ // Reverse the element of the second vector
+ b = vrev128q_f32(b);
+
+ // Compare the two vectors
+ if(dir)
+ vminmaxq(a, b);
+ else
+ vminmaxq(b, a);
+
+ // Merge the two vectors
+ float32x4x2_t ab = arm_bitonic_resort_8_f32(a, b, dir);
+
+ return ab;
+}
+
+static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
+{
+ /* Start with two vectors:
+ * +---+---+---+---+
+ * | a | b | c | d |
+ * +---+---+---+---+
+ * +---+---+---+---+
+ * | e | f | g | h |
+ * +---+---+---+---+
+ * All the elements of the first are guaranteed to be less than or equal to
+ * all of the elements in the second, and both vectors are bitonic.
+ * We need to perform these operations to completely sort both lists:
+ * vminmax([abcd],[efgh])
+ * vminmax([acbd],[egfh])
+ */
+ vtrn128_64q(a, b);
+ /* +---+---+---+---+
+ * | a | b | e | f |
+ * +---+---+---+---+
+ * +---+---+---+---+
+ * | c | d | g | h |
+ * +---+---+---+---+
+ */
+ if(dir)
+ vminmaxq(a, b);
+ else
+ vminmaxq(b, a);
+
+ vtrn128_32q(a, b);
+ /* +---+---+---+---+
+ * | a | c | e | g |
+ * +---+---+---+---+
+ * +---+---+---+---+
+ * | b | d | f | h |
+ * +---+---+---+---+
+ */
+ if(dir)
+ vminmaxq(a, b);
+ else
+ vminmaxq(b, a);
+
+ return vzipq_f32(a, b);
+}
+
+static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2, float32x4x2_t cd1, float32x4x2_t cd2, uint8_t dir)
+{
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ }
+ //Transpose 256
+ float32x4_t temp;
+
+ temp = ab2.val[0];
+ ab2.val[0] = cd1.val[0];
+ cd1.val[0] = temp;
+ temp = ab2.val[1];
+ ab2.val[1] = cd1.val[1];
+ cd1.val[1] = temp;
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ }
+
+ //Transpose 128
+ arm_bitonic_merge_16_f32(pSrc+0, ab1, cd1, dir);
+ arm_bitonic_merge_16_f32(pSrc+16, ab2, cd2, dir);
+}
+
+static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir)
+{
+ float32x4x2_t ab1, ab2, ab3, ab4;
+ float32x4x2_t cd1, cd2, cd3, cd4;
+
+ //Load and reverse second array
+ ab1.val[0] = vld1q_f32(pSrc+0 );
+ ab1.val[1] = vld1q_f32(pSrc+4 );
+ ab2.val[0] = vld1q_f32(pSrc+8 );
+ ab2.val[1] = vld1q_f32(pSrc+12);
+ ab3.val[0] = vld1q_f32(pSrc+16);
+ ab3.val[1] = vld1q_f32(pSrc+20);
+ ab4.val[0] = vld1q_f32(pSrc+24);
+ ab4.val[1] = vld1q_f32(pSrc+28);
+
+ vldrev128q_f32(cd4.val[1], pSrc+32);
+ vldrev128q_f32(cd4.val[0], pSrc+36);
+ vldrev128q_f32(cd3.val[1], pSrc+40);
+ vldrev128q_f32(cd3.val[0], pSrc+44);
+ vldrev128q_f32(cd2.val[1], pSrc+48);
+ vldrev128q_f32(cd2.val[0], pSrc+52);
+ vldrev128q_f32(cd1.val[1], pSrc+56);
+ vldrev128q_f32(cd1.val[0], pSrc+60);
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ vminmax256q(ab3, cd3);
+ vminmax256q(ab4, cd4);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ vminmax256q(cd3, ab3);
+ vminmax256q(cd4, ab4);
+ }
+
+ //Transpose 512
+ float32x4_t temp;
+
+ temp = ab3.val[0];
+ ab3.val[0] = cd1.val[0];
+ cd1.val[0] = temp;
+ temp = ab3.val[1];
+ ab3.val[1] = cd1.val[1];
+ cd1.val[1] = temp;
+ temp = ab4.val[0];
+ ab4.val[0] = cd2.val[0];
+ cd2.val[0] = temp;
+ temp = ab4.val[1];
+ ab4.val[1] = cd2.val[1];
+ cd2.val[1] = temp;
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ vminmax256q(ab3, cd3);
+ vminmax256q(ab4, cd4);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ vminmax256q(cd3, ab3);
+ vminmax256q(cd4, ab4);
+ }
+
+ //Transpose 256
+ arm_bitonic_merge_32_f32(pSrc+0, ab1, ab2, cd1, cd2, dir);
+ arm_bitonic_merge_32_f32(pSrc+32, ab3, ab4, cd3, cd4, dir);
+}
+
+static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir)
+{
+ float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8;
+ float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8;
+
+ //Load and reverse second array
+ ab1.val[0] = vld1q_f32(pSrc+0 );
+ ab1.val[1] = vld1q_f32(pSrc+4 );
+ ab2.val[0] = vld1q_f32(pSrc+8 );
+ ab2.val[1] = vld1q_f32(pSrc+12);
+ ab3.val[0] = vld1q_f32(pSrc+16);
+ ab3.val[1] = vld1q_f32(pSrc+20);
+ ab4.val[0] = vld1q_f32(pSrc+24);
+ ab4.val[1] = vld1q_f32(pSrc+28);
+ ab5.val[0] = vld1q_f32(pSrc+32);
+ ab5.val[1] = vld1q_f32(pSrc+36);
+ ab6.val[0] = vld1q_f32(pSrc+40);
+ ab6.val[1] = vld1q_f32(pSrc+44);
+ ab7.val[0] = vld1q_f32(pSrc+48);
+ ab7.val[1] = vld1q_f32(pSrc+52);
+ ab8.val[0] = vld1q_f32(pSrc+56);
+ ab8.val[1] = vld1q_f32(pSrc+60);
+
+ vldrev128q_f32(cd8.val[1], pSrc+64);
+ vldrev128q_f32(cd8.val[0], pSrc+68);
+ vldrev128q_f32(cd7.val[1], pSrc+72);
+ vldrev128q_f32(cd7.val[0], pSrc+76);
+ vldrev128q_f32(cd6.val[1], pSrc+80);
+ vldrev128q_f32(cd6.val[0], pSrc+84);
+ vldrev128q_f32(cd5.val[1], pSrc+88);
+ vldrev128q_f32(cd5.val[0], pSrc+92);
+ vldrev128q_f32(cd4.val[1], pSrc+96);
+ vldrev128q_f32(cd4.val[0], pSrc+100);
+ vldrev128q_f32(cd3.val[1], pSrc+104);
+ vldrev128q_f32(cd3.val[0], pSrc+108);
+ vldrev128q_f32(cd2.val[1], pSrc+112);
+ vldrev128q_f32(cd2.val[0], pSrc+116);
+ vldrev128q_f32(cd1.val[1], pSrc+120);
+ vldrev128q_f32(cd1.val[0], pSrc+124);
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ vminmax256q(ab3, cd3);
+ vminmax256q(ab4, cd4);
+ vminmax256q(ab5, cd5);
+ vminmax256q(ab6, cd6);
+ vminmax256q(ab7, cd7);
+ vminmax256q(ab8, cd8);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ vminmax256q(cd3, ab3);
+ vminmax256q(cd4, ab4);
+ vminmax256q(cd5, ab5);
+ vminmax256q(cd6, ab6);
+ vminmax256q(cd7, ab7);
+ vminmax256q(cd8, ab8);
+ }
+
+ //Transpose
+ float32x4_t temp;
+
+ temp = ab5.val[0];
+ ab5.val[0] = cd1.val[0];
+ cd1.val[0] = temp;
+ temp = ab5.val[1];
+ ab5.val[1] = cd1.val[1];
+ cd1.val[1] = temp;
+ temp = ab6.val[0];
+ ab6.val[0] = cd2.val[0];
+ cd2.val[0] = temp;
+ temp = ab6.val[1];
+ ab6.val[1] = cd2.val[1];
+ cd2.val[1] = temp;
+ temp = ab7.val[0];
+ ab7.val[0] = cd3.val[0];
+ cd3.val[0] = temp;
+ temp = ab7.val[1];
+ ab7.val[1] = cd3.val[1];
+ cd3.val[1] = temp;
+ temp = ab8.val[0];
+ ab8.val[0] = cd4.val[0];
+ cd4.val[0] = temp;
+ temp = ab8.val[1];
+ ab8.val[1] = cd4.val[1];
+ cd4.val[1] = temp;
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1, cd1);
+ vminmax256q(ab2, cd2);
+ vminmax256q(ab3, cd3);
+ vminmax256q(ab4, cd4);
+ vminmax256q(ab5, cd5);
+ vminmax256q(ab6, cd6);
+ vminmax256q(ab7, cd7);
+ vminmax256q(ab8, cd8);
+ }
+ else
+ {
+ vminmax256q(cd1, ab1);
+ vminmax256q(cd2, ab2);
+ vminmax256q(cd3, ab3);
+ vminmax256q(cd4, ab4);
+ vminmax256q(cd5, ab5);
+ vminmax256q(cd6, ab6);
+ vminmax256q(cd7, ab7);
+ vminmax256q(cd8, ab8);
+ }
+
+ vst1q_f32(pSrc, ab1.val[0]);
+ vst1q_f32(pSrc+4, ab1.val[1]);
+ vst1q_f32(pSrc+8, ab2.val[0]);
+ vst1q_f32(pSrc+12, ab2.val[1]);
+ vst1q_f32(pSrc+16, ab3.val[0]);
+ vst1q_f32(pSrc+20, ab3.val[1]);
+ vst1q_f32(pSrc+24, ab4.val[0]);
+ vst1q_f32(pSrc+28, ab4.val[1]);
+ vst1q_f32(pSrc+32, cd1.val[0]);
+ vst1q_f32(pSrc+36, cd1.val[1]);
+ vst1q_f32(pSrc+40, cd2.val[0]);
+ vst1q_f32(pSrc+44, cd2.val[1]);
+ vst1q_f32(pSrc+48, cd3.val[0]);
+ vst1q_f32(pSrc+52, cd3.val[1]);
+ vst1q_f32(pSrc+56, cd4.val[0]);
+ vst1q_f32(pSrc+60, cd4.val[1]);
+ vst1q_f32(pSrc+64, ab5.val[0]);
+ vst1q_f32(pSrc+68, ab5.val[1]);
+ vst1q_f32(pSrc+72, ab6.val[0]);
+ vst1q_f32(pSrc+76, ab6.val[1]);
+ vst1q_f32(pSrc+80, ab7.val[0]);
+ vst1q_f32(pSrc+84, ab7.val[1]);
+ vst1q_f32(pSrc+88, ab8.val[0]);
+ vst1q_f32(pSrc+92, ab8.val[1]);
+ vst1q_f32(pSrc+96, cd5.val[0]);
+ vst1q_f32(pSrc+100, cd5.val[1]);
+ vst1q_f32(pSrc+104, cd6.val[0]);
+ vst1q_f32(pSrc+108, cd6.val[1]);
+ vst1q_f32(pSrc+112, cd7.val[0]);
+ vst1q_f32(pSrc+116, cd7.val[1]);
+ vst1q_f32(pSrc+120, cd8.val[0]);
+ vst1q_f32(pSrc+124, cd8.val[1]);
+
+ //Transpose
+ arm_bitonic_merge_64_f32(pSrc+0 , dir);
+ arm_bitonic_merge_64_f32(pSrc+64, dir);
+}
+
+static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir)
+{
+ float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8;
+ float32x4x2_t ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16;
+ float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8;
+ float32x4x2_t cd9, cd10, cd11, cd12, cd13, cd14, cd15, cd16;
+
+ //Load and reverse second array
+ ab1.val[0] = vld1q_f32(pSrc+0 );
+ ab1.val[1] = vld1q_f32(pSrc+4 );
+ ab2.val[0] = vld1q_f32(pSrc+8 );
+ ab2.val[1] = vld1q_f32(pSrc+12 );
+ ab3.val[0] = vld1q_f32(pSrc+16 );
+ ab3.val[1] = vld1q_f32(pSrc+20 );
+ ab4.val[0] = vld1q_f32(pSrc+24 );
+ ab4.val[1] = vld1q_f32(pSrc+28 );
+ ab5.val[0] = vld1q_f32(pSrc+32 );
+ ab5.val[1] = vld1q_f32(pSrc+36 );
+ ab6.val[0] = vld1q_f32(pSrc+40 );
+ ab6.val[1] = vld1q_f32(pSrc+44 );
+ ab7.val[0] = vld1q_f32(pSrc+48 );
+ ab7.val[1] = vld1q_f32(pSrc+52 );
+ ab8.val[0] = vld1q_f32(pSrc+56 );
+ ab8.val[1] = vld1q_f32(pSrc+60 );
+ ab9.val[0] = vld1q_f32(pSrc+64 );
+ ab9.val[1] = vld1q_f32(pSrc+68 );
+ ab10.val[0] = vld1q_f32(pSrc+72 );
+ ab10.val[1] = vld1q_f32(pSrc+76 );
+ ab11.val[0] = vld1q_f32(pSrc+80 );
+ ab11.val[1] = vld1q_f32(pSrc+84 );
+ ab12.val[0] = vld1q_f32(pSrc+88 );
+ ab12.val[1] = vld1q_f32(pSrc+92 );
+ ab13.val[0] = vld1q_f32(pSrc+96 );
+ ab13.val[1] = vld1q_f32(pSrc+100);
+ ab14.val[0] = vld1q_f32(pSrc+104);
+ ab14.val[1] = vld1q_f32(pSrc+108);
+ ab15.val[0] = vld1q_f32(pSrc+112);
+ ab15.val[1] = vld1q_f32(pSrc+116);
+ ab16.val[0] = vld1q_f32(pSrc+120);
+ ab16.val[1] = vld1q_f32(pSrc+124);
+
+ vldrev128q_f32(cd16.val[1], pSrc+128);
+ vldrev128q_f32(cd16.val[0], pSrc+132);
+ vldrev128q_f32(cd15.val[1], pSrc+136);
+ vldrev128q_f32(cd15.val[0], pSrc+140);
+ vldrev128q_f32(cd14.val[1], pSrc+144);
+ vldrev128q_f32(cd14.val[0], pSrc+148);
+ vldrev128q_f32(cd13.val[1], pSrc+152);
+ vldrev128q_f32(cd13.val[0], pSrc+156);
+ vldrev128q_f32(cd12.val[1], pSrc+160);
+ vldrev128q_f32(cd12.val[0], pSrc+164);
+ vldrev128q_f32(cd11.val[1], pSrc+168);
+ vldrev128q_f32(cd11.val[0], pSrc+172);
+ vldrev128q_f32(cd10.val[1], pSrc+176);
+ vldrev128q_f32(cd10.val[0], pSrc+180);
+ vldrev128q_f32(cd9.val[1] , pSrc+184);
+ vldrev128q_f32(cd9.val[0] , pSrc+188);
+ vldrev128q_f32(cd8.val[1] , pSrc+192);
+ vldrev128q_f32(cd8.val[0] , pSrc+196);
+ vldrev128q_f32(cd7.val[1] , pSrc+200);
+ vldrev128q_f32(cd7.val[0] , pSrc+204);
+ vldrev128q_f32(cd6.val[1] , pSrc+208);
+ vldrev128q_f32(cd6.val[0] , pSrc+212);
+ vldrev128q_f32(cd5.val[1] , pSrc+216);
+ vldrev128q_f32(cd5.val[0] , pSrc+220);
+ vldrev128q_f32(cd4.val[1] , pSrc+224);
+ vldrev128q_f32(cd4.val[0] , pSrc+228);
+ vldrev128q_f32(cd3.val[1] , pSrc+232);
+ vldrev128q_f32(cd3.val[0] , pSrc+236);
+ vldrev128q_f32(cd2.val[1] , pSrc+240);
+ vldrev128q_f32(cd2.val[0] , pSrc+244);
+ vldrev128q_f32(cd1.val[1] , pSrc+248);
+ vldrev128q_f32(cd1.val[0] , pSrc+252);
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1 , cd1 );
+ vminmax256q(ab2 , cd2 );
+ vminmax256q(ab3 , cd3 );
+ vminmax256q(ab4 , cd4 );
+ vminmax256q(ab5 , cd5 );
+ vminmax256q(ab6 , cd6 );
+ vminmax256q(ab7 , cd7 );
+ vminmax256q(ab8 , cd8 );
+ vminmax256q(ab9 , cd9 );
+ vminmax256q(ab10, cd10);
+ vminmax256q(ab11, cd11);
+ vminmax256q(ab12, cd12);
+ vminmax256q(ab13, cd13);
+ vminmax256q(ab14, cd14);
+ vminmax256q(ab15, cd15);
+ vminmax256q(ab16, cd16);
+ }
+ else
+ {
+ vminmax256q(cd1 , ab1 );
+ vminmax256q(cd2 , ab2 );
+ vminmax256q(cd3 , ab3 );
+ vminmax256q(cd4 , ab4 );
+ vminmax256q(cd5 , ab5 );
+ vminmax256q(cd6 , ab6 );
+ vminmax256q(cd7 , ab7 );
+ vminmax256q(cd8 , ab8 );
+ vminmax256q(cd9 , ab9 );
+ vminmax256q(cd10, ab10);
+ vminmax256q(cd11, ab11);
+ vminmax256q(cd12, ab12);
+ vminmax256q(cd13, ab13);
+ vminmax256q(cd14, ab14);
+ vminmax256q(cd15, ab15);
+ vminmax256q(cd16, ab16);
+ }
+
+ //Transpose
+ float32x4_t temp;
+
+ temp = ab9.val[0];
+ ab9.val[0] = cd1.val[0];
+ cd1.val[0] = temp;
+ temp = ab9.val[1];
+ ab9.val[1] = cd1.val[1];
+ cd1.val[1] = temp;
+ temp = ab10.val[0];
+ ab10.val[0] = cd2.val[0];
+ cd2.val[0] = temp;
+ temp = ab10.val[1];
+ ab10.val[1] = cd2.val[1];
+ cd2.val[1] = temp;
+ temp = ab11.val[0];
+ ab11.val[0] = cd3.val[0];
+ cd3.val[0] = temp;
+ temp = ab11.val[1];
+ ab11.val[1] = cd3.val[1];
+ cd3.val[1] = temp;
+ temp = ab12.val[0];
+ ab12.val[0] = cd4.val[0];
+ cd4.val[0] = temp;
+ temp = ab12.val[1];
+ ab12.val[1] = cd4.val[1];
+ cd4.val[1] = temp;
+ temp = ab13.val[0];
+ ab13.val[0] = cd5.val[0];
+ cd5.val[0] = temp;
+ temp = ab13.val[1];
+ ab13.val[1] = cd5.val[1];
+ cd5.val[1] = temp;
+ temp = ab14.val[0];
+ ab14.val[0] = cd6.val[0];
+ cd6.val[0] = temp;
+ temp = ab14.val[1];
+ ab14.val[1] = cd6.val[1];
+ cd6.val[1] = temp;
+ temp = ab15.val[0];
+ ab15.val[0] = cd7.val[0];
+ cd7.val[0] = temp;
+ temp = ab15.val[1];
+ ab15.val[1] = cd7.val[1];
+ cd7.val[1] = temp;
+ temp = ab16.val[0];
+ ab16.val[0] = cd8.val[0];
+ cd8.val[0] = temp;
+ temp = ab16.val[1];
+ ab16.val[1] = cd8.val[1];
+ cd8.val[1] = temp;
+
+ //Compare
+ if(dir)
+ {
+ vminmax256q(ab1 , cd1 );
+ vminmax256q(ab2 , cd2 );
+ vminmax256q(ab3 , cd3 );
+ vminmax256q(ab4 , cd4 );
+ vminmax256q(ab5 , cd5 );
+ vminmax256q(ab6 , cd6 );
+ vminmax256q(ab7 , cd7 );
+ vminmax256q(ab8 , cd8 );
+ vminmax256q(ab9 , cd9 );
+ vminmax256q(ab10, cd10);
+ vminmax256q(ab11, cd11);
+ vminmax256q(ab12, cd12);
+ vminmax256q(ab13, cd13);
+ vminmax256q(ab14, cd14);
+ vminmax256q(ab15, cd15);
+ vminmax256q(ab16, cd16);
+ }
+ else
+ {
+ vminmax256q(cd1 , ab1 );
+ vminmax256q(cd2 , ab2 );
+ vminmax256q(cd3 , ab3 );
+ vminmax256q(cd4 , ab4 );
+ vminmax256q(cd5 , ab5 );
+ vminmax256q(cd6 , ab6 );
+ vminmax256q(cd7 , ab7 );
+ vminmax256q(cd8 , ab8 );
+ vminmax256q(cd9 , ab9 );
+ vminmax256q(cd10, ab10);
+ vminmax256q(cd11, ab11);
+ vminmax256q(cd12, ab12);
+ vminmax256q(cd13, ab13);
+ vminmax256q(cd14, ab14);
+ vminmax256q(cd15, ab15);
+ vminmax256q(cd16, ab16);
+ }
+
+ vst1q_f32(pSrc, ab1.val[0] );
+ vst1q_f32(pSrc+4, ab1.val[1] );
+ vst1q_f32(pSrc+8, ab2.val[0] );
+ vst1q_f32(pSrc+12, ab2.val[1] );
+ vst1q_f32(pSrc+16, ab3.val[0] );
+ vst1q_f32(pSrc+20, ab3.val[1] );
+ vst1q_f32(pSrc+24, ab4.val[0] );
+ vst1q_f32(pSrc+28, ab4.val[1] );
+ vst1q_f32(pSrc+32, ab5.val[0] );
+ vst1q_f32(pSrc+36, ab5.val[1] );
+ vst1q_f32(pSrc+40, ab6.val[0] );
+ vst1q_f32(pSrc+44, ab6.val[1] );
+ vst1q_f32(pSrc+48, ab7.val[0] );
+ vst1q_f32(pSrc+52, ab7.val[1] );
+ vst1q_f32(pSrc+56, ab8.val[0] );
+ vst1q_f32(pSrc+60, ab8.val[1] );
+ vst1q_f32(pSrc+64, cd1.val[0] );
+ vst1q_f32(pSrc+68, cd1.val[1] );
+ vst1q_f32(pSrc+72, cd2.val[0] );
+ vst1q_f32(pSrc+76, cd2.val[1] );
+ vst1q_f32(pSrc+80, cd3.val[0] );
+ vst1q_f32(pSrc+84, cd3.val[1] );
+ vst1q_f32(pSrc+88, cd4.val[0] );
+ vst1q_f32(pSrc+92, cd4.val[1] );
+ vst1q_f32(pSrc+96, cd5.val[0] );
+ vst1q_f32(pSrc+100, cd5.val[1] );
+ vst1q_f32(pSrc+104, cd6.val[0] );
+ vst1q_f32(pSrc+108, cd6.val[1] );
+ vst1q_f32(pSrc+112, cd7.val[0] );
+ vst1q_f32(pSrc+116, cd7.val[1] );
+ vst1q_f32(pSrc+120, cd8.val[0] );
+ vst1q_f32(pSrc+124, cd8.val[1] );
+ vst1q_f32(pSrc+128, ab9.val[0] );
+ vst1q_f32(pSrc+132, ab9.val[1] );
+ vst1q_f32(pSrc+136, ab10.val[0]);
+ vst1q_f32(pSrc+140, ab10.val[1]);
+ vst1q_f32(pSrc+144, ab11.val[0]);
+ vst1q_f32(pSrc+148, ab11.val[1]);
+ vst1q_f32(pSrc+152, ab12.val[0]);
+ vst1q_f32(pSrc+156, ab12.val[1]);
+ vst1q_f32(pSrc+160, ab13.val[0]);
+ vst1q_f32(pSrc+164, ab13.val[1]);
+ vst1q_f32(pSrc+168, ab14.val[0]);
+ vst1q_f32(pSrc+172, ab14.val[1]);
+ vst1q_f32(pSrc+176, ab15.val[0]);
+ vst1q_f32(pSrc+180, ab15.val[1]);
+ vst1q_f32(pSrc+184, ab16.val[0]);
+ vst1q_f32(pSrc+188, ab16.val[1]);
+ vst1q_f32(pSrc+192, cd9.val[0] );
+ vst1q_f32(pSrc+196, cd9.val[1] );
+ vst1q_f32(pSrc+200, cd10.val[0]);
+ vst1q_f32(pSrc+204, cd10.val[1]);
+ vst1q_f32(pSrc+208, cd11.val[0]);
+ vst1q_f32(pSrc+212, cd11.val[1]);
+ vst1q_f32(pSrc+216, cd12.val[0]);
+ vst1q_f32(pSrc+220, cd12.val[1]);
+ vst1q_f32(pSrc+224, cd13.val[0]);
+ vst1q_f32(pSrc+228, cd13.val[1]);
+ vst1q_f32(pSrc+232, cd14.val[0]);
+ vst1q_f32(pSrc+236, cd14.val[1]);
+ vst1q_f32(pSrc+240, cd15.val[0]);
+ vst1q_f32(pSrc+244, cd15.val[1]);
+ vst1q_f32(pSrc+248, cd16.val[0]);
+ vst1q_f32(pSrc+252, cd16.val[1]);
+
+ //Transpose
+ arm_bitonic_merge_128_f32(pSrc+0 , dir);
+ arm_bitonic_merge_128_f32(pSrc+128, dir);
+}
+
+static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
+{
+ a = arm_bitonic_sort_4_f32(a, dir);
+ b = arm_bitonic_sort_4_f32(b, dir);
+ return arm_bitonic_merge_8_f32(a, b, dir);
+}
+
+static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir)
+{
+ float32_t temp;
+
+ if( dir==(a[0]>a[1]) )
+ {
+ temp = a[1];
+ a[1] = a[0];
+ a[0] = temp;
+ }
+ if( dir==(a[2]>a[3]) )
+ {
+ temp = a[3];
+ a[3] = a[2];
+ a[2] = temp;
+ }
+
+ if( dir==(a[0]>a[3]) )
+ {
+ temp = a[3];
+ a[3] = a[0];
+ a[0] = temp;
+ }
+ if( dir==(a[1]>a[2]) )
+ {
+ temp = a[2];
+ a[2] = a[1];
+ a[1] = temp;
+ }
+
+ if( dir==(a[0]>a[1]) )
+ {
+ temp = a[1];
+ a[1] = a[0];
+ a[0] = temp;
+ }
+ if( dir==(a[2]>a[3]) )
+ {
+ temp = a[3];
+ a[3] = a[2];
+ a[2] = temp;
+ }
+
+ return a;
+}
+
+#endif
+
+void arm_bitonic_sort_f32(
+const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint16_t s, i;
+ uint8_t dir = S->dir;
+
+#ifdef ARM_MATH_NEON
+
+ float32_t * pOut;
+ uint16_t counter = blockSize>>5;
+
+ if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only
+ {
+ if(pSrc == pDst) // in-place
+ pOut = pSrc;
+ else
+ pOut = pDst;
+
+ float32x4x2_t ab1, ab2;
+ float32x4x2_t cd1, cd2;
+
+ if(blockSize == 1)
+ pOut = pSrc;
+ else if(blockSize == 2)
+ {
+ float32_t temp;
+
+ if( dir==(pSrc[0]>pSrc[1]) )
+ {
+ temp = pSrc[1];
+ pOut[1] = pSrc[0];
+ pOut[0] = temp;
+ }
+ else
+ pOut = pSrc;
+ }
+ else if(blockSize == 4)
+ {
+ float32x4_t a = vld1q_f32(pSrc);
+
+ a = arm_bitonic_sort_4_f32(a, dir);
+
+ vst1q_f32(pOut, a);
+ }
+ else if(blockSize == 8)
+ {
+ float32x4_t a;
+ float32x4_t b;
+ float32x4x2_t ab;
+
+ a = vld1q_f32(pSrc);
+ b = vld1q_f32(pSrc+4);
+
+ ab = arm_bitonic_sort_8_f32(a, b, dir);
+
+ vst1q_f32(pOut, ab.val[0]);
+ vst1q_f32(pOut+4, ab.val[1]);
+ }
+ else if(blockSize >=16)
+ {
+ // Order 16 bits long vectors
+ for(i=0; i<blockSize; i=i+16)
+ arm_bitonic_sort_16_f32(pSrc+i, pOut+i, dir);
+
+ // Merge
+ for(i=0; i<counter; i++)
+ {
+ // Load and reverse second vector
+ ab1.val[0] = vld1q_f32(pOut+32*i+0 );
+ ab1.val[1] = vld1q_f32(pOut+32*i+4 );
+ ab2.val[0] = vld1q_f32(pOut+32*i+8 );
+ ab2.val[1] = vld1q_f32(pOut+32*i+12);
+
+ vldrev128q_f32(cd2.val[1], pOut+32*i+16);
+ vldrev128q_f32(cd2.val[0], pOut+32*i+20);
+ vldrev128q_f32(cd1.val[1], pOut+32*i+24);
+ vldrev128q_f32(cd1.val[0], pOut+32*i+28);
+
+ arm_bitonic_merge_32_f32(pOut+32*i, ab1, ab2, cd1, cd2, dir);
+ }
+
+ counter = counter>>1;
+ for(i=0; i<counter; i++)
+ arm_bitonic_merge_64_f32(pOut+64*i, dir);
+
+ counter = counter>>1;
+ for(i=0; i<counter; i++)
+ arm_bitonic_merge_128_f32(pOut+128*i, dir);
+
+ counter = counter>>1;
+ for(i=0; i<counter; i++)
+ arm_bitonic_merge_256_f32(pOut+256*i, dir);
+
+ // Etc...
+ }
+ }
+
+#else
+
+ float32_t * pA;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+
+ if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only
+ {
+ for(s=2; s<=blockSize; s=s*2)
+ {
+ for(i=0; i<blockSize; i=i+s)
+ arm_bitonic_sort_core_f32(pA+i, s, dir);
+ }
+ }
+#endif
+}
+
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c
new file mode 100644
index 0000000..fcc4ceb
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c
@@ -0,0 +1,103 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_bubble_sort_f32.c
+ * Description: Floating point bubble sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The bubble sort algorithm is a simple comparison algorithm that
+ * reads the elements of a vector from the beginning to the end,
+ * compares the adjacent ones and swaps them if they are in the
+ * wrong order. The procedure is repeated until there is nothing
+ * left to swap. Bubble sort is fast for input vectors that are
+ * nearly sorted.
+ *
+ * @par It's an in-place algorithm. In order to obtain an out-of-place
+ * function, a memcpy of the source vector is performed
+ */
+
+void arm_bubble_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint8_t dir = S->dir;
+ uint32_t i;
+ uint8_t swapped =1;
+ float32_t * pA;
+ float32_t temp;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+ while(swapped==1) // If nothing has been swapped after one loop stop
+ {
+ swapped=0;
+
+ for(i=0; i<blockSize-1; i++)
+ {
+ if(dir==(pA[i]>pA[i+1]))
+ {
+ // Swap
+ temp = pA[i];
+ pA[i] = pA[i+1];
+ pA[i+1] = temp;
+
+ // Update flag
+ swapped = 1;
+ }
+ }
+
+ blockSize--;
+ }
+}
+
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c
new file mode 100644
index 0000000..09ae924
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_heap_sort_f32.c
+ * Description: Floating point heap sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The heap sort algorithm is a comparison algorithm that
+ * divides the input array into a sorted and an unsorted region,
+ * and shrinks the unsorted region by extracting the largest
+ * element and moving it to the sorted region. A heap data
+ * structure is used to find the maximum.
+ *
+ * @par It's an in-place algorithm. In order to obtain an out-of-place
+ * function, a memcpy of the source vector is performed.
+ */
+
+static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir)
+{
+ /* Put all the elements of pSrc in heap order */
+ uint32_t k = i; // Initialize largest/smallest as root
+ uint32_t l = 2*i + 1; // left = 2*i + 1
+ uint32_t r = 2*i + 2; // right = 2*i + 2
+ float32_t temp;
+
+ if (l < n && dir==(pSrc[l] > pSrc[k]) )
+ k = l;
+
+ if (r < n && dir==(pSrc[r] > pSrc[k]) )
+ k = r;
+
+ if (k != i)
+ {
+ temp = pSrc[i];
+ pSrc[i]=pSrc[k];
+ pSrc[k]=temp;
+
+ arm_heapify(pSrc, n, k, dir);
+ }
+}
+
+void arm_heap_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t * pA;
+ int32_t i;
+ float32_t temp;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+ // Build the heap array so that the largest value is the root
+ for (i = blockSize/2 - 1; i >= 0; i--)
+ arm_heapify(pA, blockSize, i, S->dir);
+
+ for (i = blockSize - 1; i >= 0; i--)
+ {
+ // Swap
+ temp = pA[i];
+ pA[i] = pA[0];
+ pA[0] = temp;
+
+ // Restore heap order
+ arm_heapify(pA, i, 0, S->dir);
+ }
+}
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c
new file mode 100644
index 0000000..92394c9
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_insertion_sort_f32.c
+ * Description: Floating point insertion sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The insertion sort is a simple sorting algorithm that
+ * reads all the element of the input array and removes one element
+ * at a time, finds the location it belongs in the final sorted list,
+ * and inserts it there.
+ *
+ * @par It's an in-place algorithm. In order to obtain an out-of-place
+ * function, a memcpy of the source vector is performed.
+ */
+
+void arm_insertion_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t* pDst,
+ uint32_t blockSize)
+{
+ float32_t * pA;
+ uint8_t dir = S->dir;
+ uint32_t i, j;
+ float32_t temp;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+ // Real all the element of the input array
+ for(i=0; i<blockSize; i++)
+ {
+ // Move the i-th element to the right position
+ for (j = i; j>0 && dir==(pA[j]<pA[j-1]); j--)
+ {
+ // Swap
+ temp = pA[j];
+ pA[j] = pA[j-1];
+ pA[j-1] = temp;
+ }
+ }
+}
+
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c
new file mode 100644
index 0000000..60cceca
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c
@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_merge_sort_f32.c
+ * Description: Floating point merge sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The merge sort algorithm is a comparison algorithm that
+ * divide the input array in sublists and merge them to produce
+ * longer sorted sublists until there is only one list remaining.
+ *
+ * @par A work array is always needed, hence pSrc and pDst cannot be
+ * equal and the results will be stored in pDst.
+ */
+
+static void arm_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, uint8_t dir)
+{
+ if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide
+ {
+ int32_t middle = (end + begin) / 2; // Take the middle point
+
+ arm_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part
+ arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
+
+ topDownMerge(pB, begin, middle, end, pA, dir);
+ }
+}
+
+static void topDownMerge(float32_t * pA, uint32_t begin, uint32_t middle, uint32_t end, float32_t * pB, uint8_t dir)
+{
+ /* Left array is pA[begin:middle-1]
+ * Right Array is pA[middle:end-1]
+ * They are merged in pB
+ */
+
+ uint32_t i = begin;
+ uint32_t j = middle;
+ uint32_t k;
+
+ // Read all the elements in the sublist
+ for (k = begin; k < end; k++)
+ {
+ // Merge
+ if (i < middle && (j >= end || dir==(pA[i] <= pA[j])) )
+ {
+ pB[k] = pA[i];
+ i++;
+ }
+ else
+ {
+ pB[k] = pA[j];
+ j++;
+ }
+ }
+}
+
+void arm_merge_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize)
+{
+ // A work array is needed: pDst
+ if(pSrc != pDst) // out-of-place only
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t));
+
+ arm_merge_sort_core_f32(pSrc, 0, blockSize, pDst, S->dir);
+ }
+}
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c
new file mode 100644
index 0000000..ad47310
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_quick_sort_f32.c
+ * Description: Floating point quick sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The quick sort algorithm is a comparison algorithm that
+ * divides the input array into two smaller sub-arrays and
+ * recursively sort them. An element of the array (the pivot)
+ * is chosen, all the elements with values smaller than the
+ * pivot are moved before the pivot, while all elements with
+ * values greater than the pivot are moved after it (partition).
+ *
+ * @par
+ * In this implementation the Hoare partition scheme has been
+ * used and the first element has always been chosen as the pivot.
+ *
+ * @par It's an in-place algorithm. In order to obtain an out-of-place
+ * function, a memcpy of the source vector is performed.
+ */
+
+static void arm_quick_sort_core_f32(float32_t *pSrc, uint32_t first, uint32_t last, uint8_t dir)
+{
+ uint32_t i, j, pivot;
+ float32_t temp;
+
+ if(dir)
+ {
+ if(first<last)
+ {
+ pivot=first; // First element chosen as pivot
+ i=first;
+ j=last;
+
+ // Look for a pair of elements (one greater than the pivot, one
+ // smaller) that are in the wrong order relative to each other.
+ while(i<j)
+ {
+ // Compare left elements with pivot
+ while(pSrc[i]<=pSrc[pivot] && i<last)
+ i++; // Move to the right
+
+ // Compare right elements with pivot
+ while(pSrc[j]>pSrc[pivot])
+ j--; // Move to the left
+
+ if(i<j)
+ {
+ // Swap i <-> j
+ temp=pSrc[i];
+ pSrc[i]=pSrc[j];
+ pSrc[j]=temp;
+ }
+ }
+
+ // Swap pivot <-> j
+ temp=pSrc[pivot];
+ pSrc[pivot]=pSrc[j];
+ pSrc[j]=temp;
+
+ arm_quick_sort_core_f32(pSrc, first, j-1, dir);
+ arm_quick_sort_core_f32(pSrc, j+1, last, dir);
+ }
+ }
+ else
+ {
+ if(first<last)
+ {
+ pivot=first;
+ i=first;
+ j=last;
+
+ while(i<j)
+ {
+ while(pSrc[i]>=pSrc[pivot] && i<last)
+ i++;
+
+ while(pSrc[j]<pSrc[pivot])
+ j--;
+
+ if(i<j)
+ {
+ temp=pSrc[i];
+ pSrc[i]=pSrc[j];
+ pSrc[j]=temp;
+ }
+ }
+
+ temp=pSrc[pivot];
+ pSrc[pivot]=pSrc[j];
+ pSrc[j]=temp;
+
+ arm_quick_sort_core_f32(pSrc, first, j-1, dir);
+ arm_quick_sort_core_f32(pSrc, j+1, last, dir);
+ }
+ }
+
+}
+
+void arm_quick_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t * pA;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+ arm_quick_sort_core_f32(pA, 0, blockSize-1, S->dir);
+}
+
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c
new file mode 100644
index 0000000..4821696
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_selection_sort_f32.c
+ * Description: Floating point selection sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Sorting
+ @{
+ */
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ *
+ * @par Algorithm
+ * The Selection sort algorithm is a comparison algorithm that
+ * divides the input array into a sorted and an unsorted sublist
+ * (initially the sorted sublist is empty and the unsorted sublist
+ * is the input array), looks for the smallest (or biggest)
+ * element in the unsorted sublist, swapping it with the leftmost
+ * one, and moving the sublists boundary one element to the right.
+ *
+ * @par It's an in-place algorithm. In order to obtain an out-of-place
+ * function, a memcpy of the source vector is performed.
+ */
+
+void arm_selection_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t i, j, k;
+ uint8_t dir = S->dir;
+ float32_t temp;
+
+ float32_t * pA;
+
+ if(pSrc != pDst) // out-of-place
+ {
+ memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
+ pA = pDst;
+ }
+ else
+ pA = pSrc;
+
+ /* Move the boundary one element to the right */
+ for (i=0; i<blockSize-1; i++)
+ {
+ /* Initialize the minimum/maximum as the first element */
+ k = i;
+
+ /* Look in the unsorted list to find the minimum/maximum value */
+ for (j=i+1; j<blockSize; j++)
+ {
+ if (dir==(pA[j] < pA[k]) )
+ {
+ /* Update value */
+ k = j;
+ }
+ }
+
+ if (k != i)
+ {
+ /* Swap the minimum/maximum with the leftmost element */
+ temp=pA[i];
+ pA[i]=pA[k];
+ pA[k]=temp;
+ }
+ }
+}
+
+/**
+ @} end of Sorting group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c
new file mode 100644
index 0000000..5824b2d
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sort_f32.c
+ * Description: Floating point sort
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+/**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+
+void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ switch(S->alg)
+ {
+ case ARM_SORT_BITONIC:
+ arm_bitonic_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_BUBBLE:
+ arm_bubble_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_HEAP:
+ arm_heap_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_INSERTION:
+ arm_insertion_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_MERGE:
+ arm_merge_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_QUICK:
+ arm_quick_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+
+ case ARM_SORT_SELECTION:
+ arm_selection_sort_f32(S, pSrc, pDst, blockSize);
+ break;
+ }
+}
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c
new file mode 100644
index 0000000..80f10a5
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c
@@ -0,0 +1,36 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sort_init_f32.c
+ * Description: Floating point sort initialization function
+ *
+ * $Date: 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_sorting.h"
+
+void arm_sort_init_f32(arm_sort_instance_f32 * S, arm_sort_alg alg, arm_sort_dir dir)
+{
+ S->alg = alg;
+ S->dir = dir;
+}
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c
new file mode 100644
index 0000000..d70f2f0
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c
@@ -0,0 +1,330 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_spline_interp_f32.c
+ * Description: Floating-point cubic spline interpolation
+ *
+ * $Date: 13 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup SplineInterpolate Cubic Spline Interpolation
+ *
+ * Spline interpolation is a method of interpolation where the interpolant
+ * is a piecewise-defined polynomial called "spline".
+ *
+ * \par Introduction
+ * Given a function f defined on the interval [a,b], a set of n nodes x(i)
+ * where a=x(1)<x(2)<...<x(n)=b and a set of n values y(i) = f(x(i)),
+ * a cubic spline interpolant S(x) is defined as: <br>
+ * <pre>
+ * S1(x) x(1) < x < x(2)
+ * S(x) = ...
+ * Sn-1(x) x(n-1) < x < x(n)
+ * <\pre><br>
+ * where<br>
+ * <pre>
+ * Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3 i=1, ..., n-1
+ * <\pre>
+ *
+ * \par Algorithm
+ * Having defined h(i) = x(i+1) - x(i)<br>
+ * <pre>
+ * h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)] i=2, ..., n-1
+ * <\pre><br>
+ * It is possible to write the previous conditions in matrix form (Ax=B).<br>
+ * In order to solve the system two boundary conidtions are needed.<br>
+ * - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0<br>
+ * In matrix form:<br>
+ * <pre>
+ * | 1 0 0 ... 0 0 0 || c(1) | | 0 |
+ * | h(0) 2[h(0)+h(1)] h(1) ... 0 0 0 || c(2) | | 3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)] |
+ * | ... ... ... ... ... ... ... || ... |=| ... |
+ * | 0 0 0 ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+ * | 0 0 0 ... 0 0 1 || c(n) | | 0 |
+ * </pre><br>
+ * - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n)<br>
+ * In matrix form:<br>
+ * <pre>
+ * | 1 -1 0 ... 0 0 0 || c(1) | | 0 |
+ * | h(0) 2[h(0)+h(1)] h(1) ... 0 0 0 || c(2) | | 3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)] |
+ * | ... ... ... ... ... ... ... || ... |=| ... |
+ * | 0 0 0 ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+ * | 0 0 0 ... 0 -1 1 || c(n) | | 0 |
+ * </pre><br>
+ * A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization
+ * algorithms (A=LU) can be simplified considerably because a large number of zeros appear
+ * in regular patterns. The Crout method has been used:<br>
+ * 1) Solve LZ=B<br>
+ * <pre>
+ * u(1,2) = A(1,2)/A(1,1)
+ * z(1) = B(1)/l(11)
+ *
+ * FOR i=2, ..., N-1
+ * l(i,i) = A(i,i)-A(i,i-1)u(i-1,i)
+ * u(i,i+1) = a(i,i+1)/l(i,i)
+ * z(i) = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
+ *
+ * l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
+ * z(N) = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
+ * </pre><br>
+ * 2) Solve UX=Z<br>
+ * <pre>
+ * c(N)=z(N)
+ *
+ * FOR i=N-1, ..., 1
+ * c(i)=z(i)-u(i,i+1)c(i+1)
+ * </pre><br>
+ * c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials. <br>
+ * b(i) and d(i) are computed as:<br>
+ * - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 <br>
+ * - d(i) = [c(i+1)-c(i)]/[3*h(i)] <br>
+ * Moreover, a(i)=y(i).
+ *
+ * \par Usage
+ * The x input array must be strictly sorted in ascending order and it must
+ * not contain twice the same value (x(i)<x(i+1)).
+ *
+ * \par
+ * It is possible to compute the interpolated vector for x values outside the
+ * input range (xq<x(1); xq>x(n)). The coefficients used to compute the y values for
+ * xq<x(1) are going to be the ones used for the first interval, while for xq>x(n) the
+ * coefficients used for the last interval.
+ *
+ */
+/**
+ @addtogroup SplineInterpolate
+ @{
+ */
+/**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+
+void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * x,
+ const float32_t * y,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t n = S->n_x;
+ arm_spline_type type = S->type;
+
+ float32_t hi, hm1;
+
+ /* Temporary variables for system AX=B */
+ float32_t u[n-1], z[n], c[n];
+ float32_t Bi, li;
+
+ float32_t bi, di;
+ float32_t x_sc;
+
+ const float32_t * pXq = xq;
+
+ int32_t blkCnt = (int32_t)blockSize;
+ int32_t blkCnt2;
+ int32_t i, j;
+
+#ifdef ARM_MATH_NEON
+ float32x4_t xiv;
+ float32x4_t aiv;
+ float32x4_t biv;
+ float32x4_t civ;
+ float32x4_t div;
+
+ float32x4_t xqv;
+
+ float32x4_t temp;
+ float32x4_t diff;
+ float32x4_t yv;
+#endif
+
+ /* === Solve LZ=B to obtain z(i) and u(i) === */
+ /* --- Row 1 --- */
+ /* B(0) = 0, not computed */
+ /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */
+ if(type == ARM_SPLINE_NATURAL)
+ u[0] = 0; // a(1,2) = 0
+ else if(type == ARM_SPLINE_PARABOLIC_RUNOUT)
+ u[0] = -1; // a(1,2) = -1
+
+ z[0] = 0; // z(1) = B(1)/a(1,1) = 0
+
+ /* --- Rows 2 to N-1 (N=n+1) --- */
+ hm1 = x[1] - x[0]; // x(2)-x(1)
+
+ for (i=1; i<n-1; i++)
+ {
+ /* Compute B(i) */
+ hi = x[i+1]-x[i];
+ Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1;
+ /* l(i) = a(ii)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */
+ li = 2*(hi+hm1) - hm1*u[i-1];
+ /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */
+ u[i] = hi/li;
+ /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */
+ z[i] = (Bi-hm1*z[i-1])/li;
+ /* Update h(i-1) */
+ hm1 = hi;
+ }
+
+ /* --- Row N --- */
+ /* l(N) = a(N,N)-a(N,N-1)u(N-1) */
+ /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */
+ if(type == ARM_SPLINE_NATURAL)
+ {
+ //li = 1; // a(N,N)=1; a(N,N-1)=0
+ z[n-1] = 0; // a(N,N-1)=0
+ }
+ else if(type == ARM_SPLINE_PARABOLIC_RUNOUT)
+ {
+ li = 1+u[n-2]; // a(N,N)=1; a(N,N-1)=-1
+ z[n-1] = z[n-2]/li; // a(N,N-1)=-1
+ }
+
+ /* === Solve UX = Z to obtain c(i) === */
+ /* c(N) = z(N) */
+ c[n-1] = z[n-1];
+ /* c(i) = z(i)-u(i+1)c(i+1) */
+ for (j = n-1-1; j >= 0; --j)
+ c[j] = z[j] - u[j] * c[j + 1];
+
+ /* === Compute b(i) and d(i) from c(i) and create output for x(i)<x<x(i+1) === */
+ for (i=0; i<n-1; i++)
+ {
+ hi = x[i+1]-x[i];
+ bi = (y[i+1]-y[i])/hi-hi*(c[i+1]+2*c[i])/3;
+ di = (c[i+1]-c[i])/(3*hi);
+
+#ifdef ARM_MATH_NEON
+ xiv = vdupq_n_f32(x[i]);
+
+ aiv = vdupq_n_f32(y[i]);
+ biv = vdupq_n_f32(bi);
+ civ = vdupq_n_f32(c[i]);
+ div = vdupq_n_f32(di);
+
+ while( *(pXq+4) <= x[i+1] && blkCnt > 4U )
+ {
+ /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */
+ xqv = vld1q_f32(pXq);
+ pXq+=4;
+
+ /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */
+ diff = vsubq_f32(xqv, xiv);
+ temp = diff;
+
+ /* y(i) = a(i) + ... */
+ yv = aiv;
+ /* ... + b(i)*(x-x(i)) + ... */
+ yv = vmlaq_f32(yv, biv, temp);
+ /* ... + c(i)*(x-x(i))^2 + ... */
+ temp = vmulq_f32(temp, diff);
+ yv = vmlaq_f32(yv, civ, temp);
+ /* ... + d(i)*(x-x(i))^3 */
+ temp = vmulq_f32(temp, diff);
+ yv = vmlaq_f32(yv, div, temp);
+
+ /* Store [y(k) y(k+1) y(k+2) y(k+3)] */
+ vst1q_f32(pDst, yv);
+ pDst+=4;
+
+ blkCnt-=4;
+ }
+#endif
+ while( *pXq <= x[i+1] && blkCnt > 0U )
+ {
+ x_sc = *pXq++;
+
+ *pDst = y[i]+bi*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+di*(x_sc-x[i])*(x_sc-x[i])*(x_sc-x[i]);
+
+ pDst++;
+ blkCnt--;
+ }
+ }
+
+ /* == Create output for remaining samples (x>=x(n)) == */
+#ifdef ARM_MATH_NEON
+ /* Compute 4 outputs at a time */
+ blkCnt2 = blkCnt >> 2;
+
+ while(blkCnt2 > 0U)
+ {
+ /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */
+ xqv = vld1q_f32(pXq);
+ pXq+=4;
+
+ /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */
+ diff = vsubq_f32(xqv, xiv);
+ temp = diff;
+
+ /* y(i) = a(i) + ... */
+ yv = aiv;
+ /* ... + b(i)*(x-x(i)) + ... */
+ yv = vmlaq_f32(yv, biv, temp);
+ /* ... + c(i)*(x-x(i))^2 + ... */
+ temp = vmulq_f32(temp, diff);
+ yv = vmlaq_f32(yv, civ, temp);
+ /* ... + d(i)*(x-x(i))^3 */
+ temp = vmulq_f32(temp, diff);
+ yv = vmlaq_f32(yv, div, temp);
+
+ /* Store [y(k) y(k+1) y(k+2) y(k+3)] */
+ vst1q_f32(pDst, yv);
+ pDst+=4;
+
+ blkCnt2--;
+ }
+
+ /* Tail */
+ blkCnt2 = blkCnt & 3;
+#else
+ blkCnt2 = blkCnt;
+#endif
+
+ while(blkCnt2 > 0U)
+ {
+ x_sc = *pXq++;
+
+ *pDst = y[i-1]+bi*(x_sc-x[i-1])+c[i]*(x_sc-x[i-1])*(x_sc-x[i-1])+di*(x_sc-x[i-1])*(x_sc-x[i-1])*(x_sc-x[i-1]);
+
+ pDst++;
+ blkCnt2--;
+ }
+}
+
+/**
+ * @} end of SplineInterpolate group
+ * */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c
new file mode 100644
index 0000000..f9b5ee9
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_spline_interp_init_f32.c
+ * Description: Floating-point cubic spline initialization function
+ *
+ * $Date: 13 November 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ @addtogroup SplineInterpolate
+ @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] n number of known data points.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ */
+
+void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ uint32_t n,
+ arm_spline_type type)
+{
+ S->n_x = n;
+ S->type = type;
+
+ /* Type (boundary conditions):
+ * 0: Natural spline ( S1''(x1)=0 ; Sn''(xn)=0 )
+ * 1: Parabolic runout spline ( S1''(x1)=S2''(x2) ; Sn-1''(xn-1)=Sn''(xn) )
+ */
+}
+
+/**
+ * @} end of SplineInterpolate group
+ */
diff --git a/CMSIS/DSP/Source/configDsp.cmake b/CMSIS/DSP/Source/configDsp.cmake
index 08a4d70..32c11a0 100644
--- a/CMSIS/DSP/Source/configDsp.cmake
+++ b/CMSIS/DSP/Source/configDsp.cmake
@@ -30,8 +30,8 @@
target_compile_definitions(${project} PRIVATE ARM_MATH_FLOAT16)
endif()
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF OR SUPPORT)
target_include_directories(${project} PRIVATE "${root}/CMSIS/DSP/PrivateInclude")
endif()
-endfunction()
\ No newline at end of file
+endfunction()
diff --git a/CMSIS/DSP/Testing/Include/Tests/SupportTestsF32.h b/CMSIS/DSP/Testing/Include/Tests/SupportTestsF32.h
index b54b3f8..2830f02 100755
--- a/CMSIS/DSP/Testing/Include/Tests/SupportTestsF32.h
+++ b/CMSIS/DSP/Testing/Include/Tests/SupportTestsF32.h
@@ -12,6 +12,10 @@
Client::Pattern<float32_t> input;
Client::Pattern<float32_t> coefs;
+ Client::Pattern<float32_t> inputX;
+ Client::Pattern<float32_t> inputY;
+ Client::Pattern<float32_t> outputX;
+
Client::LocalPattern<float32_t> output;
Client::LocalPattern<q15_t> outputQ15;
Client::LocalPattern<q31_t> outputQ31;
diff --git a/CMSIS/DSP/Testing/PatternGeneration/BasicMaths.py b/CMSIS/DSP/Testing/PatternGeneration/BasicMaths.py
index 24c2959..07daae1 100644
--- a/CMSIS/DSP/Testing/PatternGeneration/BasicMaths.py
+++ b/CMSIS/DSP/Testing/PatternGeneration/BasicMaths.py
@@ -106,7 +106,7 @@
NBSAMPLES=33
nb = writeTests(config,format)
-
+
data1 = np.full(NBSAMPLES, 2**format - 1)
data1[1::2] = 2
data2 = np.full(NBSAMPLES, -2**format)
@@ -173,6 +173,83 @@
ref = d2 * 2.0
config.writeReference(nb+12, ref,"Shift")
+ return(nb+13)
+
+
+def writeTests2(config,format):
+
+ NBSAMPLES = Tools.loopnb(format,Tools.BODYANDTAIL)
+
+ nb = writeTestsWithSat(config,format)
+
+ if format == 31:
+ maxVal = 0x7fffffff
+ if format == 15:
+ maxVal = 0x7fff
+ if format == 7:
+ maxVal = 0x7f
+
+ minVal = -maxVal-1
+
+ data1 = np.random.randint(minVal, maxVal, size=NBSAMPLES)
+ data2 = np.random.randint(minVal, maxVal, size=NBSAMPLES)
+
+ if format == 31:
+ config.writeInputS32(nb,data1,"BitwiseInput")
+ config.writeInputS32(nb+1,data2,"BitwiseInput")
+
+ if format == 15:
+ config.writeInputS16(nb,data1,"BitwiseInput")
+ config.writeInputS16(nb+1,data2,"BitwiseInput")
+
+ if format == 7:
+ config.writeInputS8(nb,data1,"BitwiseInput")
+ config.writeInputS8(nb+1,data2,"BitwiseInput")
+
+ ref = np.bitwise_and(data1, data2)
+
+ if format == 31:
+ config.writeReferenceS32(nb, ref, "And")
+
+ if format == 15:
+ config.writeReferenceS16(nb, ref, "And")
+
+ if format == 7:
+ config.writeReferenceS8(nb, ref, "And")
+
+ ref = np.bitwise_or(data1, data2)
+
+ if format == 31:
+ config.writeReferenceS32(nb+1, ref, "Or")
+
+ if format == 15:
+ config.writeReferenceS16(nb+1, ref, "Or")
+
+ if format == 7:
+ config.writeReferenceS8(nb+1, ref, "Or")
+
+ ref = np.invert(data1)
+
+ if format == 31:
+ config.writeReferenceS32(nb+2, ref, "Not")
+
+ if format == 15:
+ config.writeReferenceS16(nb+2, ref, "Not")
+
+ if format == 7:
+ config.writeReferenceS8(nb+2, ref, "Not")
+
+ ref = np.bitwise_xor(data1, data2)
+
+ if format == 31:
+ config.writeReferenceS32(nb+3, ref, "Xor")
+
+ if format == 15:
+ config.writeReferenceS16(nb+3, ref, "Xor")
+
+ if format == 7:
+ config.writeReferenceS8(nb+3, ref, "Xor")
+
def generatePatterns():
PATTERNDIR = os.path.join("Patterns","DSP","BasicMaths","BasicMaths")
@@ -183,13 +260,12 @@
configq15=Tools.Config(PATTERNDIR,PARAMDIR,"q15")
configq7=Tools.Config(PATTERNDIR,PARAMDIR,"q7")
-
-
writeTests(configf32,0)
- writeTestsWithSat(configq31,31)
- writeTestsWithSat(configq15,15)
- writeTestsWithSat(configq7,7)
-
+
+ writeTests2(configq31,31)
+ writeTests2(configq15,15)
+ writeTests2(configq7,7)
+
# Params just as example
someLists=[[1,3,5],[1,3,5],[1,3,5]]
@@ -197,4 +273,4 @@
configf32.writeParam(1, r.reshape(81))
if __name__ == '__main__':
- generatePatterns()
\ No newline at end of file
+ generatePatterns()
diff --git a/CMSIS/DSP/Testing/PatternGeneration/Support.py b/CMSIS/DSP/Testing/PatternGeneration/Support.py
index 755d0c8..404a3ce 100755
--- a/CMSIS/DSP/Testing/PatternGeneration/Support.py
+++ b/CMSIS/DSP/Testing/PatternGeneration/Support.py
@@ -3,6 +3,7 @@
import Tools
import random
import numpy as np
+from scipy import interpolate
NBTESTSAMPLES = 10
@@ -139,6 +140,59 @@
config.writeInput(1,va,"Samples")
config.writeInput(1,vb,"Coefs")
+def writeTests2(config, format):
+
+ data = np.random.randn(11)
+ data = Tools.normalize(data)
+ config.writeInput(7, data)
+ ref = np.sort(data)
+ config.writeReference(7, ref)
+
+ data = np.random.randn(16)
+ data = Tools.normalize(data)
+ config.writeInput(8, data)
+ ref = np.sort(data)
+ config.writeReference(8, ref)
+
+ data = np.random.randn(32)
+ data = Tools.normalize(data)
+ config.writeInput(9, data)
+ ref = np.sort(data)
+ config.writeReference(9, ref)
+
+ data = np.full((16), np.random.randn(1))
+ data = Tools.normalize(data)
+ config.writeInput(10, data)
+ ref = np.sort(data)
+ config.writeReference(10, ref)
+
+ x = [0,3,10,20]
+ config.writeInput(11,x,"InputX")
+ y = [0,9,100,400]
+ config.writeInput(11,y,"InputY")
+ xnew = np.arange(0,20,1)
+ config.writeInput(11,xnew,"OutputX")
+ ynew = interpolate.CubicSpline(x,y)
+ config.writeReference(11, ynew(xnew))
+
+ x = np.arange(0, 2*np.pi+np.pi/4, np.pi/4)
+ config.writeInput(12,x,"InputX")
+ y = np.sin(x)
+ config.writeInput(12,y,"InputY")
+ xnew = np.arange(0, 2*np.pi+np.pi/16, np.pi/16)
+ config.writeInput(12,xnew,"OutputX")
+ ynew = interpolate.CubicSpline(x,y,bc_type="natural")
+ config.writeReference(12, ynew(xnew))
+
+ x = [0,3,10]
+ config.writeInput(13,x,"InputX")
+ y = x
+ config.writeInput(13,y,"InputY")
+ xnew = np.arange(-10,20,1)
+ config.writeInput(13,xnew,"OutputX")
+ ynew = interpolate.CubicSpline(x,y)
+ config.writeReference(13, ynew(xnew))
+
def generatePatterns():
PATTERNDIR = os.path.join("Patterns","DSP","Support","Support")
PARAMDIR = os.path.join("Parameters","DSP","Support","Support")
@@ -152,7 +206,9 @@
writeTestsQ31(configq31)
writeTestsQ15(configq15)
writeTestsQ7(configq7)
-
+
+ writeTests2(configf32,0)
+
# For benchmarking we need to vary number of vectors and vector dimension separately
PATTERNBARDIR = os.path.join("Patterns","DSP","SupportBar")
@@ -163,4 +219,4 @@
writeBarTests(configBarf32)
if __name__ == '__main__':
- generatePatterns()
\ No newline at end of file
+ generatePatterns()
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/And24_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/And24_s16.txt
new file mode 100755
index 0000000..342b295
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/And24_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// 130
+0x0082
+// -19436
+0xB414
+// -8552
+0xDE98
+// 4126
+0x101E
+// 224
+0x00E0
+// 8352
+0x20A0
+// 440
+0x01B8
+// 74
+0x004A
+// -16062
+0xC142
+// 6480
+0x1950
+// -30656
+0x8840
+// 58
+0x003A
+// 8196
+0x2004
+// 4879
+0x130F
+// 2068
+0x0814
+// -22472
+0xA838
+// 16980
+0x4254
+// 2864
+0x0B30
+// 1440
+0x05A0
+// 912
+0x0390
+// 17944
+0x4618
+// -32184
+0x8248
+// 25088
+0x6200
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput24_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput24_s16.txt
new file mode 100755
index 0000000..8ce86d8
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput24_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// 20930
+0x51C2
+// -3020
+0xF434
+// -8519
+0xDEB9
+// 4447
+0x115F
+// 1274
+0x04FA
+// 27875
+0x6CE3
+// 13756
+0x35BC
+// 734
+0x02DE
+// -14869
+0xC5EB
+// 7032
+0x1B78
+// -4874
+0xECF6
+// 2683
+0x0A7B
+// 14814
+0x39DE
+// 7951
+0x1F0F
+// -21419
+0xAC55
+// -22408
+0xA878
+// -8618
+0xDE56
+// -13454
+0xCB72
+// 28594
+0x6FB2
+// 7124
+0x1BD4
+// 22361
+0x5759
+// -27908
+0x92FC
+// 27188
+0x6A34
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput25_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput25_s16.txt
new file mode 100755
index 0000000..520e7bb
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/BitwiseInput25_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// -29038
+0x8E92
+// -18602
+0xB756
+// -294
+0xFEDA
+// 22686
+0x589E
+// 30944
+0x78E0
+// -19532
+0xB3B4
+// -15365
+0xC3FB
+// -13973
+0xC96B
+// -13486
+0xCB52
+// -558
+0xFDD2
+// -30391
+0x8949
+// -11846
+0xD1BA
+// 8708
+0x2204
+// -19697
+0xB30F
+// 19124
+0x4AB4
+// -709
+0xFD3B
+// 25181
+0x625D
+// 7984
+0x1F30
+// -27227
+0x95A5
+// 945
+0x03B1
+// 18078
+0x469E
+// -12472
+0xCF48
+// 25280
+0x62C0
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Not26_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Not26_s16.txt
new file mode 100755
index 0000000..0bda6f0
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Not26_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// -20931
+0xAE3D
+// 3019
+0x0BCB
+// 8518
+0x2146
+// -4448
+0xEEA0
+// -1275
+0xFB05
+// -27876
+0x931C
+// -13757
+0xCA43
+// -735
+0xFD21
+// 14868
+0x3A14
+// -7033
+0xE487
+// 4873
+0x1309
+// -2684
+0xF584
+// -14815
+0xC621
+// -7952
+0xE0F0
+// 21418
+0x53AA
+// 22407
+0x5787
+// 8617
+0x21A9
+// 13453
+0x348D
+// -28595
+0x904D
+// -7125
+0xE42B
+// -22362
+0xA8A6
+// 27907
+0x6D03
+// -27189
+0x95CB
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Or25_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Or25_s16.txt
new file mode 100755
index 0000000..2adca13
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Or25_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// -8238
+0xDFD2
+// -2186
+0xF776
+// -261
+0xFEFB
+// 23007
+0x59DF
+// 31994
+0x7CFA
+// -9
+0xFFF7
+// -2049
+0xF7FF
+// -13313
+0xCBFF
+// -12293
+0xCFFB
+// -6
+0xFFFA
+// -4609
+0xEDFF
+// -9221
+0xDBFB
+// 15326
+0x3BDE
+// -16625
+0xBF0F
+// -4363
+0xEEF5
+// -645
+0xFD7B
+// -417
+0xFE5F
+// -8334
+0xDF72
+// -73
+0xFFB7
+// 7157
+0x1BF5
+// 22495
+0x57DF
+// -8196
+0xDFFC
+// 27380
+0x6AF4
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Xor27_s16.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Xor27_s16.txt
new file mode 100755
index 0000000..40acfb3
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ15/Xor27_s16.txt
@@ -0,0 +1,48 @@
+H
+23
+// -8368
+0xDF50
+// 17250
+0x4362
+// 8291
+0x2063
+// 18881
+0x49C1
+// 31770
+0x7C1A
+// -8361
+0xDF57
+// -2489
+0xF647
+// -13387
+0xCBB5
+// 3769
+0x0EB9
+// -6486
+0xE6AA
+// 26047
+0x65BF
+// -9279
+0xDBC1
+// 7130
+0x1BDA
+// -21504
+0xAC00
+// -6431
+0xE6E1
+// 21827
+0x5543
+// -17397
+0xBC0B
+// -11198
+0xD442
+// -1513
+0xFA17
+// 6245
+0x1865
+// 4551
+0x11C7
+// 23988
+0x5DB4
+// 2292
+0x08F4
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/And24_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/And24_s32.txt
new file mode 100755
index 0000000..12e7c2d
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/And24_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// 131336302
+0x07D4086E
+// 573792
+0x0008C160
+// -1593474808
+0xA1058108
+// -1069218047
+0xC0450701
+// 1117782104
+0x42A00058
+// -2147106816
+0x8005C000
+// 17565825
+0x010C0881
+// 254135317
+0x0F25CC15
+// 138819520
+0x084637C0
+// 553664528
+0x21004010
+// 1208095012
+0x48021124
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput24_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput24_s32.txt
new file mode 100755
index 0000000..01ad779
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput24_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// 265759230
+0x0FD729FE
+// -536290964
+0xE008D96C
+// -239617255
+0xF1B7BB19
+// -497596487
+0xE25747B9
+// -492107394
+0xE2AB097E
+// -1854549686
+0x9175D14A
+// -1253111631
+0xB54F08B1
+// 1601694807
+0x5F77EC57
+// 1288091588
+0x4CC6B7C4
+// -1319059376
+0xB160C050
+// 1281785204
+0x4C667D74
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput25_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput25_s32.txt
new file mode 100755
index 0000000..9031ffb
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/BitwiseInput25_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -940303249
+0xC7F41C6F
+// 416867312
+0x18D8E3F0
+// -1455046258
+0xA945C18E
+// -974311615
+0xC5ED2F41
+// 1139078873
+0x43E4F6D9
+// -997202764
+0xC48FE4B4
+// 61664903
+0x03ACEE87
+// -1348083939
+0xAFA5DF1D
+// 142571506
+0x087F77F2
+// 797733180
+0x2F8C713C
+// -914156762
+0xC9831326
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Not26_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Not26_s32.txt
new file mode 100755
index 0000000..7d3b2da
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Not26_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -265759231
+0xF028D601
+// 536290963
+0x1FF72693
+// 239617254
+0x0E4844E6
+// 497596486
+0x1DA8B846
+// 492107393
+0x1D54F681
+// 1854549685
+0x6E8A2EB5
+// 1253111630
+0x4AB0F74E
+// -1601694808
+0xA08813A8
+// -1288091589
+0xB339483B
+// 1319059375
+0x4E9F3FAF
+// -1281785205
+0xB399828B
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Or25_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Or25_s32.txt
new file mode 100755
index 0000000..bab5588
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Or25_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -805880321
+0xCFF73DFF
+// -119997444
+0xF8D8FBFC
+// -101188705
+0xF9F7FB9F
+// -402690055
+0xE7FF6FF9
+// -470810625
+0xE3EFFFFF
+// -704645634
+0xD5FFF5FE
+// -1209012553
+0xB7EFEEB7
+// -524449
+0xFFF7FF5F
+// 1291843574
+0x4CFFF7F6
+// -1074990724
+0xBFECF17C
+// -840466570
+0xCDE77F76
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Xor27_s32.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Xor27_s32.txt
new file mode 100755
index 0000000..4119607
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ31/Xor27_s32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -937216623
+0xC8233591
+// -120571236
+0xF8D03A9C
+// 1492286103
+0x58F27A97
+// 666527992
+0x27BA68F8
+// -1588592729
+0xA14FFFA7
+// 1442461182
+0x55FA35FE
+// -1226578378
+0xB6E3E636
+// -254659766
+0xF0D2334A
+// 1153024054
+0x44B9C036
+// -1628655252
+0x9EECB16C
+// -2048561582
+0x85E56E52
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/And24_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/And24_s8.txt
new file mode 100755
index 0000000..58bc9ce
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/And24_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// 0
+0x00
+// 4
+0x04
+// -87
+0xA9
+// 52
+0x34
+// 10
+0x0A
+// 68
+0x44
+// 0
+0x00
+// 101
+0x65
+// 67
+0x43
+// -29
+0xE3
+// 13
+0x0D
+// 8
+0x08
+// 104
+0x68
+// -122
+0x86
+// 69
+0x45
+// -126
+0x82
+// 56
+0x38
+// 34
+0x22
+// 72
+0x48
+// 32
+0x20
+// 17
+0x11
+// 4
+0x04
+// 4
+0x04
+// -26
+0xE6
+// -96
+0xA0
+// -111
+0x91
+// 113
+0x71
+// 17
+0x11
+// 26
+0x1A
+// -88
+0xA8
+// 16
+0x10
+// 1
+0x01
+// 1
+0x01
+// -127
+0x81
+// 1
+0x01
+// 36
+0x24
+// 4
+0x04
+// 65
+0x41
+// 34
+0x22
+// 0
+0x00
+// 12
+0x0C
+// 36
+0x24
+// 99
+0x63
+// -124
+0x84
+// 48
+0x30
+// 73
+0x49
+// 96
+0x60
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput24_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput24_s8.txt
new file mode 100755
index 0000000..6f49da8
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput24_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// 120
+0x78
+// -10
+0xF6
+// -1
+0xFF
+// -74
+0xB6
+// 94
+0x5E
+// -36
+0xDC
+// 14
+0x0E
+// 103
+0x67
+// -17
+0xEF
+// -13
+0xF3
+// 45
+0x2D
+// 40
+0x28
+// -7
+0xF9
+// -82
+0xAE
+// -43
+0xD5
+// -14
+0xF2
+// 56
+0x38
+// -90
+0xA6
+// 88
+0x58
+// -94
+0xA2
+// 49
+0x31
+// 12
+0x0C
+// 53
+0x35
+// -25
+0xE7
+// -95
+0xA1
+// -107
+0x95
+// 121
+0x79
+// 29
+0x1D
+// -98
+0x9E
+// -66
+0xBE
+// -39
+0xD9
+// 111
+0x6F
+// 23
+0x17
+// -23
+0xE9
+// 17
+0x11
+// 102
+0x66
+// 5
+0x05
+// 77
+0x4D
+// -86
+0xAA
+// 65
+0x41
+// -2
+0xFE
+// 38
+0x26
+// 115
+0x73
+// -81
+0xAF
+// -75
+0xB5
+// 111
+0x6F
+// 107
+0x6B
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput25_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput25_s8.txt
new file mode 100755
index 0000000..f5f83da
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/BitwiseInput25_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// 3
+0x03
+// 5
+0x05
+// -87
+0xA9
+// 52
+0x34
+// 10
+0x0A
+// 100
+0x64
+// 113
+0x71
+// 117
+0x75
+// 67
+0x43
+// -17
+0xEF
+// 79
+0x4F
+// 13
+0x0D
+// 106
+0x6A
+// -105
+0x97
+// 101
+0x65
+// -117
+0x8B
+// 122
+0x7A
+// 114
+0x72
+// 74
+0x4A
+// 53
+0x35
+// 29
+0x1D
+// 6
+0x06
+// -122
+0x86
+// -18
+0xEE
+// -76
+0xB4
+// -37
+0xDB
+// 115
+0x73
+// 83
+0x53
+// 122
+0x7A
+// -88
+0xA8
+// 48
+0x30
+// -111
+0x91
+// -87
+0xA9
+// -125
+0x83
+// 15
+0x0F
+// -67
+0xBD
+// 22
+0x16
+// 115
+0x73
+// 115
+0x73
+// 20
+0x14
+// 13
+0x0D
+// -19
+0xED
+// -21
+0xEB
+// -60
+0xC4
+// 112
+0x70
+// -39
+0xD9
+// 100
+0x64
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Not26_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Not26_s8.txt
new file mode 100755
index 0000000..a890d52
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Not26_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// -121
+0x87
+// 9
+0x09
+// 0
+0x00
+// 73
+0x49
+// -95
+0xA1
+// 35
+0x23
+// -15
+0xF1
+// -104
+0x98
+// 16
+0x10
+// 12
+0x0C
+// -46
+0xD2
+// -41
+0xD7
+// 6
+0x06
+// 81
+0x51
+// 42
+0x2A
+// 13
+0x0D
+// -57
+0xC7
+// 89
+0x59
+// -89
+0xA7
+// 93
+0x5D
+// -50
+0xCE
+// -13
+0xF3
+// -54
+0xCA
+// 24
+0x18
+// 94
+0x5E
+// 106
+0x6A
+// -122
+0x86
+// -30
+0xE2
+// 97
+0x61
+// 65
+0x41
+// 38
+0x26
+// -112
+0x90
+// -24
+0xE8
+// 22
+0x16
+// -18
+0xEE
+// -103
+0x99
+// -6
+0xFA
+// -78
+0xB2
+// 85
+0x55
+// -66
+0xBE
+// 1
+0x01
+// -39
+0xD9
+// -116
+0x8C
+// 80
+0x50
+// 74
+0x4A
+// -112
+0x90
+// -108
+0x94
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Or25_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Or25_s8.txt
new file mode 100755
index 0000000..00a74c2
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Or25_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// 123
+0x7B
+// -9
+0xF7
+// -1
+0xFF
+// -74
+0xB6
+// 94
+0x5E
+// -4
+0xFC
+// 127
+0x7F
+// 119
+0x77
+// -17
+0xEF
+// -1
+0xFF
+// 111
+0x6F
+// 45
+0x2D
+// -5
+0xFB
+// -65
+0xBF
+// -11
+0xF5
+// -5
+0xFB
+// 122
+0x7A
+// -10
+0xF6
+// 90
+0x5A
+// -73
+0xB7
+// 61
+0x3D
+// 14
+0x0E
+// -73
+0xB7
+// -17
+0xEF
+// -75
+0xB5
+// -33
+0xDF
+// 123
+0x7B
+// 95
+0x5F
+// -2
+0xFE
+// -66
+0xBE
+// -7
+0xF9
+// -1
+0xFF
+// -65
+0xBF
+// -21
+0xEB
+// 31
+0x1F
+// -1
+0xFF
+// 23
+0x17
+// 127
+0x7F
+// -5
+0xFB
+// 85
+0x55
+// -1
+0xFF
+// -17
+0xEF
+// -5
+0xFB
+// -17
+0xEF
+// -11
+0xF5
+// -1
+0xFF
+// 111
+0x6F
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Xor27_s8.txt b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Xor27_s8.txt
new file mode 100755
index 0000000..905b376
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/BasicMaths/BasicMathsQ7/Xor27_s8.txt
@@ -0,0 +1,96 @@
+B
+47
+// 123
+0x7B
+// -13
+0xF3
+// 86
+0x56
+// -126
+0x82
+// 84
+0x54
+// -72
+0xB8
+// 127
+0x7F
+// 18
+0x12
+// -84
+0xAC
+// 28
+0x1C
+// 98
+0x62
+// 37
+0x25
+// -109
+0x93
+// 57
+0x39
+// -80
+0xB0
+// 121
+0x79
+// 66
+0x42
+// -44
+0xD4
+// 18
+0x12
+// -105
+0x97
+// 44
+0x2C
+// 10
+0x0A
+// -77
+0xB3
+// 9
+0x09
+// 21
+0x15
+// 78
+0x4E
+// 10
+0x0A
+// 78
+0x4E
+// -28
+0xE4
+// 22
+0x16
+// -23
+0xE9
+// -2
+0xFE
+// -66
+0xBE
+// 106
+0x6A
+// 30
+0x1E
+// -37
+0xDB
+// 19
+0x13
+// 62
+0x3E
+// -39
+0xD9
+// 85
+0x55
+// -13
+0xF3
+// -53
+0xCB
+// -104
+0x98
+// 107
+0x6B
+// -59
+0xC5
+// -74
+0xB6
+// 15
+0x0F
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input10_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input10_f32.txt
new file mode 100755
index 0000000..acc5e3b
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input10_f32.txt
@@ -0,0 +1,34 @@
+W
+16
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input7_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input7_f32.txt
new file mode 100755
index 0000000..75f8383
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input7_f32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -0.284240
+0xbe9187ea
+// -0.110841
+0xbde300aa
+// 0.871462
+0x3f5f1821
+// 0.062906
+0x3d80d49e
+// -0.256175
+0xbe83296e
+// -0.609709
+0xbf1c15e7
+// 0.459676
+0x3eeb5ab0
+// 0.625655
+0x3f202af3
+// -0.136353
+0xbe0ba00e
+// -0.693686
+0xbf31956f
+// -1.000000
+0xbf800000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input8_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input8_f32.txt
new file mode 100755
index 0000000..03904f0
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input8_f32.txt
@@ -0,0 +1,34 @@
+W
+16
+// 0.143440
+0x3e12e1e8
+// -0.433392
+0xbedde596
+// 0.174183
+0x3e325d02
+// 0.249633
+0x3e7f9fcd
+// 0.270761
+0x3e8aa13f
+// -0.032531
+0xbd053f5e
+// -0.039249
+0xbd20c3b1
+// -0.493843
+0xbefcd8ee
+// 0.608310
+0x3f1bba36
+// 0.103193
+0x3dd356cb
+// 0.912365
+0x3f6990be
+// 0.442634
+0x3ee2a0fb
+// -0.743851
+0xbf3e6d02
+// -0.361292
+0xbeb8fb41
+// 0.557505
+0x3f0eb8a9
+// -1.000000
+0xbf800000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input9_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input9_f32.txt
new file mode 100755
index 0000000..c5f378d
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Input9_f32.txt
@@ -0,0 +1,66 @@
+W
+32
+// -0.334382
+0xbeab3419
+// 0.755803
+0x3f417c55
+// 0.283553
+0x3e912de0
+// 0.064048
+0x3d832b8c
+// 0.164799
+0x3e28c0f6
+// -0.266484
+0xbe88708f
+// -0.391877
+0xbec8a40c
+// -0.155958
+0xbe1fb37a
+// -0.758920
+0xbf424893
+// 0.017386
+0x3c8e6dc7
+// -0.245446
+0xbe7b563e
+// -0.485731
+0xbef8b1bb
+// -0.169911
+0xbe2dfd3c
+// 0.232379
+0x3e6df4aa
+// -0.777798
+0xbf471dca
+// 0.019173
+0x3c9d0fb4
+// 0.085283
+0x3daea8ee
+// -1.000000
+0xbf800000
+// -0.198733
+0xbe4b80bd
+// -0.148676
+0xbe183e9a
+// -0.249440
+0xbe7f6d34
+// -0.317374
+0xbea27ee3
+// -0.635982
+0xbf22cfb4
+// 0.253418
+0x3e81bff3
+// -0.079539
+0xbda2e56c
+// -0.042185
+0xbd2cc9bb
+// -0.166690
+0xbe2ab0d0
+// -0.306983
+0xbe9d2cde
+// -0.263410
+0xbe86dd9f
+// -0.322421
+0xbea51462
+// -0.683139
+0xbf2ee22f
+// 0.111310
+0x3de3f65d
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX11_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX11_f32.txt
new file mode 100755
index 0000000..4f51280
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX11_f32.txt
@@ -0,0 +1,10 @@
+W
+4
+// 0.000000
+0x0
+// 3.000000
+0x40400000
+// 10.000000
+0x41200000
+// 20.000000
+0x41a00000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX12_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX12_f32.txt
new file mode 100755
index 0000000..8949fc5
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX12_f32.txt
@@ -0,0 +1,20 @@
+W
+9
+// 0.000000
+0x0
+// 0.785398
+0x3f490fdb
+// 1.570796
+0x3fc90fdb
+// 2.356194
+0x4016cbe4
+// 3.141593
+0x40490fdb
+// 3.926991
+0x407b53d1
+// 4.712389
+0x4096cbe4
+// 5.497787
+0x40afeddf
+// 6.283185
+0x40c90fdb
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX13_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX13_f32.txt
new file mode 100755
index 0000000..854af24
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX13_f32.txt
@@ -0,0 +1,8 @@
+W
+3
+// 0.000000
+0x0
+// 3.000000
+0x40400000
+// 10.000000
+0x41200000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX14_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX14_f32.txt
new file mode 100755
index 0000000..f34dc4b
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputX14_f32.txt
@@ -0,0 +1,14 @@
+W
+6
+// 0.000000
+0x0
+// 1.000000
+0x3f800000
+// 2.000000
+0x40000000
+// 3.000000
+0x40400000
+// 4.000000
+0x40800000
+// 5.000000
+0x40a00000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY11_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY11_f32.txt
new file mode 100755
index 0000000..281affb
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY11_f32.txt
@@ -0,0 +1,10 @@
+W
+4
+// 0.000000
+0x0
+// 9.000000
+0x41100000
+// 100.000000
+0x42c80000
+// 400.000000
+0x43c80000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY12_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY12_f32.txt
new file mode 100755
index 0000000..228b213
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY12_f32.txt
@@ -0,0 +1,20 @@
+W
+9
+// 0.000000
+0x0
+// 0.707107
+0x3f3504f3
+// 1.000000
+0x3f800000
+// 0.707107
+0x3f3504f3
+// 0.000000
+0x250d3132
+// -0.707107
+0xbf3504f3
+// -1.000000
+0xbf800000
+// -0.707107
+0xbf3504f3
+// -0.000000
+0xa58d3132
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY13_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY13_f32.txt
new file mode 100755
index 0000000..854af24
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY13_f32.txt
@@ -0,0 +1,8 @@
+W
+3
+// 0.000000
+0x0
+// 3.000000
+0x40400000
+// 10.000000
+0x41200000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY14_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY14_f32.txt
new file mode 100755
index 0000000..d5942ee
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/InputY14_f32.txt
@@ -0,0 +1,14 @@
+W
+6
+// 0.000000
+0x0
+// 0.841471
+0x3f576aa4
+// 0.909297
+0x3f68c7b7
+// 0.141120
+0x3e1081c3
+// -0.756802
+0xbf41bdcf
+// -0.958924
+0xbf757c10
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX11_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX11_f32.txt
new file mode 100755
index 0000000..63c1c92
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX11_f32.txt
@@ -0,0 +1,42 @@
+W
+20
+// 0.000000
+0x0
+// 1.000000
+0x3f800000
+// 2.000000
+0x40000000
+// 3.000000
+0x40400000
+// 4.000000
+0x40800000
+// 5.000000
+0x40a00000
+// 6.000000
+0x40c00000
+// 7.000000
+0x40e00000
+// 8.000000
+0x41000000
+// 9.000000
+0x41100000
+// 10.000000
+0x41200000
+// 11.000000
+0x41300000
+// 12.000000
+0x41400000
+// 13.000000
+0x41500000
+// 14.000000
+0x41600000
+// 15.000000
+0x41700000
+// 16.000000
+0x41800000
+// 17.000000
+0x41880000
+// 18.000000
+0x41900000
+// 19.000000
+0x41980000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX12_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX12_f32.txt
new file mode 100755
index 0000000..03a2a24
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX12_f32.txt
@@ -0,0 +1,68 @@
+W
+33
+// 0.000000
+0x0
+// 0.196350
+0x3e490fdb
+// 0.392699
+0x3ec90fdb
+// 0.589049
+0x3f16cbe4
+// 0.785398
+0x3f490fdb
+// 0.981748
+0x3f7b53d1
+// 1.178097
+0x3f96cbe4
+// 1.374447
+0x3fafeddf
+// 1.570796
+0x3fc90fdb
+// 1.767146
+0x3fe231d6
+// 1.963495
+0x3ffb53d1
+// 2.159845
+0x400a3ae6
+// 2.356194
+0x4016cbe4
+// 2.552544
+0x40235ce2
+// 2.748894
+0x402feddf
+// 2.945243
+0x403c7edd
+// 3.141593
+0x40490fdb
+// 3.337942
+0x4055a0d8
+// 3.534292
+0x406231d6
+// 3.730641
+0x406ec2d4
+// 3.926991
+0x407b53d1
+// 4.123340
+0x4083f267
+// 4.319690
+0x408a3ae6
+// 4.516039
+0x40908365
+// 4.712389
+0x4096cbe4
+// 4.908739
+0x409d1463
+// 5.105088
+0x40a35ce2
+// 5.301438
+0x40a9a560
+// 5.497787
+0x40afeddf
+// 5.694137
+0x40b6365e
+// 5.890486
+0x40bc7edd
+// 6.086836
+0x40c2c75c
+// 6.283185
+0x40c90fdb
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX13_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX13_f32.txt
new file mode 100755
index 0000000..13caa02
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/OutputX13_f32.txt
@@ -0,0 +1,62 @@
+W
+30
+// -10.000000
+0xc1200000
+// -9.000000
+0xc1100000
+// -8.000000
+0xc1000000
+// -7.000000
+0xc0e00000
+// -6.000000
+0xc0c00000
+// -5.000000
+0xc0a00000
+// -4.000000
+0xc0800000
+// -3.000000
+0xc0400000
+// -2.000000
+0xc0000000
+// -1.000000
+0xbf800000
+// 0.000000
+0x0
+// 1.000000
+0x3f800000
+// 2.000000
+0x40000000
+// 3.000000
+0x40400000
+// 4.000000
+0x40800000
+// 5.000000
+0x40a00000
+// 6.000000
+0x40c00000
+// 7.000000
+0x40e00000
+// 8.000000
+0x41000000
+// 9.000000
+0x41100000
+// 10.000000
+0x41200000
+// 11.000000
+0x41300000
+// 12.000000
+0x41400000
+// 13.000000
+0x41500000
+// 14.000000
+0x41600000
+// 15.000000
+0x41700000
+// 16.000000
+0x41800000
+// 17.000000
+0x41880000
+// 18.000000
+0x41900000
+// 19.000000
+0x41980000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference10_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference10_f32.txt
new file mode 100755
index 0000000..acc5e3b
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference10_f32.txt
@@ -0,0 +1,34 @@
+W
+16
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
+// -0.896846
+0xbf6597b1
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference11_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference11_f32.txt
new file mode 100755
index 0000000..78e4974
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference11_f32.txt
@@ -0,0 +1,42 @@
+W
+20
+// 0.000000
+0x0
+// 1.000000
+0x3f800000
+// 4.000000
+0x40800000
+// 9.000000
+0x41100000
+// 16.000000
+0x41800000
+// 25.000000
+0x41c80000
+// 36.000000
+0x42100000
+// 49.000000
+0x42440000
+// 64.000000
+0x42800000
+// 81.000000
+0x42a20000
+// 100.000000
+0x42c80000
+// 121.000000
+0x42f20000
+// 144.000000
+0x43100000
+// 169.000000
+0x43290000
+// 196.000000
+0x43440000
+// 225.000000
+0x43610000
+// 256.000000
+0x43800000
+// 289.000000
+0x43908000
+// 324.000000
+0x43a20000
+// 361.000000
+0x43b48000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference12_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference12_f32.txt
new file mode 100755
index 0000000..5fbe3fd
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference12_f32.txt
@@ -0,0 +1,68 @@
+W
+33
+// 0.000000
+0x0
+// 0.194708
+0x3e476168
+// 0.382243
+0x3ec3b551
+// 0.555433
+0x3f0e30df
+// 0.707107
+0x3f3504f3
+// 0.830791
+0x3f54aebc
+// 0.922816
+0x3f6c3da3
+// 0.980209
+0x3f7aeef6
+// 1.000000
+0x3f800000
+// 0.980209
+0x3f7aeef6
+// 0.922816
+0x3f6c3da3
+// 0.830791
+0x3f54aebc
+// 0.707107
+0x3f3504f3
+// 0.555433
+0x3f0e30df
+// 0.382243
+0x3ec3b551
+// 0.194708
+0x3e476168
+// 0.000000
+0x250d3132
+// -0.194708
+0xbe476168
+// -0.382243
+0xbec3b551
+// -0.555433
+0xbf0e30df
+// -0.707107
+0xbf3504f3
+// -0.830791
+0xbf54aebc
+// -0.922816
+0xbf6c3da3
+// -0.980209
+0xbf7aeef6
+// -1.000000
+0xbf800000
+// -0.980209
+0xbf7aeef6
+// -0.922816
+0xbf6c3da3
+// -0.830791
+0xbf54aebc
+// -0.707107
+0xbf3504f3
+// -0.555433
+0xbf0e30df
+// -0.382243
+0xbec3b551
+// -0.194708
+0xbe476168
+// -0.000000
+0xa5a00000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference13_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference13_f32.txt
new file mode 100755
index 0000000..13caa02
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference13_f32.txt
@@ -0,0 +1,62 @@
+W
+30
+// -10.000000
+0xc1200000
+// -9.000000
+0xc1100000
+// -8.000000
+0xc1000000
+// -7.000000
+0xc0e00000
+// -6.000000
+0xc0c00000
+// -5.000000
+0xc0a00000
+// -4.000000
+0xc0800000
+// -3.000000
+0xc0400000
+// -2.000000
+0xc0000000
+// -1.000000
+0xbf800000
+// 0.000000
+0x0
+// 1.000000
+0x3f800000
+// 2.000000
+0x40000000
+// 3.000000
+0x40400000
+// 4.000000
+0x40800000
+// 5.000000
+0x40a00000
+// 6.000000
+0x40c00000
+// 7.000000
+0x40e00000
+// 8.000000
+0x41000000
+// 9.000000
+0x41100000
+// 10.000000
+0x41200000
+// 11.000000
+0x41300000
+// 12.000000
+0x41400000
+// 13.000000
+0x41500000
+// 14.000000
+0x41600000
+// 15.000000
+0x41700000
+// 16.000000
+0x41800000
+// 17.000000
+0x41880000
+// 18.000000
+0x41900000
+// 19.000000
+0x41980000
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference7_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference7_f32.txt
new file mode 100755
index 0000000..a1122ae
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference7_f32.txt
@@ -0,0 +1,24 @@
+W
+11
+// -1.000000
+0xbf800000
+// -0.693686
+0xbf31956f
+// -0.609709
+0xbf1c15e7
+// -0.284240
+0xbe9187ea
+// -0.256175
+0xbe83296e
+// -0.136353
+0xbe0ba00e
+// -0.110841
+0xbde300aa
+// 0.062906
+0x3d80d49e
+// 0.459676
+0x3eeb5ab0
+// 0.625655
+0x3f202af3
+// 0.871462
+0x3f5f1821
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference8_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference8_f32.txt
new file mode 100755
index 0000000..3d21aa5
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference8_f32.txt
@@ -0,0 +1,34 @@
+W
+16
+// -1.000000
+0xbf800000
+// -0.743851
+0xbf3e6d02
+// -0.493843
+0xbefcd8ee
+// -0.433392
+0xbedde596
+// -0.361292
+0xbeb8fb41
+// -0.039249
+0xbd20c3b1
+// -0.032531
+0xbd053f5e
+// 0.103193
+0x3dd356cb
+// 0.143440
+0x3e12e1e8
+// 0.174183
+0x3e325d02
+// 0.249633
+0x3e7f9fcd
+// 0.270761
+0x3e8aa13f
+// 0.442634
+0x3ee2a0fb
+// 0.557505
+0x3f0eb8a9
+// 0.608310
+0x3f1bba36
+// 0.912365
+0x3f6990be
diff --git a/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference9_f32.txt b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference9_f32.txt
new file mode 100755
index 0000000..1e3dd54
--- /dev/null
+++ b/CMSIS/DSP/Testing/Patterns/DSP/Support/SupportF32/Reference9_f32.txt
@@ -0,0 +1,66 @@
+W
+32
+// -1.000000
+0xbf800000
+// -0.777798
+0xbf471dca
+// -0.758920
+0xbf424893
+// -0.683139
+0xbf2ee22f
+// -0.635982
+0xbf22cfb4
+// -0.485731
+0xbef8b1bb
+// -0.391877
+0xbec8a40c
+// -0.334382
+0xbeab3419
+// -0.322421
+0xbea51462
+// -0.317374
+0xbea27ee3
+// -0.306983
+0xbe9d2cde
+// -0.266484
+0xbe88708f
+// -0.263410
+0xbe86dd9f
+// -0.249440
+0xbe7f6d34
+// -0.245446
+0xbe7b563e
+// -0.198733
+0xbe4b80bd
+// -0.169911
+0xbe2dfd3c
+// -0.166690
+0xbe2ab0d0
+// -0.155958
+0xbe1fb37a
+// -0.148676
+0xbe183e9a
+// -0.079539
+0xbda2e56c
+// -0.042185
+0xbd2cc9bb
+// 0.017386
+0x3c8e6dc7
+// 0.019173
+0x3c9d0fb4
+// 0.064048
+0x3d832b8c
+// 0.085283
+0x3daea8ee
+// 0.111310
+0x3de3f65d
+// 0.164799
+0x3e28c0f6
+// 0.232379
+0x3e6df4aa
+// 0.253418
+0x3e81bff3
+// 0.283553
+0x3e912de0
+// 0.755803
+0x3f417c55
diff --git a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ15.cpp b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ15.cpp
index e16a132..df24ed7 100755
--- a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ15.cpp
+++ b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ15.cpp
@@ -165,6 +165,54 @@
}
+ void BasicTestsQ15::test_and_q15()
+ {
+ GET_Q15_PTR();
+
+ arm_and_q15(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ15::test_or_q15()
+ {
+ GET_Q15_PTR();
+
+ arm_or_q15(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ15::test_not_q15()
+ {
+ GET_Q15_PTR();
+
+ arm_not_q15(inp1,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ15::test_xor_q15()
+ {
+ GET_Q15_PTR();
+
+ arm_xor_q15(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
void BasicTestsQ15::setUp(Testing::testID_t id,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr)
{
@@ -428,6 +476,99 @@
input1.reload(BasicTestsQ15::MAXNEG_Q15_ID,mgr);
break;
+ case BasicTestsQ15::TEST_AND_Q15_37:
+ nb = 7;
+ ref.reload(BasicTestsQ15::REF_AND_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_AND_Q15_38:
+ nb = 16;
+ ref.reload(BasicTestsQ15::REF_AND_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+ case BasicTestsQ15::TEST_AND_Q15_39:
+ nb = 23;
+ ref.reload(BasicTestsQ15::REF_AND_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_OR_Q15_40:
+ nb = 7;
+ ref.reload(BasicTestsQ15::REF_OR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_OR_Q15_41:
+ nb = 16;
+ ref.reload(BasicTestsQ15::REF_OR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+ case BasicTestsQ15::TEST_OR_Q15_42:
+ nb = 23;
+ ref.reload(BasicTestsQ15::REF_OR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_NOT_Q15_43:
+ nb = 7;
+ ref.reload(BasicTestsQ15::REF_NOT_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_NOT_Q15_44:
+ nb = 16;
+ ref.reload(BasicTestsQ15::REF_NOT_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+ case BasicTestsQ15::TEST_NOT_Q15_45:
+ nb = 23;
+ ref.reload(BasicTestsQ15::REF_NOT_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_XOR_Q15_46:
+ nb = 7;
+ ref.reload(BasicTestsQ15::REF_XOR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ15::TEST_XOR_Q15_47:
+ nb = 16;
+ ref.reload(BasicTestsQ15::REF_XOR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+ case BasicTestsQ15::TEST_XOR_Q15_48:
+ nb = 23;
+ ref.reload(BasicTestsQ15::REF_XOR_Q15_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ15::OUT_SAMPLES_Q15_ID,mgr);
+ input1.reload(BasicTestsQ15::INPUT1_BITWISE_Q15_ID,mgr,nb);
+ input2.reload(BasicTestsQ15::INPUT2_BITWISE_Q15_ID,mgr,nb);
+ break;
+
+
}
diff --git a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ31.cpp b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ31.cpp
index 6494fe3..47e62ed 100755
--- a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ31.cpp
+++ b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ31.cpp
@@ -163,6 +163,53 @@
}
+ void BasicTestsQ31::test_and_q31()
+ {
+ GET_Q31_PTR();
+
+ arm_and_q31(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ31::test_or_q31()
+ {
+ GET_Q31_PTR();
+
+ arm_or_q31(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ31::test_not_q31()
+ {
+ GET_Q31_PTR();
+
+ arm_not_q31(inp1,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ31::test_xor_q31()
+ {
+ GET_Q31_PTR();
+
+ arm_xor_q31(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
void BasicTestsQ31::setUp(Testing::testID_t id,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr)
{
@@ -426,6 +473,99 @@
input1.reload(BasicTestsQ31::MAXNEG_Q31_ID,mgr);
break;
+ case BasicTestsQ31::TEST_AND_Q31_37:
+ nb = 3;
+ ref.reload(BasicTestsQ31::REF_AND_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_AND_Q31_38:
+ nb = 8;
+ ref.reload(BasicTestsQ31::REF_AND_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+ case BasicTestsQ31::TEST_AND_Q31_39:
+ nb = 11;
+ ref.reload(BasicTestsQ31::REF_AND_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_OR_Q31_40:
+ nb = 3;
+ ref.reload(BasicTestsQ31::REF_OR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_OR_Q31_41:
+ nb = 8;
+ ref.reload(BasicTestsQ31::REF_OR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+ case BasicTestsQ31::TEST_OR_Q31_42:
+ nb = 11;
+ ref.reload(BasicTestsQ31::REF_OR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_NOT_Q31_43:
+ nb = 3;
+ ref.reload(BasicTestsQ31::REF_NOT_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_NOT_Q31_44:
+ nb = 8;
+ ref.reload(BasicTestsQ31::REF_NOT_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+ case BasicTestsQ31::TEST_NOT_Q31_45:
+ nb = 11;
+ ref.reload(BasicTestsQ31::REF_NOT_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_XOR_Q31_46:
+ nb = 3;
+ ref.reload(BasicTestsQ31::REF_XOR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ31::TEST_XOR_Q31_47:
+ nb = 8;
+ ref.reload(BasicTestsQ31::REF_XOR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+ case BasicTestsQ31::TEST_XOR_Q31_48:
+ nb = 11;
+ ref.reload(BasicTestsQ31::REF_XOR_Q31_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ31::OUT_SAMPLES_Q31_ID,mgr);
+ input1.reload(BasicTestsQ31::INPUT1_BITWISE_Q31_ID,mgr,nb);
+ input2.reload(BasicTestsQ31::INPUT2_BITWISE_Q31_ID,mgr,nb);
+ break;
+
+
}
diff --git a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ7.cpp b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ7.cpp
index 67ae9c6..83cc0b7 100755
--- a/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ7.cpp
+++ b/CMSIS/DSP/Testing/Source/Tests/BasicTestsQ7.cpp
@@ -177,6 +177,53 @@
}
+ void BasicTestsQ7::test_and_q7()
+ {
+ GET_Q7_PTR();
+
+ arm_and_q7(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ7::test_or_q7()
+ {
+ GET_Q7_PTR();
+
+ arm_or_q7(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ7::test_not_q7()
+ {
+ GET_Q7_PTR();
+
+ arm_not_q7(inp1,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void BasicTestsQ7::test_xor_q7()
+ {
+ GET_Q7_PTR();
+
+ arm_xor_q7(inp1,inp2,outp,input1.nbSamples());
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
void BasicTestsQ7::setUp(Testing::testID_t id,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr)
{
@@ -440,8 +487,102 @@
input1.reload(BasicTestsQ7::MAXNEG_Q7_ID,mgr);
break;
+ case BasicTestsQ7::TEST_AND_Q7_37:
+ nb = 15;
+ ref.reload(BasicTestsQ7::REF_AND_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_AND_Q7_38:
+ nb = 32;
+ ref.reload(BasicTestsQ7::REF_AND_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+ case BasicTestsQ7::TEST_AND_Q7_39:
+ nb = 47;
+ ref.reload(BasicTestsQ7::REF_AND_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_OR_Q7_40:
+ nb = 15;
+ ref.reload(BasicTestsQ7::REF_OR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_OR_Q7_41:
+ nb = 32;
+ ref.reload(BasicTestsQ7::REF_OR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+ case BasicTestsQ7::TEST_OR_Q7_42:
+ nb = 47;
+ ref.reload(BasicTestsQ7::REF_OR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_NOT_Q7_43:
+ nb = 15;
+ ref.reload(BasicTestsQ7::REF_NOT_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_NOT_Q7_44:
+ nb = 32;
+ ref.reload(BasicTestsQ7::REF_NOT_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+ case BasicTestsQ7::TEST_NOT_Q7_45:
+ nb = 47;
+ ref.reload(BasicTestsQ7::REF_NOT_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_XOR_Q7_46:
+ nb = 15;
+ ref.reload(BasicTestsQ7::REF_XOR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+ case BasicTestsQ7::TEST_XOR_Q7_47:
+ nb = 32;
+ ref.reload(BasicTestsQ7::REF_XOR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+ case BasicTestsQ7::TEST_XOR_Q7_48:
+ nb = 47;
+ ref.reload(BasicTestsQ7::REF_XOR_Q7_ID,mgr,nb);
+ output.create(ref.nbSamples(),BasicTestsQ7::OUT_SAMPLES_Q7_ID,mgr);
+ input1.reload(BasicTestsQ7::INPUT1_BITWISE_Q7_ID,mgr,nb);
+ input2.reload(BasicTestsQ7::INPUT2_BITWISE_Q7_ID,mgr,nb);
+ break;
+
+
+
}
-
+
diff --git a/CMSIS/DSP/Testing/Source/Tests/SupportTestsF32.cpp b/CMSIS/DSP/Testing/Source/Tests/SupportTestsF32.cpp
index 696b656..736d663 100755
--- a/CMSIS/DSP/Testing/Source/Tests/SupportTestsF32.cpp
+++ b/CMSIS/DSP/Testing/Source/Tests/SupportTestsF32.cpp
@@ -106,13 +106,372 @@
}
-
+ void SupportTestsF32::test_bitonic_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BITONIC, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_bitonic_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BITONIC, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+
+ }
+
+ void SupportTestsF32::test_bitonic_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BITONIC, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_bubble_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BUBBLE, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_bubble_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BUBBLE, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+
+ }
+
+ void SupportTestsF32::test_bubble_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_BUBBLE, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_heap_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_HEAP, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_heap_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_HEAP, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+ }
+
+ void SupportTestsF32::test_heap_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_HEAP, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_insertion_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_INSERTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_insertion_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_INSERTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+
+ }
+
+ void SupportTestsF32::test_insertion_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_INSERTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_merge_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_MERGE, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_merge_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_MERGE, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+ }
+
+ void SupportTestsF32::test_quick_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_QUICK, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_quick_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_QUICK, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+
+ }
+
+ void SupportTestsF32::test_quick_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_QUICK, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_selection_sort_out_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_SELECTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_selection_sort_in_f32()
+ {
+ float32_t *inp = input.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_SELECTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,inp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(input);
+
+ ASSERT_EQ(input,ref);
+
+ }
+
+ void SupportTestsF32::test_selection_sort_const_f32()
+ {
+ float32_t *inp = input.ptr();
+ float32_t *outp = output.ptr();
+ arm_sort_instance_f32 S;
+
+ arm_sort_init_f32(&S, ARM_SORT_SELECTION, ARM_SORT_ASCENDING);
+
+ arm_sort_f32(&S,inp,outp,this->nbSamples);
+
+ ASSERT_EMPTY_TAIL(output);
+
+ ASSERT_EQ(output,ref);
+
+ }
+
+ void SupportTestsF32::test_spline_square_f32()
+ {
+ const float32_t *inpX = inputX.ptr();
+ const float32_t *inpY = inputY.ptr();
+ const float32_t *outX = outputX.ptr();
+ float32_t *outp = output.ptr();
+
+ arm_spline_instance_f32 S;
+
+ arm_spline_init_f32(&S, 4, ARM_SPLINE_PARABOLIC_RUNOUT);
+ arm_spline_f32(&S, inpX, inpY, outX, outp, 20);
+
+ ASSERT_EMPTY_TAIL(output);
+ ASSERT_SNR(output,ref,(float32_t)SNR_THRESHOLD);
+ }
+
+ void SupportTestsF32::test_spline_sine_f32()
+ {
+ const float32_t *inpX = inputX.ptr();
+ const float32_t *inpY = inputY.ptr();
+ const float32_t *outX = outputX.ptr();
+ float32_t *outp = output.ptr();
+
+ arm_spline_instance_f32 S;
+
+ arm_spline_init_f32(&S, 9, ARM_SPLINE_NATURAL);
+ arm_spline_f32(&S, inpX, inpY, outX, outp, 33);
+
+ ASSERT_EMPTY_TAIL(output);
+ ASSERT_SNR(output,ref,(float32_t)SNR_THRESHOLD);
+ }
+
+ void SupportTestsF32::test_spline_ramp_f32()
+ {
+ const float32_t *inpX = inputX.ptr();
+ const float32_t *inpY = inputY.ptr();
+ const float32_t *outX = outputX.ptr();
+ float32_t *outp = output.ptr();
+
+ arm_spline_instance_f32 S;
+
+ arm_spline_init_f32(&S, 3, ARM_SPLINE_PARABOLIC_RUNOUT);
+ arm_spline_f32(&S, inpX, inpY, outX, outp, 30);
+
+ ASSERT_EMPTY_TAIL(output);
+ ASSERT_SNR(output,ref,(float32_t)SNR_THRESHOLD);
+ }
+
void SupportTestsF32::setUp(Testing::testID_t id,std::vector<Testing::param_t>& paramsArgs,Client::PatternMgr *mgr)
{
switch(id)
- {
-
+ {
case TEST_WEIGHTED_SUM_F32_1:
this->nbSamples = 3;
input.reload(SupportTestsF32::INPUTS_F32_ID,mgr,this->nbSamples);
@@ -263,9 +622,178 @@
break;
- }
+ case TEST_BITONIC_SORT_OUT_F32_19:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_BITONIC_SORT_16_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_BITONIC_SORT_16_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
-
+ case TEST_BITONIC_SORT_OUT_F32_20:
+ this->nbSamples = 32;
+ input.reload(SupportTestsF32::INPUT_BITONIC_SORT_32_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_BITONIC_SORT_32_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_BITONIC_SORT_IN_F32_21:
+ this->nbSamples = 32;
+ input.reload(SupportTestsF32::INPUT_BITONIC_SORT_32_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_BITONIC_SORT_32_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_BITONIC_SORT_CONST_F32_22:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_BUBBLE_SORT_OUT_F32_23:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_BUBBLE_SORT_IN_F32_24:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_BUBBLE_SORT_CONST_F32_25:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_HEAP_SORT_OUT_F32_26:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_HEAP_SORT_IN_F32_27:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_HEAP_SORT_CONST_F32_28:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_INSERTION_SORT_OUT_F32_29:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_INSERTION_SORT_IN_F32_30:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_INSERTION_SORT_CONST_F32_31:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_MERGE_SORT_OUT_F32_32:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_MERGE_SORT_CONST_F32_33:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_QUICK_SORT_OUT_F32_34:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_QUICK_SORT_IN_F32_35:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_QUICK_SORT_CONST_F32_36:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SELECTION_SORT_OUT_F32_37:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SELECTION_SORT_IN_F32_38:
+ this->nbSamples = 11;
+ input.reload(SupportTestsF32::INPUT_SORT_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SELECTION_SORT_CONST_F32_39:
+ this->nbSamples = 16;
+ input.reload(SupportTestsF32::INPUT_SORT_CONST_F32_ID,mgr,this->nbSamples);
+ ref.reload(SupportTestsF32::REF_SORT_CONST_F32_ID,mgr);
+ output.create(this->nbSamples,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SPLINE_SQUARE_F32_40:
+ inputX.reload(SupportTestsF32::INPUT_SPLINE_SQU_X_F32_ID,mgr,4);
+ inputY.reload(SupportTestsF32::INPUT_SPLINE_SQU_Y_F32_ID,mgr,4);
+ outputX.reload(SupportTestsF32::OUTPUT_SPLINE_SQU_X_F32_ID,mgr,20);
+ ref.reload(SupportTestsF32::REF_SPLINE_SQU_F32_ID,mgr,20);
+ output.create(20,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SPLINE_SINE_F32_41:
+ inputX.reload(SupportTestsF32::INPUT_SPLINE_SIN_X_F32_ID,mgr,9);
+ inputY.reload(SupportTestsF32::INPUT_SPLINE_SIN_Y_F32_ID,mgr,9);
+ outputX.reload(SupportTestsF32::OUTPUT_SPLINE_SIN_X_F32_ID,mgr,33);
+ ref.reload(SupportTestsF32::REF_SPLINE_SIN_F32_ID,mgr,33);
+ output.create(33,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ case TEST_SPLINE_RAMP_F32_42:
+ inputX.reload(SupportTestsF32::INPUT_SPLINE_RAM_X_F32_ID,mgr,3);
+ inputY.reload(SupportTestsF32::INPUT_SPLINE_RAM_Y_F32_ID,mgr,3);
+ outputX.reload(SupportTestsF32::OUTPUT_SPLINE_RAM_X_F32_ID,mgr,30);
+ ref.reload(SupportTestsF32::REF_SPLINE_RAM_F32_ID,mgr,30);
+ output.create(30,SupportTestsF32::OUT_F32_ID,mgr);
+ break;
+
+ }
}
diff --git a/CMSIS/DSP/Testing/desc.txt b/CMSIS/DSP/Testing/desc.txt
index ccc6650..d85aeb7 100644
--- a/CMSIS/DSP/Testing/desc.txt
+++ b/CMSIS/DSP/Testing/desc.txt
@@ -254,8 +254,28 @@
folder = SupportF32
Pattern INPUTS_F32_ID : Inputs6_f32.txt
+ Pattern INPUT_SORT_F32_ID : Input7_f32.txt
+ Pattern INPUT_BITONIC_SORT_16_F32_ID : Input8_f32.txt
+ Pattern INPUT_BITONIC_SORT_32_F32_ID : Input9_f32.txt
+ Pattern INPUT_SORT_CONST_F32_ID : Input10_f32.txt
+ Pattern INPUT_SPLINE_SQU_X_F32_ID : InputX11_f32.txt
+ Pattern INPUT_SPLINE_SQU_Y_F32_ID : InputY11_f32.txt
+ Pattern OUTPUT_SPLINE_SQU_X_F32_ID : OutputX11_f32.txt
+ Pattern INPUT_SPLINE_SIN_X_F32_ID : InputX12_f32.txt
+ Pattern INPUT_SPLINE_SIN_Y_F32_ID : InputY12_f32.txt
+ Pattern OUTPUT_SPLINE_SIN_X_F32_ID : OutputX12_f32.txt
+ Pattern INPUT_SPLINE_RAM_X_F32_ID : InputX13_f32.txt
+ Pattern INPUT_SPLINE_RAM_Y_F32_ID : InputY13_f32.txt
+ Pattern OUTPUT_SPLINE_RAM_X_F32_ID : OutputX13_f32.txt
Pattern WEIGHTS_F32_ID : Weights6_f32.txt
Pattern REF_F32_ID : Ref6_f32.txt
+ Pattern REF_SORT_F32_ID : Reference7_f32.txt
+ Pattern REF_BITONIC_SORT_16_F32_ID : Reference8_f32.txt
+ Pattern REF_BITONIC_SORT_32_F32_ID : Reference9_f32.txt
+ Pattern REF_SORT_CONST_F32_ID : Reference10_f32.txt
+ Pattern REF_SPLINE_SQU_F32_ID : Reference11_f32.txt
+ Pattern REF_SPLINE_SIN_F32_ID : Reference12_f32.txt
+ Pattern REF_SPLINE_RAM_F32_ID : Reference13_f32.txt
Pattern SAMPLES_F32_ID : Samples1_f32.txt
Pattern SAMPLES_Q15_ID : Samples3_q15.txt
Pattern SAMPLES_Q31_ID : Samples4_q31.txt
@@ -282,6 +302,32 @@
test_float_q7 nb=15:test_float_to_q7
test_float_q7 nb=16n:test_float_to_q7
test_float_q7 nb=16n+1:test_float_to_q7
+
+ test_bitonic_sort_f32 nb=16 outofoplace:test_bitonic_sort_out_f32
+ test_bitonic_sort_f32 nb=32 outofplace:test_bitonic_sort_out_f32
+ test_bitonic_sort_f32 nb=32 inplace:test_bitonic_sort_in_f32
+ test_bitonic_sort_f32 nb=16 const:test_bitonic_sort_const_f32
+ test_bubble_sort_f32 nb=11 outofplace:test_bubble_sort_out_f32
+ test_bubble_sort_f32 nb=11 inplace:test_bubble_sort_in_f32
+ test_bubble_sort_f32 nb=16 const:test_bubble_sort_const_f32
+ test_heap_sort_f32 nb=11 outofplace:test_heap_sort_out_f32
+ test_heap_sort_f32 nb=11 inplace:test_heap_sort_in_f32
+ test_heap_sort_f32 nb=16 const:test_heap_sort_const_f32
+ test_insertion_sort_f32 nb=11 outofplace:test_insertion_sort_out_f32
+ test_insertion_sort_f32 nb=11 inplace:test_insertion_sort_in_f32
+ test_insertion_sort_f32 nb=16 const:test_insertion_sort_const_f32
+ test_merge_sort_f32 nb=11 outofplace:test_merge_sort_out_f32
+ test_merge_sort_f32 nb=16 const:test_merge_sort_const_f32
+ test_quick_sort_f32 nb=11 outofplace:test_quick_sort_out_f32
+ test_quick_sort_f32 nb=11 inplace:test_quick_sort_in_f32
+ test_quick_sort_f32 nb=16 const:test_quick_sort_const_f32
+ test_selection_sort_f32 nb=11 outofplace:test_selection_sort_out_f32
+ test_selection_sort_f32 nb=11 inplace:test_selection_sort_in_f32
+ test_selection_sort_f32 nb=16 const:test_selection_sort_const_f32
+
+ test_spline_f32 square:test_spline_square_f32
+ test_spline_f32 sin:test_spline_sine_f32
+ test_spline_f32 ramp:test_spline_ramp_f32
}
}
@@ -470,7 +516,10 @@
Pattern MAXNEG_Q31_ID : MaxNegInput12_s32.txt
Pattern MAXNEG2_Q31_ID : MaxNeg2Input12_s32.txt
Pattern MAXPOS_Q31_ID : MaxPosInput12_s32.txt
-
+
+ Pattern INPUT1_BITWISE_Q31_ID : BitwiseInput24_s32.txt
+ Pattern INPUT2_BITWISE_Q31_ID : BitwiseInput25_s32.txt
+
Pattern REF_ADD_Q31_ID : Reference1_q31.txt
Pattern REF_SUB_Q31_ID : Reference2_q31.txt
Pattern REF_MULT_Q31_ID : Reference3_q31.txt
@@ -496,6 +545,11 @@
Pattern REF_SHIFT_POSSAT_22_Q31_ID : Shift22_q31.txt
Pattern REF_SHIFT_NEGSAT_23_Q31_ID : Shift23_q31.txt
+ Pattern REF_AND_Q31_ID : And24_s32.txt
+ Pattern REF_OR_Q31_ID : Or25_s32.txt
+ Pattern REF_NOT_Q31_ID : Not26_s32.txt
+ Pattern REF_XOR_Q31_ID : Xor27_s32.txt
+
Output OUT_SAMPLES_Q31_ID : Output
Output OUT_STATE_Q31_ID : State
@@ -550,6 +604,23 @@
Test shift:test_shift_q31
Test shift pos sat:test_shift_q31
Test shift neg sat:test_shift_q31
+
+ Test nb=3 arm_and_q31:test_and_q31
+ Test nb=4n arm_and_q31:test_and_q31
+ Test nb=4n+3 arm_and_q31:test_and_q31
+
+ Test nb=3 arm_or_q31:test_or_q31
+ Test nb=4n arm_or_q31:test_or_q31
+ Test nb=4n+3 arm_or_q31:test_or_q31
+
+ Test nb=3 arm_not_q31:test_not_q31
+ Test nb=4n arm_not_q31:test_not_q31
+ Test nb=4n+3 arm_not_q31:test_not_q31
+
+ Test nb=3 arm_xor_q31:test_xor_q31
+ Test nb=4n arm_xor_q31:test_xor_q31
+ Test nb=4n+3 arm_xor_q31:test_xor_q31
+
}
}
@@ -564,7 +635,10 @@
Pattern MAXNEG_Q15_ID : MaxNegInput12_s16.txt
Pattern MAXNEG2_Q15_ID : MaxNeg2Input12_s16.txt
Pattern MAXPOS_Q15_ID : MaxPosInput12_s16.txt
-
+
+ Pattern INPUT1_BITWISE_Q15_ID : BitwiseInput24_s16.txt
+ Pattern INPUT2_BITWISE_Q15_ID : BitwiseInput25_s16.txt
+
Pattern REF_ADD_Q15_ID : Reference1_q15.txt
Pattern REF_SUB_Q15_ID : Reference2_q15.txt
Pattern REF_MULT_Q15_ID : Reference3_q15.txt
@@ -590,6 +664,11 @@
Pattern REF_SHIFT_POSSAT_22_Q15_ID : Shift22_q15.txt
Pattern REF_SHIFT_NEGSAT_23_Q15_ID : Shift23_q15.txt
+ Pattern REF_AND_Q15_ID : And24_s16.txt
+ Pattern REF_OR_Q15_ID : Or25_s16.txt
+ Pattern REF_NOT_Q15_ID : Not26_s16.txt
+ Pattern REF_XOR_Q15_ID : Xor27_s16.txt
+
Output OUT_SAMPLES_Q15_ID : Output
Output OUT_STATE_Q15_ID : State
@@ -644,6 +723,23 @@
Test shift:test_shift_q15
Test shift pos sat:test_shift_q15
Test shift neg sat:test_shift_q15
+
+ Test nb=7 arm_and_q15:test_and_q15
+ Test nb=8n arm_and_q15:test_and_q15
+ Test nb=8n+7 arm_and_q15:test_and_q15
+
+ Test nb=7 arm_or_q15:test_or_q15
+ Test nb=8n arm_or_q15:test_or_q15
+ Test nb=8n+7 arm_or_q15:test_or_q15
+
+ Test nb=7 arm_not_q15:test_not_q15
+ Test nb=8n arm_not_q15:test_not_q15
+ Test nb=8n+7 arm_not_q15:test_not_q15
+
+ Test nb=7 arm_xor_q15:test_xor_q15
+ Test nb=8n arm_xor_q15:test_xor_q15
+ Test nb=8n+7 arm_xor_q15:test_xor_q15
+
}
}
@@ -658,7 +754,10 @@
Pattern MAXNEG_Q7_ID : MaxNegInput12_s8.txt
Pattern MAXNEG2_Q7_ID : MaxNeg2Input12_s8.txt
Pattern MAXPOS_Q7_ID : MaxPosInput12_s8.txt
-
+
+ Pattern INPUT1_BITWISE_Q7_ID : BitwiseInput24_s8.txt
+ Pattern INPUT2_BITWISE_Q7_ID : BitwiseInput25_s8.txt
+
Pattern REF_ADD_Q7_ID : Reference1_q7.txt
Pattern REF_SUB_Q7_ID : Reference2_q7.txt
Pattern REF_MULT_Q7_ID : Reference3_q7.txt
@@ -684,6 +783,11 @@
Pattern REF_SHIFT_POSSAT_22_Q7_ID : Shift22_q7.txt
Pattern REF_SHIFT_NEGSAT_23_Q7_ID : Shift23_q7.txt
+ Pattern REF_AND_Q7_ID : And24_s8.txt
+ Pattern REF_OR_Q7_ID : Or25_s8.txt
+ Pattern REF_NOT_Q7_ID : Not26_s8.txt
+ Pattern REF_XOR_Q7_ID : Xor27_s8.txt
+
Output OUT_SAMPLES_Q7_ID : Output
Output OUT_STATE_Q7_ID : State
@@ -738,6 +842,22 @@
Test shift:test_shift_q7
Test shift pos sat:test_shift_q7
Test shift neg sat:test_shift_q7
+
+ Test nb=15 arm_and_q7:test_and_q7
+ Test nb=16n arm_and_q7:test_and_q7
+ Test nb=16n+15 arm_and_q7:test_and_q7
+
+ Test nb=15 arm_or_q7:test_or_q7
+ Test nb=16n arm_or_q7:test_or_q7
+ Test nb=16n+15 arm_or_q7:test_or_q7
+
+ Test nb=15 arm_not_q7:test_not_q7
+ Test nb=16n arm_not_q7:test_not_q7
+ Test nb=16n+15 arm_not_q7:test_not_q7
+
+ Test nb=15 arm_xor_q7:test_xor_q7
+ Test nb=16n arm_xor_q7:test_xor_q7
+ Test nb=16n+15 arm_xor_q7:test_xor_q7
}
}
}