CMSIS-DSP: Improvement to test framework
Added support for A32.
Still some issues with cycle model.
diff --git a/CMSIS/DSP/Include/arm_math.h b/CMSIS/DSP/Include/arm_math.h
index 7dca0a4..a5eb4ff 100644
--- a/CMSIS/DSP/Include/arm_math.h
+++ b/CMSIS/DSP/Include/arm_math.h
@@ -145,9 +145,9 @@
    *
    * Select Helium versions of the int and fixed point algorithms.
    *
-   * - ARM_MATH_FLOAT16:
+   * - ARM_MATH_MVE_FLOAT16:
    *
-   * Float16 implementations of some algorithms (Requires MVE extension).
+   * MVE Float16 implementations of some algorithms (Requires MVE extension).
    *
    * <hr>
    * \section pack CMSIS-DSP in ARM::CMSIS Pack
diff --git a/CMSIS/DSP/Include/arm_math_f16.h b/CMSIS/DSP/Include/arm_math_f16.h
index e537a7d..0b8c19c 100755
--- a/CMSIS/DSP/Include/arm_math_f16.h
+++ b/CMSIS/DSP/Include/arm_math_f16.h
@@ -54,8 +54,8 @@
   #define ARM_FLOAT16_SUPPORTED
   #endif
 #else
-  /* HW Float16 not yet well supported on gcc for M55 */
-  #if !defined(__CMSIS_GCC_H)
+  /* HW Float16 not yet well supported on some configs */
+  #if !defined(__CMSIS_GCC_H) && !defined(DISABLEFLOAT16)
     #define ARM_FLOAT16_SUPPORTED
   #endif
 #endif
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/Include/ARMCA32.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/Include/ARMCA32.h
new file mode 100755
index 0000000..9c28bea
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/Include/ARMCA32.h
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     ARMCA5.h
+ * @brief    CMSIS Cortex-A5 Core Peripheral Access Layer Header File 
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARMCA32_H__
+#define __ARMCA32_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,        /*!< Software Generated Interrupt 0 */
+  SGI1_IRQn            =  1,        /*!< Software Generated Interrupt 1 */
+  SGI2_IRQn            =  2,        /*!< Software Generated Interrupt 2 */
+  SGI3_IRQn            =  3,        /*!< Software Generated Interrupt 3 */
+  SGI4_IRQn            =  4,        /*!< Software Generated Interrupt 4 */
+  SGI5_IRQn            =  5,        /*!< Software Generated Interrupt 5 */
+  SGI6_IRQn            =  6,        /*!< Software Generated Interrupt 6 */
+  SGI7_IRQn            =  7,        /*!< Software Generated Interrupt 7 */
+  SGI8_IRQn            =  8,        /*!< Software Generated Interrupt 8 */
+  SGI9_IRQn            =  9,        /*!< Software Generated Interrupt 9 */
+  SGI10_IRQn           = 10,        /*!< Software Generated Interrupt 10 */
+  SGI11_IRQn           = 11,        /*!< Software Generated Interrupt 11 */
+  SGI12_IRQn           = 12,        /*!< Software Generated Interrupt 12 */
+  SGI13_IRQn           = 13,        /*!< Software Generated Interrupt 13 */
+  SGI14_IRQn           = 14,        /*!< Software Generated Interrupt 14 */
+  SGI15_IRQn           = 15,        /*!< Software Generated Interrupt 15 */
+
+/******  Cortex-A5 Processor Exceptions Numbers ****************************************/
+  GlobalTimer_IRQn     = 27,        /*!< Global Timer Interrupt                        */
+  PrivTimer_IRQn       = 29,        /*!< Private Timer Interrupt                       */
+  PrivWatchdog_IRQn    = 30,        /*!< Private Watchdog Interrupt                    */
+
+/******  Platform Exceptions Numbers ***************************************************/
+  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */
+  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */
+  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */
+  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */
+  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */
+  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */
+  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */
+  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */
+  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */
+  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */
+  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */
+  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */
+  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */
+  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */
+  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */
+  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */
+} IRQn_Type;
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+/* Peripheral and RAM base address */
+#define VE_A5_MP_FLASH_BASE0                  (0x00000000UL)                                /*!< (FLASH0     ) Base Address */
+#define VE_A5_MP_FLASH_BASE1                  (0x0C000000UL)                                /*!< (FLASH1     ) Base Address */
+#define VE_A5_MP_SRAM_BASE                    (0x14000000UL)                                /*!< (SRAM       ) Base Address */
+#define VE_A5_MP_PERIPH_BASE_CS2              (0x18000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_VRAM_BASE                    (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (VRAM       ) Base Address */
+#define VE_A5_MP_ETHERNET_BASE                (0x02000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (ETHERNET   ) Base Address */
+#define VE_A5_MP_USB_BASE                     (0x03000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (USB        ) Base Address */
+#define VE_A5_MP_PERIPH_BASE_CS3              (0x1C000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_DAP_BASE                     (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (LOCAL DAP  ) Base Address */
+#define VE_A5_MP_SYSTEM_REG_BASE              (0x00010000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SYSTEM REG ) Base Address */
+#define VE_A5_MP_SERIAL_BASE                  (0x00030000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SERIAL     ) Base Address */
+#define VE_A5_MP_AACI_BASE                    (0x00040000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (AACI       ) Base Address */
+#define VE_A5_MP_MMCI_BASE                    (0x00050000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (MMCI       ) Base Address */
+#define VE_A5_MP_KMI0_BASE                    (0x00060000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (KMI0       ) Base Address */
+#define VE_A5_MP_UART_BASE                    (0x00090000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART       ) Base Address */
+#define VE_A5_MP_WDT_BASE                     (0x000F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (WDT        ) Base Address */
+#define VE_A5_MP_TIMER_BASE                   (0x00110000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (TIMER      ) Base Address */
+#define VE_A5_MP_DVI_BASE                     (0x00160000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (DVI        ) Base Address */
+#define VE_A5_MP_RTC_BASE                     (0x00170000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (RTC        ) Base Address */
+#define VE_A5_MP_UART4_BASE                   (0x001B0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART4      ) Base Address */
+#define VE_A5_MP_CLCD_BASE                    (0x001F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (CLCD       ) Base Address */
+#define VE_A5_MP_PRIVATE_PERIPH_BASE          (0x2C000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_GIC_DISTRIBUTOR_BASE         (0x00001000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST   ) Base Address */
+#define VE_A5_MP_GIC_INTERFACE_BASE           (0x00000100UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */
+#define VE_A5_MP_PRIVATE_TIMER                (0x00000600UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM       ) Base Address */
+#define VE_A5_MP_PL310_BASE                   (0x000F0000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310    ) Base Address */
+#define VE_A5_MP_SSRAM_BASE                   (0x2E000000UL)                                /*!< (System SRAM) Base Address */
+#define VE_A5_MP_DRAM_BASE                    (0x80000000UL)                                /*!< (DRAM       ) Base Address */
+#define GIC_DISTRIBUTOR_BASE                  VE_A5_MP_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                    VE_A5_MP_GIC_INTERFACE_BASE
+#define TIMER_BASE                            VE_A5_MP_PRIVATE_TIMER
+
+//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
+//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
+#define L2C_310_BASE                          VE_A5_MP_PL310_BASE
+
+/* --------  Configuration of the Cortex-A5 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /* Core revision r0p0                            */
+#define __CORTEX_A           5U    /* Cortex-A5 Core                                */
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        1U    /* TIM present                                   */
+#define __L2C_PRESENT        0U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include <system_ARMCA32.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __ARMCA5_H__
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/lnk.sct b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/lnk.sct
new file mode 100755
index 0000000..7eba725
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/lnk.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h
new file mode 100755
index 0000000..55badff
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h
@@ -0,0 +1,101 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00400000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+//#define __RAM_BASE       0x80200000#
+#define __RAM_BASE       0x80600000
+#define __RAM_SIZE       0x00700000
+
+#define __RW_DATA_SIZE   0x00200000
+#define __ZI_DATA_SIZE   0x00200000
+
+#define __STACK_SIZE     0x00007000
+#define __HEAP_SIZE      0x00200000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/system_ARMCA5.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/system_ARMCA5.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC5/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/lnk.sct b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/lnk.sct
new file mode 100755
index 0000000..ca790a0
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/lnk.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a32 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA32.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    ALIGN 64 EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) ALIGN 64 EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}
\ No newline at end of file
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h
new file mode 100755
index 0000000..d9783db
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA32_H
+#define __MEM_ARMCA32_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x00000000
+#define __ROM_SIZE       0x00400000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+//#define __RAM_BASE       0x80200000#
+#define __RAM_BASE       0x0500000
+#define __RAM_SIZE       0x00700000
+
+#define __RW_DATA_SIZE   0x00200000
+#define __ZI_DATA_SIZE   0x00200000
+
+#define __STACK_SIZE     0x00007000
+#define __HEAP_SIZE      0x00200000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/system_ARMCA32.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/system_ARMCA32.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/AC6/system_ARMCA32.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/lnk.ld b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/lnk.ld
new file mode 100755
index 0000000..ec3a401
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/lnk.ld
@@ -0,0 +1,183 @@
+#include "mem_ARMCA5.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __heap_base = .;
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h
new file mode 100755
index 0000000..44a1b31
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h
@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00400000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80400000
+#define __RAM_SIZE       0x00300000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00003000
+#define __HEAP_SIZE      0x00100000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80800000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/system_ARMCA5.h b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/system_ARMCA5.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/LinkScripts/GCC/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC5/startup_ARMCA5.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC5/startup_ARMCA5.c
new file mode 100755
index 0000000..17da1c8
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC5/startup_ARMCA5.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  volatile int i;
+#if 0
+  __ASM volatile(
+  "LDR    __current_pc, =Reset_Handler                        \n"
+  "LDR    __current_pc, =Undef_Handler                        \n"
+  "LDR    __current_pc, =SVC_Handler                          \n"
+  "LDR    __current_pc, =PAbt_Handler                         \n"
+  "LDR    __current_pc, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    __current_pc, =IRQ_Handler                          \n"
+  "LDR    __current_pc, =FIQ_Handler                          \n"
+  );
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+#if 0
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC6/startup_ARMCA32.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC6/startup_ARMCA32.c
new file mode 100755
index 0000000..3236a0e
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/AC6/startup_ARMCA32.c
@@ -0,0 +1,141 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA32.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  //"BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  //"BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  6)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  "LDR     r0,=Image$$TTB$$ZI$$Base                \n"
+  "MCR     p15, 0, r0, c2, c0, 0                   \n"
+
+  "LDR     r0, =0xFFFFFFFF                         \n"            
+  "MCR     p15, 0, r0, c3, c0, 0                   \n"      // Write Domain Access Control Register
+
+
+
+  "LDR     SP, =Image$$ARM_LIB_STACK$$ZI$$Limit      \n"
+
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x2                            \n"   // Clear A bit  1 to disable strict alignment fault checking
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  //"CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/startup_ARMCA5.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/startup_ARMCA5.c
new file mode 100755
index 0000000..7772401
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/startup_ARMCA5.c
@@ -0,0 +1,142 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+void support(void);
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+extern void initialise_monitor_handles(void);
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/support.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/support.c
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/Startup/GCC/support.c
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/irq_ctrl_gic.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/irq_ctrl_gic.c
new file mode 100755
index 0000000..88e1f58
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/irq_ctrl_gic.c
@@ -0,0 +1,387 @@
+#if 0
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t     IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  // Ignore CPUID field (software generated interrupts)
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+  int32_t status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      cfg = 0x00U;
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0U;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1U;
+      } else {
+        secure = 0U;
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFFU;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+  IRQn_Type irq = (IRQn_Type)irqn;
+
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt (irq);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/mmu_ARMCA32.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/mmu_ARMCA32.c
new file mode 100755
index 0000000..f32ebd8
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/mmu_ARMCA32.c
@@ -0,0 +1,29 @@
+#include "cmsis_compiler.h"
+#include "cmsis_cp15.h"
+#include "mem_ARMCA32.h"
+
+// TTB base address
+#define TTB_BASE ((uint32_t*)__TTB_BASE)
+
+
+void MMU_CreateTranslationTable(void)
+{
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x1  (Inner WB WA)
+    ; 5     - NOS     0x0  (Non-shared)
+    ; 4:3   - RGN     0x01 (Outer WB WA)
+    ; 2     - IMP     0x0  (Implementation Defined)
+    ; 1     - S       0x0  (Non-shared)
+    ; 0     - IRGN[1] 0x0  (Inner WB WA) */
+    __set_TTBR0(__TTB_BASE);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(0xFFFFFFFF);
+    __ISB();
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMCA32/system_ARMCA32.c b/CMSIS/DSP/Platforms/FVP/ARMCA32/system_ARMCA32.c
new file mode 100755
index 0000000..72e0e82
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMCA32/system_ARMCA32.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+//#include "irq_ctrl.h"
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // Create Translation Table
+  //MMU_CreateTranslationTable();
+
+  // Enable MMU
+  //MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  //L2C_Enable();
+#endif
+
+  // IRQ Initialize
+  //IRQ_Initialize();
+
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/Include/ARMCA32.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Include/ARMCA32.h
new file mode 100755
index 0000000..9c28bea
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Include/ARMCA32.h
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     ARMCA5.h
+ * @brief    CMSIS Cortex-A5 Core Peripheral Access Layer Header File 
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARMCA32_H__
+#define __ARMCA32_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,        /*!< Software Generated Interrupt 0 */
+  SGI1_IRQn            =  1,        /*!< Software Generated Interrupt 1 */
+  SGI2_IRQn            =  2,        /*!< Software Generated Interrupt 2 */
+  SGI3_IRQn            =  3,        /*!< Software Generated Interrupt 3 */
+  SGI4_IRQn            =  4,        /*!< Software Generated Interrupt 4 */
+  SGI5_IRQn            =  5,        /*!< Software Generated Interrupt 5 */
+  SGI6_IRQn            =  6,        /*!< Software Generated Interrupt 6 */
+  SGI7_IRQn            =  7,        /*!< Software Generated Interrupt 7 */
+  SGI8_IRQn            =  8,        /*!< Software Generated Interrupt 8 */
+  SGI9_IRQn            =  9,        /*!< Software Generated Interrupt 9 */
+  SGI10_IRQn           = 10,        /*!< Software Generated Interrupt 10 */
+  SGI11_IRQn           = 11,        /*!< Software Generated Interrupt 11 */
+  SGI12_IRQn           = 12,        /*!< Software Generated Interrupt 12 */
+  SGI13_IRQn           = 13,        /*!< Software Generated Interrupt 13 */
+  SGI14_IRQn           = 14,        /*!< Software Generated Interrupt 14 */
+  SGI15_IRQn           = 15,        /*!< Software Generated Interrupt 15 */
+
+/******  Cortex-A5 Processor Exceptions Numbers ****************************************/
+  GlobalTimer_IRQn     = 27,        /*!< Global Timer Interrupt                        */
+  PrivTimer_IRQn       = 29,        /*!< Private Timer Interrupt                       */
+  PrivWatchdog_IRQn    = 30,        /*!< Private Watchdog Interrupt                    */
+
+/******  Platform Exceptions Numbers ***************************************************/
+  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */
+  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */
+  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */
+  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */
+  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */
+  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */
+  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */
+  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */
+  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */
+  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */
+  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */
+  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */
+  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */
+  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */
+  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */
+  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */
+} IRQn_Type;
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+/* Peripheral and RAM base address */
+#define VE_A5_MP_FLASH_BASE0                  (0x00000000UL)                                /*!< (FLASH0     ) Base Address */
+#define VE_A5_MP_FLASH_BASE1                  (0x0C000000UL)                                /*!< (FLASH1     ) Base Address */
+#define VE_A5_MP_SRAM_BASE                    (0x14000000UL)                                /*!< (SRAM       ) Base Address */
+#define VE_A5_MP_PERIPH_BASE_CS2              (0x18000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_VRAM_BASE                    (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (VRAM       ) Base Address */
+#define VE_A5_MP_ETHERNET_BASE                (0x02000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (ETHERNET   ) Base Address */
+#define VE_A5_MP_USB_BASE                     (0x03000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (USB        ) Base Address */
+#define VE_A5_MP_PERIPH_BASE_CS3              (0x1C000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_DAP_BASE                     (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (LOCAL DAP  ) Base Address */
+#define VE_A5_MP_SYSTEM_REG_BASE              (0x00010000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SYSTEM REG ) Base Address */
+#define VE_A5_MP_SERIAL_BASE                  (0x00030000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SERIAL     ) Base Address */
+#define VE_A5_MP_AACI_BASE                    (0x00040000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (AACI       ) Base Address */
+#define VE_A5_MP_MMCI_BASE                    (0x00050000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (MMCI       ) Base Address */
+#define VE_A5_MP_KMI0_BASE                    (0x00060000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (KMI0       ) Base Address */
+#define VE_A5_MP_UART_BASE                    (0x00090000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART       ) Base Address */
+#define VE_A5_MP_WDT_BASE                     (0x000F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (WDT        ) Base Address */
+#define VE_A5_MP_TIMER_BASE                   (0x00110000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (TIMER      ) Base Address */
+#define VE_A5_MP_DVI_BASE                     (0x00160000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (DVI        ) Base Address */
+#define VE_A5_MP_RTC_BASE                     (0x00170000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (RTC        ) Base Address */
+#define VE_A5_MP_UART4_BASE                   (0x001B0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART4      ) Base Address */
+#define VE_A5_MP_CLCD_BASE                    (0x001F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (CLCD       ) Base Address */
+#define VE_A5_MP_PRIVATE_PERIPH_BASE          (0x2C000000UL)                                /*!< (Peripheral ) Base Address */
+#define VE_A5_MP_GIC_DISTRIBUTOR_BASE         (0x00001000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST   ) Base Address */
+#define VE_A5_MP_GIC_INTERFACE_BASE           (0x00000100UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */
+#define VE_A5_MP_PRIVATE_TIMER                (0x00000600UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM       ) Base Address */
+#define VE_A5_MP_PL310_BASE                   (0x000F0000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310    ) Base Address */
+#define VE_A5_MP_SSRAM_BASE                   (0x2E000000UL)                                /*!< (System SRAM) Base Address */
+#define VE_A5_MP_DRAM_BASE                    (0x80000000UL)                                /*!< (DRAM       ) Base Address */
+#define GIC_DISTRIBUTOR_BASE                  VE_A5_MP_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                    VE_A5_MP_GIC_INTERFACE_BASE
+#define TIMER_BASE                            VE_A5_MP_PRIVATE_TIMER
+
+//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
+//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
+#define L2C_310_BASE                          VE_A5_MP_PL310_BASE
+
+/* --------  Configuration of the Cortex-A5 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /* Core revision r0p0                            */
+#define __CORTEX_A           5U    /* Cortex-A5 Core                                */
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        1U    /* TIM present                                   */
+#define __L2C_PRESENT        0U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include <system_ARMCA32.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __ARMCA5_H__
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/lnk.sct b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/lnk.sct
new file mode 100755
index 0000000..7eba725
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/lnk.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h
new file mode 100755
index 0000000..55badff
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/mem_ARMCA5.h
@@ -0,0 +1,101 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00400000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+//#define __RAM_BASE       0x80200000#
+#define __RAM_BASE       0x80600000
+#define __RAM_SIZE       0x00700000
+
+#define __RW_DATA_SIZE   0x00200000
+#define __ZI_DATA_SIZE   0x00200000
+
+#define __STACK_SIZE     0x00007000
+#define __HEAP_SIZE      0x00200000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/system_ARMCA5.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/system_ARMCA5.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC5/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/lnk.sct b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/lnk.sct
new file mode 100755
index 0000000..808b793
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/lnk.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a32 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA32.h"
+
+SDRAM __ROM_BASE        ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+  }
+  
+  RW_DATA __RAM_BASE NOCOMPRESS __RW_DATA_SIZE
+  {       
+  * (+RO-DATA)   
+    * (+RW,+ZI)    
+  }                   ; Application RW data (.data)
+  
+             ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                )    ALIGN 64 EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) ALIGN 64 EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}
\ No newline at end of file
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h
new file mode 100755
index 0000000..4d23c9d
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA32_H
+#define __MEM_ARMCA32_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x00000000
+#define __ROM_SIZE       0x100000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+//#define __RAM_BASE       0x80200000#
+#define __RAM_BASE       0x0500000
+#define __RAM_SIZE       0x00700000
+
+#define __RW_DATA_SIZE   0xF0000
+#define __ZI_DATA_SIZE   0x00200000
+
+#define __STACK_SIZE     0x00007000
+#define __HEAP_SIZE      0x00200000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00005000
+
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/system_ARMCA32.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/system_ARMCA32.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/system_ARMCA32.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/lnk.ld b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/lnk.ld
new file mode 100755
index 0000000..ec3a401
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/lnk.ld
@@ -0,0 +1,183 @@
+#include "mem_ARMCA5.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __heap_base = .;
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h
new file mode 100755
index 0000000..44a1b31
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/mem_ARMCA5.h
@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00400000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <i> For compatibility with MMU config the sections must be multiple of 1MB
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
+//   <h> Data Sections
+//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   </h>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80400000
+#define __RAM_SIZE       0x00300000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00003000
+#define __HEAP_SIZE      0x00100000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
+//   <i> The TLB L2 entries are placed after the L1 in the MMU config
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80800000
+#define __TTB_SIZE       0x00005000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/system_ARMCA5.h b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/system_ARMCA5.h
new file mode 100755
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/GCC/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC5/startup_ARMCA5.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC5/startup_ARMCA5.c
new file mode 100755
index 0000000..17da1c8
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC5/startup_ARMCA5.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  volatile int i;
+#if 0
+  __ASM volatile(
+  "LDR    __current_pc, =Reset_Handler                        \n"
+  "LDR    __current_pc, =Undef_Handler                        \n"
+  "LDR    __current_pc, =SVC_Handler                          \n"
+  "LDR    __current_pc, =PAbt_Handler                         \n"
+  "LDR    __current_pc, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    __current_pc, =IRQ_Handler                          \n"
+  "LDR    __current_pc, =FIQ_Handler                          \n"
+  );
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+#if 0
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC6/startup_ARMCA32.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC6/startup_ARMCA32.c
new file mode 100755
index 0000000..9fd3a81
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC6/startup_ARMCA32.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA32.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  //"BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  //"BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  6)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  "LDR     r0,=Image$$TTB$$ZI$$Base                \n"
+  "MCR     p15, 0, r0, c2, c0, 0                   \n"
+
+  "LDR     r0, =0xFFFFFFFF                         \n"            
+  "MCR     p15, 0, r0, c3, c0, 0                   \n"      // Write Domain Access Control Register
+
+);
+
+  #if defined(__ARM_NEON) || defined(__ARM_FP)
+//----------------------------------------------------------------
+// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+// Enables Full Access i.e. in both privileged and non privileged modes
+//----------------------------------------------------------------
+__ASM volatile(
+        "MRC     p15, 0, r0, c1, c0, 2 \n"      // Read Coprocessor Access Control Register (CPACR)
+        "ORR     r0, r0, #(0xF << 20) \n"       // Enable access to CP 10 & 11
+        "MCR     p15, 0, r0, c1, c0, 2 \n"      // Write Coprocessor Access Control Register (CPACR)
+        "ISB \n"
+
+//----------------------------------------------------------------
+// Switch on the VFP and NEON hardware
+//----------------------------------------------------------------
+
+        "MOV     r0, #0x40000000 \n"
+        "VMSR    FPEXC, r0 \n"                   // Write FPEXC register, EN bit set
+);
+#endif
+
+__ASM volatile(
+  "LDR     SP, =Image$$ARM_LIB_STACK$$ZI$$Limit      \n"
+
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  
+  "BIC     R0, R0, #0x2                            \n"   // Clear A bit  1 to disable strict alignment fault checking
+  "ORR     R0, R0, #(0x1 << 11)                    \n"  // Set Z bit 11 to enable branch prediction
+  //"BIC     R0, R0, #(0x1 << 13)
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  //"CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+void enable_caches(void)
+{
+__ASM volatile(
+
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "ORR     R0, R0, #(0x1 << 12)                    \n"  // Set I bit 12 to enable I Cache
+  "ORR     R0, R0, #(0x1 <<  2)                    \n"  // Set C bit  2 to enable D Cache
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  );
+}
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/startup_ARMCA5.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/startup_ARMCA5.c
new file mode 100755
index 0000000..7772401
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/startup_ARMCA5.c
@@ -0,0 +1,142 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+void support(void);
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+extern void initialise_monitor_handles(void);
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/support.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/support.c
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/GCC/support.c
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/irq_ctrl_gic.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/irq_ctrl_gic.c
new file mode 100755
index 0000000..88e1f58
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/irq_ctrl_gic.c
@@ -0,0 +1,387 @@
+#if 0
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t     IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  // Ignore CPUID field (software generated interrupts)
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+  int32_t status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      cfg = 0x00U;
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0U;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1U;
+      } else {
+        secure = 0U;
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFFU;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+  IRQn_Type irq = (IRQn_Type)irqn;
+
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt (irq);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/mmu_ARMCA32.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/mmu_ARMCA32.c
new file mode 100755
index 0000000..f32ebd8
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/mmu_ARMCA32.c
@@ -0,0 +1,29 @@
+#include "cmsis_compiler.h"
+#include "cmsis_cp15.h"
+#include "mem_ARMCA32.h"
+
+// TTB base address
+#define TTB_BASE ((uint32_t*)__TTB_BASE)
+
+
+void MMU_CreateTranslationTable(void)
+{
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x1  (Inner WB WA)
+    ; 5     - NOS     0x0  (Non-shared)
+    ; 4:3   - RGN     0x01 (Outer WB WA)
+    ; 2     - IMP     0x0  (Implementation Defined)
+    ; 1     - S       0x0  (Non-shared)
+    ; 0     - IRGN[1] 0x0  (Inner WB WA) */
+    __set_TTBR0(__TTB_BASE);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(0xFFFFFFFF);
+    __ISB();
+}
diff --git a/CMSIS/DSP/Platforms/IPSS/ARMCA32/system_ARMCA32.c b/CMSIS/DSP/Platforms/IPSS/ARMCA32/system_ARMCA32.c
new file mode 100755
index 0000000..45e9f9d
--- /dev/null
+++ b/CMSIS/DSP/Platforms/IPSS/ARMCA32/system_ARMCA32.c
@@ -0,0 +1,486 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version  V1.0.1
+ * @date     13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+
+#include <rt_sys.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+
+#define SERIAL_BASE_ADDRESS (0x13000000)
+
+#define SERIAL_DATA  *((volatile unsigned *) SERIAL_BASE_ADDRESS)
+
+int stdout_putchar(char txchar)
+{
+    SERIAL_DATA = txchar; 
+    return(txchar);                    
+}
+
+int stderr_putchar(char txchar)
+{
+    return stdout_putchar(txchar);
+}
+
+void ttywrch (int ch)
+{
+  stdout_putchar(ch);
+}
+
+extern void enable_caches(void);
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+enable_caches();
+
+}
+
+__attribute__((constructor(255)))
+void platform_init(void)
+{
+    printf("\n_[TEST START]____________________________________________________\n");
+}
+
+
+#if __IS_COMPILER_ARM_COMPILER_6__
+__asm(".global __use_no_semihosting\n\t");
+#   ifndef __MICROLIB
+__asm(".global __ARM_use_no_argv\n\t");
+#   endif
+#endif
+
+/**
+   Writes the character specified by c (converted to an unsigned char) to
+   the output stream pointed to by stream, at the position indicated by the
+   associated file position indicator (if defined), and advances the
+   indicator appropriately. If the file position indicator is not defined,
+   the character is appended to the output stream.
+ 
+  \param[in] c       Character
+  \param[in] stream  Stream handle
+ 
+  \return    The character written. If a write error occurs, the error
+             indicator is set and fputc returns EOF.
+*/
+__attribute__((weak))
+int fputc (int c, FILE * stream) 
+{
+    if (stream == &__stdout) {
+        return (stdout_putchar(c));
+    }
+
+    if (stream == &__stderr) {
+        return (stderr_putchar(c));
+    }
+
+    return (-1);
+}
+
+/* IO device file handles. */
+#define FH_STDIN    0x8001
+#define FH_STDOUT   0x8002
+#define FH_STDERR   0x8003
+
+const char __stdin_name[]  = ":STDIN";
+const char __stdout_name[] = ":STDOUT";
+const char __stderr_name[] = ":STDERR";
+
+#define RETARGET_SYS        1
+#define RTE_Compiler_IO_STDOUT  1
+#define RTE_Compiler_IO_STDERR  1
+/**
+  Defined in rt_sys.h, this function opens a file.
+ 
+  The _sys_open() function is required by fopen() and freopen(). These
+  functions in turn are required if any file input/output function is to
+  be used.
+  The openmode parameter is a bitmap whose bits mostly correspond directly to
+  the ISO mode specification. Target-dependent extensions are possible, but
+  freopen() must also be extended.
+ 
+  \param[in] name     File name
+  \param[in] openmode Mode specification bitmap
+ 
+  \return    The return value is ?1 if an error occurs.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+FILEHANDLE _sys_open (const char *name, int openmode) {
+#if (!defined(RTE_Compiler_IO_File))
+  (void)openmode;
+#endif
+ 
+  if (name == NULL) {
+    return (-1);
+  }
+ 
+  if (name[0] == ':') {
+    if (strcmp(name, ":STDIN") == 0) {
+      return (FH_STDIN);
+    }
+    if (strcmp(name, ":STDOUT") == 0) {
+      return (FH_STDOUT);
+    }
+    if (strcmp(name, ":STDERR") == 0) {
+      return (FH_STDERR);
+    }
+    return (-1);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_open(name, openmode));
+#endif
+#else
+  return (-1);
+#endif
+}
+#endif
+ 
+ 
+/**
+  Defined in rt_sys.h, this function closes a file previously opened
+  with _sys_open().
+  
+  This function must be defined if any input/output function is to be used.
+ 
+  \param[in] fh File handle
+ 
+  \return    The return value is 0 if successful. A nonzero value indicates
+             an error.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_close (FILEHANDLE fh) {
+ 
+  switch (fh) {
+    case FH_STDIN:
+      return (0);
+    case FH_STDOUT:
+      return (0);
+    case FH_STDERR:
+      return (0);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_close(fh));
+#endif
+#else
+  return (-1);
+#endif
+}
+#endif
+ 
+ 
+/**
+  Defined in rt_sys.h, this function writes the contents of a buffer to a file
+  previously opened with _sys_open().
+ 
+  \note The mode parameter is here for historical reasons. It contains
+        nothing useful and must be ignored.
+ 
+  \param[in] fh   File handle
+  \param[in] buf  Data buffer
+  \param[in] len  Data length
+  \param[in] mode Ignore this parameter
+ 
+  \return    The return value is either:
+             - a positive number representing the number of characters not
+               written (so any nonzero return value denotes a failure of
+               some sort)
+             - a negative number indicating an error.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) {
+#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR))
+  int ch;
+#elif (!defined(RTE_Compiler_IO_File))
+  (void)buf;
+  (void)len;
+#endif
+  (void)mode;
+ 
+  switch (fh) {
+    case FH_STDIN:
+      return (-1);
+    case FH_STDOUT:
+#ifdef RTE_Compiler_IO_STDOUT
+      for (; len; len--) {
+        ch = *buf++;
+
+        stdout_putchar(ch);
+      }
+#endif
+      return (0);
+    case FH_STDERR:
+#ifdef RTE_Compiler_IO_STDERR
+      for (; len; len--) {
+        ch = *buf++;
+
+        stderr_putchar(ch);
+      }
+#endif
+      return (0);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_write(fh, buf, len));
+#endif
+#else
+  return (-1);
+#endif
+}
+#endif
+ 
+ 
+/**
+  Defined in rt_sys.h, this function reads the contents of a file into a buffer.
+ 
+  Reading up to and including the last byte of data does not turn on the EOF
+  indicator. The EOF indicator is only reached when an attempt is made to read
+  beyond the last byte of data. The target-independent code is capable of
+  handling:
+    - the EOF indicator being returned in the same read as the remaining bytes
+      of data that precede the EOF
+    - the EOF indicator being returned on its own after the remaining bytes of
+      data have been returned in a previous read.
+ 
+  \note The mode parameter is here for historical reasons. It contains
+        nothing useful and must be ignored.
+ 
+  \param[in] fh   File handle
+  \param[in] buf  Data buffer
+  \param[in] len  Data length
+  \param[in] mode Ignore this parameter
+ 
+  \return     The return value is one of the following:
+              - The number of bytes not read (that is, len - result number of
+                bytes were read).
+              - An error indication.
+              - An EOF indicator. The EOF indication involves the setting of
+                0x80000000 in the normal result.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) {
+#ifdef RTE_Compiler_IO_STDIN
+  int ch;
+#elif (!defined(RTE_Compiler_IO_File))
+  (void)buf;
+  (void)len;
+#endif
+  (void)mode;
+ 
+  switch (fh) {
+    case FH_STDIN:
+#ifdef RTE_Compiler_IO_STDIN
+      ch = stdin_getchar();
+      if (ch < 0) {
+        return ((int)(len | 0x80000000U));
+      }
+      *buf++ = (uint8_t)ch;
+#if (STDIN_ECHO != 0)
+      stdout_putchar(ch);
+#endif
+      len--;
+      return ((int)(len));
+#else
+      return ((int)(len | 0x80000000U));
+#endif
+    case FH_STDOUT:
+      return (-1);
+    case FH_STDERR:
+      return (-1);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_read(fh, buf, len));
+#endif
+#else
+  return (-1);
+#endif
+}
+#endif
+ 
+ 
+
+ 
+ 
+/**
+  Defined in rt_sys.h, this function determines if a file handle identifies
+  a terminal.
+ 
+  When a file is connected to a terminal device, this function is used to
+  provide unbuffered behavior by default (in the absence of a call to
+  set(v)buf) and to prohibit seeking.
+ 
+  \param[in] fh File handle
+ 
+  \return    The return value is one of the following values:
+             - 0:     There is no interactive device.
+             - 1:     There is an interactive device.
+             - other: An error occurred.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_istty (FILEHANDLE fh) {
+ 
+  switch (fh) {
+    case FH_STDIN:
+      return (1);
+    case FH_STDOUT:
+      return (1);
+    case FH_STDERR:
+      return (1);
+  }
+ 
+  return (0);
+}
+#endif
+ 
+ 
+/**
+  Defined in rt_sys.h, this function puts the file pointer at offset pos from
+  the beginning of the file.
+ 
+  This function sets the current read or write position to the new location pos
+  relative to the start of the current file fh.
+ 
+  \param[in] fh  File handle
+  \param[in] pos File pointer offset
+ 
+  \return    The result is:
+             - non-negative if no error occurs
+             - negative if an error occurs
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+int _sys_seek (FILEHANDLE fh, long pos) {
+#if (!defined(RTE_Compiler_IO_File))
+  (void)pos;
+#endif
+ 
+  switch (fh) {
+    case FH_STDIN:
+      return (-1);
+    case FH_STDOUT:
+      return (-1);
+    case FH_STDERR:
+      return (-1);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_seek(fh, (uint32_t)pos));
+#endif
+#else
+  return (-1);
+#endif
+}
+#endif
+ 
+ 
+/**
+  Defined in rt_sys.h, this function returns the current length of a file.
+ 
+  This function is used by _sys_seek() to convert an offset relative to the
+  end of a file into an offset relative to the beginning of the file.
+  You do not have to define _sys_flen() if you do not intend to use fseek().
+  If you retarget at system _sys_*() level, you must supply _sys_flen(),
+  even if the underlying system directly supports seeking relative to the
+  end of a file.
+ 
+  \param[in] fh File handle
+ 
+  \return    This function returns the current length of the file fh,
+             or a negative error indicator.
+*/
+#ifdef RETARGET_SYS
+__attribute__((weak))
+long _sys_flen (FILEHANDLE fh) {
+ 
+  switch (fh) {
+    case FH_STDIN:
+      return (0);
+    case FH_STDOUT:
+      return (0);
+    case FH_STDERR:
+      return (0);
+  }
+ 
+#ifdef RTE_Compiler_IO_File
+#ifdef RTE_Compiler_IO_File_FS
+  return (__sys_flen(fh));
+#endif
+#else
+  return (0);
+#endif
+}
+#endif
+ 
+
+
+#define log_str(...)                                \
+    do {                                                \
+        const char *pchSrc = __VA_ARGS__;               \
+        uint_fast16_t hwSize = sizeof(__VA_ARGS__);     \
+        do {                                            \
+            stdout_putchar(*pchSrc++);                  \
+        } while(--hwSize);                              \
+    } while(0)
+
+void _sys_exit(int n)
+{
+    (void)n;
+  log_str("\n");
+  log_str("_[TEST COMPLETE]_________________________________________________\n");
+  log_str("\n\n");
+  stdout_putchar(4);
+  while(1);
+}
+
+extern void ttywrch (int ch);
+__attribute__((weak))
+void _ttywrch (int ch) 
+{
+    ttywrch(ch);
+}
+
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt
index 0821b1d..fe4a4de 100644
--- a/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt
+++ b/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt
@@ -19,7 +19,7 @@
 add_library(CMSISDSPBasicMath STATIC ${SRCF64})
 target_sources(CMSISDSPBasicMath PRIVATE ${SRCF32})
 
-if (NOT ARMAC5)
+if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16))
 target_sources(CMSISDSPBasicMath PRIVATE ${SRCF16})
 endif()
 
diff --git a/CMSIS/DSP/Source/CMakeLists.txt b/CMSIS/DSP/Source/CMakeLists.txt
index aa1b21d..895e6ec 100755
--- a/CMSIS/DSP/Source/CMakeLists.txt
+++ b/CMSIS/DSP/Source/CMakeLists.txt
@@ -21,6 +21,7 @@
 option(MVEF "MVEF intrinsics supported" OFF)
 option(MVEI "MVEI intrinsics supported" OFF)
 option(MVEFLOAT16 "Float16 MVE intrinsics supported" OFF)
+option(DISABLEFLOAT16 "Disable building float16 kernels" OFF)
 
 # Select which parts of the CMSIS-DSP must be compiled.
 # There are some dependencies between the parts but they are not tracked
diff --git a/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt
index b5a95e1..2411563 100644
--- a/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt
+++ b/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt
@@ -28,7 +28,7 @@
 target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f32.c)
 endif()
 
-if (NOT ARMAC5)
+if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16))
 if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F16_16 OR CFFT_F16_32 OR CFFT_F16_64 OR CFFT_F16_128 OR CFFT_F16_256 OR CFFT_F16_512 
     OR CFFT_F16_1024 OR CFFT_F16_2048 OR CFFT_F16_4096)
 target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f16.c)
diff --git a/CMSIS/DSP/Source/configDsp.cmake b/CMSIS/DSP/Source/configDsp.cmake
index 12ea633..e5b0195 100644
--- a/CMSIS/DSP/Source/configDsp.cmake
+++ b/CMSIS/DSP/Source/configDsp.cmake
@@ -34,4 +34,9 @@
    target_include_directories(${project} PRIVATE "${root}/CMSIS/DSP/PrivateInclude")
 endif()
 
+if (DISABLEFLOAT16)
+    target_compile_definitions(${project} PRIVATE DISABLEFLOAT16) 
+endif()
+
+
 endfunction()
diff --git a/CMSIS/DSP/Testing/CMakeLists.txt b/CMSIS/DSP/Testing/CMakeLists.txt
index 67056d4..63304bb 100644
--- a/CMSIS/DSP/Testing/CMakeLists.txt
+++ b/CMSIS/DSP/Testing/CMakeLists.txt
@@ -318,6 +318,10 @@
 target_sources(FrameworkLib PRIVATE ${FRAMEWORKSRC})
 target_sources(FrameworkLib PRIVATE ${FRAMEWORKMODESRC})
 
+if (DISABLEFLOAT16)
+    target_compile_definitions(FrameworkLib PRIVATE DISABLEFLOAT16) 
+endif()
+
 if (BENCHMARK)
     target_compile_definitions(FrameworkLib PUBLIC BENCHMARK)
 endif()
diff --git a/CMSIS/DSP/Testing/Source/Benchmarks/BasicMathsBenchmarksF32.cpp b/CMSIS/DSP/Testing/Source/Benchmarks/BasicMathsBenchmarksF32.cpp
index d56ae11..505c582 100644
--- a/CMSIS/DSP/Testing/Source/Benchmarks/BasicMathsBenchmarksF32.cpp
+++ b/CMSIS/DSP/Testing/Source/Benchmarks/BasicMathsBenchmarksF32.cpp
@@ -49,7 +49,7 @@
     void BasicMathsBenchmarksF32::setUp(Testing::testID_t id,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr)
     {
 
-
+       this->setForceInCache(true);
        std::vector<Testing::param_t>::iterator it = params.begin();
        this->nb = *it;
 
diff --git a/CMSIS/DSP/Toolchain/AC6.cmake b/CMSIS/DSP/Toolchain/AC6.cmake
index f232acd..9733a38 100644
--- a/CMSIS/DSP/Toolchain/AC6.cmake
+++ b/CMSIS/DSP/Toolchain/AC6.cmake
@@ -62,6 +62,7 @@
           target_compile_options(${PROJECTNAME} PUBLIC "-mfpu=vfpv4-d16")
       endif()
   endif()
+
   
   if (ARM_CPU STREQUAL "cortex-a5" )
       if ((NEON OR NEONEXPERIMENTAL))
@@ -71,6 +72,7 @@
       endif()
   endif()
 
+
   if(EXPERIMENTAL)
     experimentalCompilerSpecificCompileOptions(${PROJECTNAME} ${ROOT})
   endif()
diff --git a/CMSIS/DSP/armac6.cmake b/CMSIS/DSP/armac6.cmake
index f24c7a4..75535c4 100755
--- a/CMSIS/DSP/armac6.cmake
+++ b/CMSIS/DSP/armac6.cmake
@@ -50,9 +50,15 @@
     )
 endif(NOT ARM_CPU)
 
+if (AARCH64)
+SET(CMAKE_C_FLAGS "-mcpu=${ARM_CPU} --target=aarch64-arm-none-eabi" CACHE INTERNAL "C compiler common flags")
+SET(CMAKE_CXX_FLAGS "-mcpu=${ARM_CPU} --target=aarch64-arm-none-eabi" CACHE INTERNAL "C compiler common flags")
+SET(CMAKE_ASM_FLAGS "-g -x assembler-with-cpp -masm=auto -mcpu=${ARM_CPU} --target=aarch64-arm-none-eabi" CACHE INTERNAL "ASM compiler common flags")
+else()
 SET(CMAKE_C_FLAGS "-mcpu=${ARM_CPU} --target=arm-arm-none-eabi" CACHE INTERNAL "C compiler common flags")
 SET(CMAKE_CXX_FLAGS "-mcpu=${ARM_CPU} --target=arm-arm-none-eabi" CACHE INTERNAL "C compiler common flags")
 SET(CMAKE_ASM_FLAGS "-g -x assembler-with-cpp -masm=auto -mcpu=${ARM_CPU} --target=arm-arm-none-eabi" CACHE INTERNAL "ASM compiler common flags")
+endif()
 #SET(CMAKE_ASM_FLAGS "--cpu=${ARM_CPU}" CACHE INTERNAL "ASM compiler common flags")
 #SET(CMAKE_EXE_LINKER_FLAGS "-flto" CACHE INTERNAL "linker flags")
 
diff --git a/CMSIS/DSP/configBoot.cmake b/CMSIS/DSP/configBoot.cmake
index 80486dd..578afa9 100755
--- a/CMSIS/DSP/configBoot.cmake
+++ b/CMSIS/DSP/configBoot.cmake
@@ -68,7 +68,7 @@
   
   ###################
   #
-  # Cortex cortex-a5
+  # Cortex cortex-a
   #
   if (ARM_CPU MATCHES "^[cC]ortex-[Aa].*")
     cortexa(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
diff --git a/CMSIS/DSP/configCore.cmake b/CMSIS/DSP/configCore.cmake
index 0a94d40..18ccbe0 100644
--- a/CMSIS/DSP/configCore.cmake
+++ b/CMSIS/DSP/configCore.cmake
@@ -30,6 +30,18 @@
   # CORTEX-A
   #
 
+  # CORTEX-A32
+  if (ARM_CPU  MATCHES  "^[cC]ortex-[aA]32([^0-9].*)?$" )
+    target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include")
+    SET(CORTEXM OFF)
+    target_compile_definitions(${PROJECTNAME} PRIVATE ARMv8A) 
+  
+    target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA)
+    SET(HARDFP ON)
+    SET(LITTLEENDIAN ON)
+    SET(COREID ARMCA32 PARENT_SCOPE)
+  endif()
+
   # CORTEX-A15
   if (ARM_CPU  MATCHES  "^[cC]ortex-[aA]15([^0-9].*)?$" )
     target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include")
diff --git a/CMSIS/DSP/configPlatform.cmake b/CMSIS/DSP/configPlatform.cmake
index 770c40f..0b3036f 100644
--- a/CMSIS/DSP/configPlatform.cmake
+++ b/CMSIS/DSP/configPlatform.cmake
@@ -104,6 +104,15 @@
       SET(CORE ARMCM0 PARENT_SCOPE)
       
   endif()
+
+  ###################
+  #
+  # Cortex cortex-a32
+  #
+  if (ARM_CPU MATCHES "^[cC]ortex-[aA]32([^0-9].*)?$")
+    SET(CORE ARMCA32 PARENT_SCOPE)
+    
+  endif()
   
   ###################
   #