diff --git a/CMSIS/DoxyGen/Core/src/core_cm7.txt b/CMSIS/DoxyGen/Core/src/core_cm7.txt
index 7ec67bb..0d22ecd 100644
--- a/CMSIS/DoxyGen/Core/src/core_cm7.txt
+++ b/CMSIS/DoxyGen/Core/src/core_cm7.txt
@@ -1,9 +1,10 @@
 /**
-\defgroup cache_functions_m7 Cache Functions  (only Cortex-M7)
-\brief Functions for Instruction and Data Cache.
+\defgroup cache_functions_m7 Cache Functions (Level-1)
+\brief Functions for level-1 instruction and data cache.
 \details 
-Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction
-cache with ECC.  The optional CPU cache has an instruction and data cache with sizes of \token{[0;4;8;16;32;64]KB}.
+Enhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional
+Harvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction
+and data cache with sizes of \token{[0;4;8;16;32;64]KB}.
 Both instruction and data cache RAM can be configured at implementation time to have Error
 Correcting Code (ECC) to protect the data stored in the memory from errors.
 
@@ -22,7 +23,7 @@
 
 /**
   \defgroup Icache_functions_m7 I-Cache Functions
-  \brief Functions for the instruction cache.
+  \brief Functions for the level-1 instruction cache.
   @{
 */
  
@@ -38,7 +39,7 @@
 \note 
 After reset, you must invalidate (\ref SCB_InvalidateICache) each cache before enabling it. 
 */
-__STATIC_INLINE void SCB_EnableICache (void);
+__STATIC_FORCEINLINE void SCB_EnableICache (void);
 
 
 /**
@@ -47,7 +48,7 @@
   The function turns off the instruction cache.
 
 */
-__STATIC_INLINE void SCB_DisableICache (void);
+__STATIC_FORCEINLINE void SCB_DisableICache (void);
 
 
 /**
@@ -59,16 +60,26 @@
 After reset, you must invalidate each cache before enabling (\ref SCB_EnableICache) it. 
 
 */
-__STATIC_INLINE void SCB_InvalidateICache (void);
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void);
 
 
 /**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+
+/**
   @}  // close ICache functions
 */
  
 /**
-  \defgroup Dcache_functions_m7 D-Cache Functions  
-  \brief Functions for the data cache.
+  \defgroup Dcache_functions_m7 D-Cache Functions (Level-1)
+  \brief Functions for the level-1 data cache.
 
   @{
 */
@@ -84,7 +95,7 @@
 \note 
 After reset, you must invalidate (\ref SCB_InvalidateDCache) each cache before enabling it. 
 */
-__STATIC_INLINE void SCB_EnableDCache (void);
+__STATIC_FORCEINLINE void SCB_EnableDCache (void);
 
 
 /** 
@@ -97,7 +108,7 @@
 flushed to external memory.
 
 */
-__STATIC_INLINE void SCB_DisableDCache (void);
+__STATIC_FORCEINLINE void SCB_DisableDCache (void);
 
 
 /**
@@ -109,7 +120,7 @@
 After reset, you must invalidate each cache before enabling (\ref SCB_EnableDCache) it. 
 
 */
-__STATIC_INLINE void SCB_InvalidateDCache (void);
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void);
 
 
 /** 
@@ -117,7 +128,7 @@
 
   The function cleans the entire data cache.
 */
-__STATIC_INLINE void SCB_CleanDCache (void);
+__STATIC_FORCEINLINE void SCB_CleanDCache (void);
 
 
 /** 
@@ -125,7 +136,7 @@
  
   The function cleans and invalidates the entire data cache.
 */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void);
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void);
 
 
 /**
@@ -135,7 +146,7 @@
   
   The function invalidates a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundry.
 */
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);
 
 
 /**
@@ -147,7 +158,7 @@
 
 
 */
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize);
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize);
 
 
 /**
@@ -157,7 +168,7 @@
   
   The function invalidates and cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundry.
 */
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);
 
 /**
 @}  // close D-Cache Functions
diff --git a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Event.txt b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Event.txt
index 26753c0..ad1f9e4 100644
--- a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Event.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Event.txt
@@ -157,15 +157,18 @@
 \fn uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags)
 \details
 The function \b osEventFlagsSet sets the event flags specified by the parameter \a flags in an event flags object specified
-by parameter \a ef_id. All threads waiting for the flag set will be notified to resume from \ref ThreadStates "BLOCKED" state.
+by parameter \a ef_id. 
+
+The threads with highest priority waiting for the flag(s) set will be notified to resume from \ref ThreadStates "BLOCKED" state.
 The function returns the event flags stored in the event control block or an error code (highest bit is set, refer to
-\ref flags_error_codes).
+\ref flags_error_codes). Further threads may be wakened in priority order when the option \b osFlagsNoClear is given to the
+\ref osEventFlagsWait call.
 
 Possible \ref flags_error_codes return values:
     - \em osFlagsErrorUnknown: unspecified error.
     - \em osFlagsErrorParameter: parameter \a ef_id does not identify a valid event flags object or \em flags has highest bit set. 
     - \em osFlagsErrorResource: the event flags object is in an invalid state.
-
+    
 \note This function may be called from \ref CMSIS_RTOS_ISR_Calls "Interrupt Service Routines".
 
 <b>Code Example</b>
diff --git a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ThreadFlags.txt b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ThreadFlags.txt
index 7ef9d44..a1cbb1e 100644
--- a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ThreadFlags.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ThreadFlags.txt
@@ -67,8 +67,7 @@
 the flags stored in the thread control block, or an error code if highest bit is set (refer to \ref flags_error_codes).
 Refer to \b Usage \b Examples below to understand how the return value is computed.
 
-This function maybe used also within interrupt service routines. Threads waiting for a flag to be set will resume from
-\ref ThreadStates "BLOCKED" state.
+The target thread waiting for a flag to be set will resume from \ref ThreadStates "BLOCKED" state.
 
 Possible \ref flags_error_codes return values:
     - \em osFlagsErrorUnknown: unspecified error.