commit b9671a2b43e991182b45d92e393b75d2e8c88978
author Edmund Player <Edmund.Player@arm.com> Thu Mar 26 14:48:23 2020 +0000
committer Jonatan Antoni <jonatan.antoni@arm.com> Thu Mar 26 16:04:03 2020 +0100
tree eca791f65029875a1b7397a154b0962fda4d6d5f
parent 036eae5490d49490c1574c96d5003e4ce64ae8fe

Updating PMU Event Counter Number from 12 to 8 to align with Cortex-M55's default number when the PMU is configured.

Device/ARM/ARMCM55/Include/ARMCM55.h

diff --git a/Device/ARM/ARMCM55/Include/ARMCM55.h b/Device/ARM/ARMCM55/Include/ARMCM55.h
index c2e7eed..0e848d4 100644
--- a/Device/ARM/ARMCM55/Include/ARMCM55.h
+++ b/Device/ARM/ARMCM55/Include/ARMCM55.h
@@ -4,7 +4,7 @@
  *           ARMCM55 Device Series (configured for ARMCM55 with double precision FPU,
  *                                  DSP extension, MVE, TrustZone)
  * @version  V1.0.0
- * @date     03. March 2020
+ * @date     26. March 2020
  ******************************************************************************/
 /*
  * Copyright (c) 2020 Arm Limited. All rights reserved.
@@ -101,7 +101,7 @@
 #define __DSP_PRESENT             1U        /* DSP extension present */
 #define __SAUREGION_PRESENT       1U        /* SAU regions present */
 #define __PMU_PRESENT             1U        /* PMU present */
-#define __PMU_NUM_EVENTCNT       12U        /* PMU Event Counters */
+#define __PMU_NUM_EVENTCNT        8U        /* PMU Event Counters */
 #define __ICACHE_PRESENT          1U
 #define __DCACHE_PRESENT          1U