CMSIS-DAP: Remove v1 firmware for NXP LPC-Link2
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvguix b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvguix
deleted file mode 100644
index ba27619..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvguix
+++ /dev/null
@@ -1,1878 +0,0 @@
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diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvoptx b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvoptx
deleted file mode 100644
index 70399ba..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvoptx
+++ /dev/null
@@ -1,331 +0,0 @@
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diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvprojx b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvprojx
deleted file mode 100644
index 741ff07..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvprojx
+++ /dev/null
@@ -1,664 +0,0 @@
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- </Group>
- <Group>
- <GroupName>::Device</GroupName>
- </Group>
- <Group>
- <GroupName>::USB</GroupName>
- </Group>
- </Groups>
- </Target>
- </Targets>
-
- <RTE>
- <apis>
- <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </api>
- <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </api>
- <api Capiversion="2.1.2" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </api>
- </apis>
- <components>
- <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5">
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="CORE" Cvariant="Release" Cvendor="Keil" Cversion="6.14.4" condition="USB Core">
- <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.14.4" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
- <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.14.4" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
- <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Capiversion="2.1" Cclass="CMSIS Driver" Cgroup="USART" Cvendor="Keil" Cversion="2.14" condition="LPC4300 CMSIS SCU GPDMA">
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Capiversion="2.1" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB0" Cvendor="Keil" Cversion="2.12" condition="LPC4300 CMSIS SCU">
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cclass="Device" Cgroup="GPDMA" Cvendor="Keil" Cversion="1.6" condition="LPC4300 CMSIS">
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.1" condition="LPC4300 CMSIS">
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </component>
- <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS">
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2">
- <c>
- <Define>USE_SPIFI=1</Define>
- </c>
- <asm>
- <Define>NO_CRP</Define>
- </asm>
- </targetInfo>
- </targetInfos>
- </component>
- </components>
- <files>
- <file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
- <instance index="0">RTE\CMSIS\RTX_Config.c</instance>
- <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.1">
- <instance index="0">RTE\CMSIS\RTX_Config.h</instance>
- <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5"/>
- <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="2.2.1">
- <instance index="0">RTE\Device\LPC4370_Cortex-M4\RTE_Device.h</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="source" condition="CM4 ARM Compiler" name="Device\Source\ARM\startup_LPC43xx.s" version="1.0.0">
- <instance index="0">RTE\Device\LPC4370_Cortex-M4\startup_LPC43xx.s</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="source" condition="CM4" name="Device\Source\system_LPC43xx.c" version="1.0.3">
- <instance index="0">RTE\Device\LPC4370_Cortex-M4\system_LPC43xx.c</instance>
- <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
- <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.2.0">
- <instance index="0">RTE\USB\USBD_Config_0.c</instance>
- <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
- <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- <file attr="config" category="header" name="USB\Config\USBD_Config_HID.h" version="5.0.2">
- <instance index="0">RTE\USB\USBD_Config_HID_0.h</instance>
- <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
- <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
- <targetInfos>
- <targetInfo name="LPC-Link2"/>
- </targetInfos>
- </file>
- </files>
- </RTE>
-
- <LayerInfo>
- <Layers>
- <Layer>
- <LayName>CMSIS_DAP</LayName>
- <LayPrjMark>1</LayPrjMark>
- </Layer>
- </Layers>
- </LayerInfo>
-
-</Project>
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DAP_config.h b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DAP_config.h
deleted file mode 100644
index 7f8a959..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DAP_config.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 16. June 2021
- * $Revision: V2.1.0
- *
- * Project: CMSIS-DAP Examples LPC-Link2
- * Title: DAP_config.h CMSIS-DAP Configuration File for LPC-Link2
- *
- *---------------------------------------------------------------------------*/
-
-#ifndef __DAP_CONFIG_H__
-#define __DAP_CONFIG_H__
-
-
-//**************************************************************************************************
-/**
-\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
-\ingroup DAP_ConfigIO_gr
-@{
-Provides definitions about the hardware and configuration of the Debug Unit.
-
-This information includes:
- - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- - Debug Unit Identification strings (Vendor, Product, Serial Number).
- - Debug Unit communication packet size.
- - Debug Access Port supported modes and settings (JTAG/SWD and SWO).
- - Optional information about a connected Target Device (for Evaluation Boards).
-*/
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#include CMSIS_device_header
-#else
-#include "device.h" // Debug Unit Cortex-M Processor Header File
-#endif
-
-/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
-/// This value is used to calculate the SWD/JTAG clock speed.
-#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz.
-
-/// Number of processor cycles for I/O Port write operations.
-/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
-/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
-/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
-/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
-/// required.
-#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
-
-/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
-
-/// Indicate that JTAG communication mode is available at the Debug Port.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
-
-/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
-/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
-#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
-
-/// Default communication mode on the Debug Access Port.
-/// Used for the command \ref DAP_Connect when Port Default mode is selected.
-#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
-
-/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
-/// Used to initialize the default SWD/JTAG clock frequency.
-/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
-#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
-
-/// Maximum Package Size for Command and Response data.
-/// This configuration settings is used to optimize the communication performance with the
-/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
-/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
-#define DAP_PACKET_SIZE 1024U ///< Specifies Packet Size in bytes.
-
-/// Maximum Package Buffers for Command and Response data.
-/// This configuration settings is used to optimize the communication performance with the
-/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
-/// setting can be reduced (valid range is 1 .. 255).
-#define DAP_PACKET_COUNT 4U ///< Specifies number of packets buffered.
-
-/// Indicate that UART Serial Wire Output (SWO) trace is available.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
-
-/// USART Driver instance number for the UART SWO.
-#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
-
-/// Maximum SWO UART Baudrate.
-#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
-
-/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
-
-/// SWO Trace Buffer Size.
-#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n).
-
-/// SWO Streaming Trace.
-#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
-
-/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
-#define TIMESTAMP_CLOCK 180000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
-
-/// Indicate that UART Communication Port is available.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available.
-
-/// USART Driver instance number for the UART Communication Port.
-#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
-
-/// UART Receive Buffer Size.
-#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
-
-/// UART Transmit Buffer Size.
-#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
-
-/// Indicate that UART Communication via USB COM Port is available.
-/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART_USB_COM_PORT 0 ///< USB COM Port: 1 = available, 0 = not available.
-
-/// Debug Unit is connected to fixed Target Device.
-/// The Debug Unit may be part of an evaluation board and always connected to a fixed
-/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
-/// are stored and may be used by the debugger or IDE to configure device parameters.
-#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
-
-#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor
-#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
-#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor
-#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name
-
-#if TARGET_FIXED != 0
-#include <string.h>
-static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
-static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
-static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR;
-static const char TargetBoardName [] = TARGET_BOARD_NAME;
-#endif
-
-/** Get Vendor Name string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
- (void)str;
- return (0U);
-}
-
-/** Get Product Name string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
- (void)str;
- return (0U);
-}
-
-/** Get Serial Number string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
- (void)str;
- return (0U);
-}
-
-/** Get Target Device Vendor string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
-#if TARGET_FIXED != 0
- uint8_t len;
-
- strcpy(str, TargetDeviceVendor);
- len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
- return (len);
-#else
- (void)str;
- return (0U);
-#endif
-}
-
-/** Get Target Device Name string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
-#if TARGET_FIXED != 0
- uint8_t len;
-
- strcpy(str, TargetDeviceName);
- len = (uint8_t)(strlen(TargetDeviceName) + 1U);
- return (len);
-#else
- (void)str;
- return (0U);
-#endif
-}
-
-/** Get Target Board Vendor string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
-#if TARGET_FIXED != 0
- uint8_t len;
-
- strcpy(str, TargetBoardVendor);
- len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
- return (len);
-#else
- (void)str;
- return (0U);
-#endif
-}
-
-/** Get Target Board Name string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
-#if TARGET_FIXED != 0
- uint8_t len;
-
- strcpy(str, TargetBoardName);
- len = (uint8_t)(strlen(TargetBoardName) + 1U);
- return (len);
-#else
- (void)str;
- return (0U);
-#endif
-}
-
-/** Get Product Firmware Version string.
-\param str Pointer to buffer to store the string (max 60 characters).
-\return String length (including terminating NULL character) or 0 (no string).
-*/
-__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
- (void)str;
- return (0U);
-}
-
-///@}
-
-
-// LPC43xx peripheral register bit masks (used by macros)
-#define CCU_CLK_CFG_RUN (1U << 0)
-#define CCU_CLK_CFG_AUTO (1U << 1)
-#define CCU_CLK_STAT_RUN (1U << 0)
-#define SCU_SFS_EPD (1U << 3)
-#define SCU_SFS_EPUN (1U << 4)
-#define SCU_SFS_EHS (1U << 5)
-#define SCU_SFS_EZI (1U << 6)
-#define SCU_SFS_ZIF (1U << 7)
-
-
-// Debug Port I/O Pins
-
-// SWCLK/TCK Pin P1_17: GPIO0[12]
-#define PIN_SWCLK_TCK_PORT 0
-#define PIN_SWCLK_TCK_BIT 12
-
-// SWDIO/TMS Pin P1_6: GPIO1[9]
-#define PIN_SWDIO_TMS_PORT 1
-#define PIN_SWDIO_TMS_BIT 9
-
-// SWDIO Output Enable Pin P1_5: GPIO1[8]
-#define PIN_SWDIO_OE_PORT 1
-#define PIN_SWDIO_OE_BIT 8
-
-// TDI Pin P1_18: GPIO0[13]
-#define PIN_TDI_PORT 0
-#define PIN_TDI_BIT 13
-
-// TDO Pin P1_14: GPIO1[7]
-#define PIN_TDO_PORT 1
-#define PIN_TDO_BIT 7
-
-// nTRST Pin Not available
-#define PIN_nTRST_PORT
-#define PIN_nTRST_BIT
-
-// nRESET Pin P2_5: GPIO5[5]
-#define PIN_nRESET_PORT 5
-#define PIN_nRESET_BIT 5
-
-// nRESET Output Enable Pin P2_6: GPIO5[6]
-#define PIN_nRESET_OE_PORT 5
-#define PIN_nRESET_OE_BIT 6
-
-
-// Debug Unit LEDs
-
-// Connected LED P1_1: GPIO0[8]
-#define LED_CONNECTED_PORT 0
-#define LED_CONNECTED_BIT 8
-
-// Target Running LED Not available
-
-
-//**************************************************************************************************
-/**
-\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
-\ingroup DAP_ConfigIO_gr
-@{
-
-Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
-and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
-interface of a device. The following I/O Pins are provided:
-
-JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
----------------------------- | -------------------- | ---------------------------------------------
-TCK: Test Clock | SWCLK: Clock | Output Push/Pull
-TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
-TDI: Test Data Input | | Output Push/Pull
-TDO: Test Data Output | | Input
-nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
-nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
-
-
-DAP Hardware I/O Pin Access Functions
--------------------------------------
-The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
-these I/O Pins.
-
-For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
-This functions are provided to achieve faster I/O that is possible with some advanced GPIO
-peripherals that can independently write/read a single I/O pin without affecting any other pins
-of the same I/O port. The following SWDIO I/O Pin functions are provided:
- - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
- - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
- - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
- - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
-*/
-
-
-// Configure DAP I/O pins ------------------------------
-
-// LPC-Link2 HW uses buffers for debug port pins. Therefore it is not
-// possible to disable outputs SWCLK/TCK, TDI and they are left active.
-// Only SWDIO/TMS output can be disabled but it is also left active.
-// nRESET is configured for open drain mode.
-
-/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
-Configures the DAP Hardware I/O pins for JTAG mode:
- - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
- - TDO to input mode.
-*/
-__STATIC_INLINE void PORT_JTAG_SETUP (void) {
- LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
- LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
-}
-
-/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
-Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
- - SWCLK, SWDIO, nRESET to output mode and set to default high level.
- - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
-*/
-__STATIC_INLINE void PORT_SWD_SETUP (void) {
- LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
- LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
-}
-
-/** Disable JTAG/SWD I/O Pins.
-Disables the DAP Hardware I/O pins which configures:
- - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
-*/
-__STATIC_INLINE void PORT_OFF (void) {
- LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
- LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
- LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
- LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
- LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
- LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
-}
-
-
-// SWCLK/TCK I/O pin -------------------------------------
-
-/** SWCLK/TCK I/O pin: Get Input.
-\return Current status of the SWCLK/TCK DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
- return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
-}
-
-/** SWCLK/TCK I/O pin: Set Output to High.
-Set the SWCLK/TCK DAP hardware I/O pin to high level.
-*/
-__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
- LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
-}
-
-/** SWCLK/TCK I/O pin: Set Output to Low.
-Set the SWCLK/TCK DAP hardware I/O pin to low level.
-*/
-__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
- LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
-}
-
-
-// SWDIO/TMS Pin I/O --------------------------------------
-
-/** SWDIO/TMS I/O pin: Get Input.
-\return Current status of the SWDIO/TMS DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
- return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
-}
-
-/** SWDIO/TMS I/O pin: Set Output to High.
-Set the SWDIO/TMS DAP hardware I/O pin to high level.
-*/
-__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
- LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
-}
-
-/** SWDIO/TMS I/O pin: Set Output to Low.
-Set the SWDIO/TMS DAP hardware I/O pin to low level.
-*/
-__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
- LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
-}
-
-/** SWDIO I/O pin: Get Input (used in SWD mode only).
-\return Current status of the SWDIO DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
- return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
-}
-
-/** SWDIO I/O pin: Set Output (used in SWD mode only).
-\param bit Output value for the SWDIO DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
- LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
-}
-
-/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
-Configure the SWDIO DAP hardware I/O pin to output mode. This function is
-called prior \ref PIN_SWDIO_OUT function calls.
-*/
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
- LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
-}
-
-/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
-Configure the SWDIO DAP hardware I/O pin to input mode. This function is
-called prior \ref PIN_SWDIO_IN function calls.
-*/
-__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
- LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
-}
-
-
-// TDI Pin I/O ---------------------------------------------
-
-/** TDI I/O pin: Get Input.
-\return Current status of the TDI DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
- return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
-}
-
-/** TDI I/O pin: Set Output.
-\param bit Output value for the TDI DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
- LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
-}
-
-
-// TDO Pin I/O ---------------------------------------------
-
-/** TDO I/O pin: Get Input.
-\return Current status of the TDO DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
- return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
-}
-
-
-// nTRST Pin I/O -------------------------------------------
-
-/** nTRST I/O pin: Get Input.
-\return Current status of the nTRST DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
- return (0U); // Not available
-}
-
-/** nTRST I/O pin: Set Output.
-\param bit JTAG TRST Test Reset pin status:
- - 0: issue a JTAG TRST Test Reset.
- - 1: release JTAG TRST Test Reset.
-*/
-__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
- (void) bit;
- // Not available
-}
-
-// nRESET Pin I/O------------------------------------------
-
-/** nRESET I/O pin: Get Input.
-\return Current status of the nRESET DAP hardware I/O pin.
-*/
-__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
- return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
-}
-
-/** nRESET I/O pin: Set Output.
-\param bit target device hardware reset pin status:
- - 0: issue a device hardware reset.
- - 1: release device hardware reset.
-*/
-__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
- if (bit) {
- LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
- LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
- } else {
- LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
- LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT);
- }
-}
-
-///@}
-
-
-//**************************************************************************************************
-/**
-\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
-\ingroup DAP_ConfigIO_gr
-@{
-
-CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
-
-It is recommended to provide the following LEDs for status indication:
- - Connect LED: is active when the DAP hardware is connected to a debugger.
- - Running LED: is active when the debugger has put the target device into running state.
-*/
-
-/** Debug Unit: Set status of Connected LED.
-\param bit status of the Connect LED.
- - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
- - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
-*/
-__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
- LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = (uint8_t)bit;
-}
-
-/** Debug Unit: Set status Target Running LED.
-\param bit status of the Target Running LED.
- - 1: Target Running LED ON: program execution in target started.
- - 0: Target Running LED OFF: program execution in target stopped.
-*/
-__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
- (void) bit;
- // Not available
-}
-
-///@}
-
-
-//**************************************************************************************************
-/**
-\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
-\ingroup DAP_ConfigIO_gr
-@{
-Access function for Test Domain Timer.
-
-The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
-default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
-
-*/
-
-/** Get timestamp of Test Domain Timer.
-\return Current timestamp value.
-*/
-__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
- return (DWT->CYCCNT);
-}
-
-///@}
-
-
-//**************************************************************************************************
-/**
-\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
-\ingroup DAP_ConfigIO_gr
-@{
-
-CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
-*/
-
-/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
-This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
-Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
- - I/O clock system enabled.
- - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
- - for nTRST, nRESET a weak pull-up (if available) is enabled.
- - LED output pins are enabled and LEDs are turned off.
-*/
-__STATIC_INLINE void DAP_SETUP (void) {
-
- /* Enable clock and init GPIO outputs */
- LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
- while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
-
- /* Configure I/O pins: function number, input buffer enabled, */
- /* no pull-up/down except nRESET (pull-up) */
- LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */
- LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */
- LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */
- LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */
- LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */
- LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */
- LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */
- LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */
-#ifdef TARGET_POWER_EN
- LPC_SCU->SFSP3_1 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* Target Power enable P3_1 GPIO5[8] */
-#endif
-
- /* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */
- /* TDO as input */
- /* nRESET as input with output latch set to low level */
- /* nRESET_OE as output (low level) */
- LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
- LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
- LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
- LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
- LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT);
- LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
- LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT);
- LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT);
- LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT);
- LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT);
- LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT);
- LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
- LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT);
-
-#ifdef TARGET_POWER_EN
- /* Target Power enable as output (turned on) */
- LPC_GPIO_PORT->SET[5] = (1U << 8);
- LPC_GPIO_PORT->DIR[5] |= (1U << 8);
-#endif
-
- /* Configure: LED as output (turned off) */
- LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT);
- LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT);
-
- /* Configure Peripheral Interrupt Priorities */
- NVIC_SetPriority(USB0_IRQn, 1U);
-}
-
-/** Reset Target Device with custom specific I/O pin or command sequence.
-This function allows the optional implementation of a device specific reset sequence.
-It is called when the command \ref DAP_ResetTarget and is for example required
-when a device needs a time-critical unlock sequence that enables the debug port.
-\return 0 = no device specific reset sequence is implemented.\n
- 1 = a device specific reset sequence is implemented.
-*/
-__STATIC_INLINE uint8_t RESET_TARGET (void) {
- return (0U); // change to '1' when a device reset sequence is implemented
-}
-
-///@}
-
-
-#endif /* __DAP_CONFIG_H__ */
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf
deleted file mode 100644
index fb89136..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf
+++ /dev/null
@@ -1,43 +0,0 @@
-// <<< Use Configuration Wizard in Context Menu >>>
-
-// <h> Debug Setup
-
-// <o> Release M0 On Connect
-// <0=> No
-// <1=> Yes
-// <i> Debugger releases the M0 Application processor from reset when connecting to it.
-ReleaseM0OnConnect = 1;
-
-// <o> Release M0 Sub-System On Connect
-// <0=> No
-// <1=> Yes
-// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
-ReleaseM0SubOnConnect = 1;
-
-// <o> Vector Reset
-// <0=> Processor Only
-// <1=> Processor and Peripherals
-// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
-VecResetWithPeriph = 1;
-
-// </h>
-
-// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
-// <i> Configure the TPIU pin routing as used on your target platform.
-// <o.1> TRACEDATA0
-// <0=> Pin PF_5
-// <1=> Pin P7_4
-// <o.2> TRACEDATA1
-// <0=> Pin PF_6
-// <1=> Pin P7_5
-// <o.3> TRACEDATA2
-// <0=> Pin PF_7
-// <1=> Pin P7_6
-// <o.4> TRACEDATA3
-// <0=> Pin PF_8
-// <1=> Pin P7_7
-RoutingTPIU = 0x00000000;
-
-// </h>
-
-// <<< end of configuration section >>>
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/Objects/CMSIS_DAP.hex b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/Objects/CMSIS_DAP.hex
deleted file mode 100644
index afb205b..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/Objects/CMSIS_DAP.hex
+++ /dev/null
@@ -1,3459 +0,0 @@
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diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/README.md b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/README.md
deleted file mode 100644
index d733940..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/README.md
+++ /dev/null
@@ -1,3 +0,0 @@
-CMSIS-DAP v1 firmware for NXP LPC-Link2 debug probe.
-
-CMSIS-DAP v1 uses USB HID for the communication with the host PC.
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.c b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.c
deleted file mode 100644
index 22151e9..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision: V5.1.0
- *
- * Project: CMSIS-RTOS RTX
- * Title: RTX Configuration
- *
- * -----------------------------------------------------------------------------
- */
-
-#include "cmsis_compiler.h"
-#include "rtx_os.h"
-
-// OS Idle Thread
-__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
- (void)argument;
-
- for (;;) {}
-}
-
-// OS Error Callback function
-__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
- (void)object_id;
-
- switch (code) {
- case osRtxErrorStackUnderflow:
- // Stack overflow detected for thread (thread_id=object_id)
- break;
- case osRtxErrorISRQueueOverflow:
- // ISR Queue overflow detected when inserting object (object_id)
- break;
- case osRtxErrorTimerQueueOverflow:
- // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
- break;
- case osRtxErrorClibSpace:
- // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
- break;
- case osRtxErrorClibMutex:
- // Standard C/C++ library mutex initialization failed
- break;
- default:
- break;
- }
- for (;;) {}
-//return 0U;
-}
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.h b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.h
deleted file mode 100644
index d4a9381..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/*
- * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision: V5.5.1
- *
- * Project: CMSIS-RTOS RTX
- * Title: RTX Configuration definitions
- *
- * -----------------------------------------------------------------------------
- */
-
-#ifndef RTX_CONFIG_H_
-#define RTX_CONFIG_H_
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#ifdef RTE_RTX_CONFIG_H
-#include RTE_RTX_CONFIG_H
-#endif
-#endif
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>System Configuration
-// =======================
-
-// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
-// <i> Defines the combined global dynamic memory size.
-// <i> Default: 32768
-#ifndef OS_DYNAMIC_MEM_SIZE
-#define OS_DYNAMIC_MEM_SIZE 4096
-#endif
-
-// <o>Kernel Tick Frequency [Hz] <1-1000000>
-// <i> Defines base time unit for delays and timeouts.
-// <i> Default: 1000 (1ms tick)
-#ifndef OS_TICK_FREQ
-#define OS_TICK_FREQ 1000
-#endif
-
-// <e>Round-Robin Thread switching
-// <i> Enables Round-Robin Thread switching.
-#ifndef OS_ROBIN_ENABLE
-#define OS_ROBIN_ENABLE 1
-#endif
-
-// <o>Round-Robin Timeout <1-1000>
-// <i> Defines how many ticks a thread will execute before a thread switch.
-// <i> Default: 5
-#ifndef OS_ROBIN_TIMEOUT
-#define OS_ROBIN_TIMEOUT 5
-#endif
-
-// </e>
-
-// <o>ISR FIFO Queue
-// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
-// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
-// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
-// <i> RTOS Functions called from ISR store requests to this buffer.
-// <i> Default: 16 entries
-#ifndef OS_ISR_FIFO_QUEUE
-#define OS_ISR_FIFO_QUEUE 16
-#endif
-
-// <q>Object Memory usage counters
-// <i> Enables object memory usage counters (requires RTX source variant).
-#ifndef OS_OBJ_MEM_USAGE
-#define OS_OBJ_MEM_USAGE 0
-#endif
-
-// </h>
-
-// <h>Thread Configuration
-// =======================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_THREAD_OBJ_MEM
-#define OS_THREAD_OBJ_MEM 0
-#endif
-
-// <o>Number of user Threads <1-1000>
-// <i> Defines maximum number of user threads that can be active at the same time.
-// <i> Applies to user threads with system provided memory for control blocks.
-#ifndef OS_THREAD_NUM
-#define OS_THREAD_NUM 1
-#endif
-
-// <o>Number of user Threads with default Stack size <0-1000>
-// <i> Defines maximum number of user threads with default stack size.
-// <i> Applies to user threads with zero stack size specified.
-#ifndef OS_THREAD_DEF_STACK_NUM
-#define OS_THREAD_DEF_STACK_NUM 0
-#endif
-
-// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
-// <i> Defines the combined stack size for user threads with user-provided stack size.
-// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
-// <i> Default: 0
-#ifndef OS_THREAD_USER_STACK_SIZE
-#define OS_THREAD_USER_STACK_SIZE 0
-#endif
-
-// </e>
-
-// <o>Default Thread Stack size [bytes] <96-1073741824:8>
-// <i> Defines stack size for threads with zero stack size specified.
-// <i> Default: 3072
-#ifndef OS_STACK_SIZE
-#define OS_STACK_SIZE 1024
-#endif
-
-// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
-// <i> Defines stack size for Idle thread.
-// <i> Default: 512
-#ifndef OS_IDLE_THREAD_STACK_SIZE
-#define OS_IDLE_THREAD_STACK_SIZE 512
-#endif
-
-// <o>Idle Thread TrustZone Module Identifier
-// <i> Defines TrustZone Thread Context Management Identifier.
-// <i> Applies only to cores with TrustZone technology.
-// <i> Default: 0 (not used)
-#ifndef OS_IDLE_THREAD_TZ_MOD_ID
-#define OS_IDLE_THREAD_TZ_MOD_ID 0
-#endif
-
-// <q>Stack overrun checking
-// <i> Enables stack overrun check at thread switch.
-// <i> Enabling this option increases slightly the execution time of a thread switch.
-#ifndef OS_STACK_CHECK
-#define OS_STACK_CHECK 1
-#endif
-
-// <q>Stack usage watermark
-// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
-// <i> Enabling this option increases significantly the execution time of thread creation.
-#ifndef OS_STACK_WATERMARK
-#define OS_STACK_WATERMARK 0
-#endif
-
-// <o>Processor mode for Thread execution
-// <0=> Unprivileged mode
-// <1=> Privileged mode
-// <i> Default: Privileged mode
-#ifndef OS_PRIVILEGE_MODE
-#define OS_PRIVILEGE_MODE 1
-#endif
-
-// </h>
-
-// <h>Timer Configuration
-// ======================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_TIMER_OBJ_MEM
-#define OS_TIMER_OBJ_MEM 0
-#endif
-
-// <o>Number of Timer objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_TIMER_NUM
-#define OS_TIMER_NUM 1
-#endif
-
-// </e>
-
-// <o>Timer Thread Priority
-// <8=> Low
-// <16=> Below Normal <24=> Normal <32=> Above Normal
-// <40=> High
-// <48=> Realtime
-// <i> Defines priority for timer thread
-// <i> Default: High
-#ifndef OS_TIMER_THREAD_PRIO
-#define OS_TIMER_THREAD_PRIO 40
-#endif
-
-// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
-// <i> Defines stack size for Timer thread.
-// <i> May be set to 0 when timers are not used.
-// <i> Default: 512
-#ifndef OS_TIMER_THREAD_STACK_SIZE
-#define OS_TIMER_THREAD_STACK_SIZE 512
-#endif
-
-// <o>Timer Thread TrustZone Module Identifier
-// <i> Defines TrustZone Thread Context Management Identifier.
-// <i> Applies only to cores with TrustZone technology.
-// <i> Default: 0 (not used)
-#ifndef OS_TIMER_THREAD_TZ_MOD_ID
-#define OS_TIMER_THREAD_TZ_MOD_ID 0
-#endif
-
-// <o>Timer Callback Queue entries <0-256>
-// <i> Number of concurrent active timer callback functions.
-// <i> May be set to 0 when timers are not used.
-// <i> Default: 4
-#ifndef OS_TIMER_CB_QUEUE
-#define OS_TIMER_CB_QUEUE 4
-#endif
-
-// </h>
-
-// <h>Event Flags Configuration
-// ============================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_EVFLAGS_OBJ_MEM
-#define OS_EVFLAGS_OBJ_MEM 0
-#endif
-
-// <o>Number of Event Flags objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_EVFLAGS_NUM
-#define OS_EVFLAGS_NUM 1
-#endif
-
-// </e>
-
-// </h>
-
-// <h>Mutex Configuration
-// ======================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_MUTEX_OBJ_MEM
-#define OS_MUTEX_OBJ_MEM 0
-#endif
-
-// <o>Number of Mutex objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MUTEX_NUM
-#define OS_MUTEX_NUM 1
-#endif
-
-// </e>
-
-// </h>
-
-// <h>Semaphore Configuration
-// ==========================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_SEMAPHORE_OBJ_MEM
-#define OS_SEMAPHORE_OBJ_MEM 0
-#endif
-
-// <o>Number of Semaphore objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_SEMAPHORE_NUM
-#define OS_SEMAPHORE_NUM 1
-#endif
-
-// </e>
-
-// </h>
-
-// <h>Memory Pool Configuration
-// ============================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_MEMPOOL_OBJ_MEM
-#define OS_MEMPOOL_OBJ_MEM 0
-#endif
-
-// <o>Number of Memory Pool objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MEMPOOL_NUM
-#define OS_MEMPOOL_NUM 1
-#endif
-
-// <o>Data Storage Memory size [bytes] <0-1073741824:8>
-// <i> Defines the combined data storage memory size.
-// <i> Applies to objects with system provided memory for data storage.
-// <i> Default: 0
-#ifndef OS_MEMPOOL_DATA_SIZE
-#define OS_MEMPOOL_DATA_SIZE 0
-#endif
-
-// </e>
-
-// </h>
-
-// <h>Message Queue Configuration
-// ==============================
-
-// <e>Object specific Memory allocation
-// <i> Enables object specific memory allocation.
-#ifndef OS_MSGQUEUE_OBJ_MEM
-#define OS_MSGQUEUE_OBJ_MEM 0
-#endif
-
-// <o>Number of Message Queue objects <1-1000>
-// <i> Defines maximum number of objects that can be active at the same time.
-// <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MSGQUEUE_NUM
-#define OS_MSGQUEUE_NUM 1
-#endif
-
-// <o>Data Storage Memory size [bytes] <0-1073741824:8>
-// <i> Defines the combined data storage memory size.
-// <i> Applies to objects with system provided memory for data storage.
-// <i> Default: 0
-#ifndef OS_MSGQUEUE_DATA_SIZE
-#define OS_MSGQUEUE_DATA_SIZE 0
-#endif
-
-// </e>
-
-// </h>
-
-// <h>Event Recorder Configuration
-// ===============================
-
-// <e>Global Initialization
-// <i> Initialize Event Recorder during 'osKernelInitialize'.
-#ifndef OS_EVR_INIT
-#define OS_EVR_INIT 0
-#endif
-
-// <q>Start recording
-// <i> Start event recording after initialization.
-#ifndef OS_EVR_START
-#define OS_EVR_START 1
-#endif
-
-// <h>Global Event Filter Setup
-// <i> Initial recording level applied to all components.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_LEVEL
-#define OS_EVR_LEVEL 0x00U
-#endif
-
-// <h>RTOS Event Filter Setup
-// <i> Recording levels for RTX components.
-// <i> Only applicable if events for the respective component are generated.
-
-// <h>Memory Management
-// <i> Recording level for Memory Management events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_MEMORY_LEVEL
-#define OS_EVR_MEMORY_LEVEL 0x01U
-#endif
-
-// <h>Kernel
-// <i> Recording level for Kernel events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_KERNEL_LEVEL
-#define OS_EVR_KERNEL_LEVEL 0x01U
-#endif
-
-// <h>Thread
-// <i> Recording level for Thread events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_THREAD_LEVEL
-#define OS_EVR_THREAD_LEVEL 0x05U
-#endif
-
-// <h>Generic Wait
-// <i> Recording level for Generic Wait events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_WAIT_LEVEL
-#define OS_EVR_WAIT_LEVEL 0x01U
-#endif
-
-// <h>Thread Flags
-// <i> Recording level for Thread Flags events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_THFLAGS_LEVEL
-#define OS_EVR_THFLAGS_LEVEL 0x01U
-#endif
-
-// <h>Event Flags
-// <i> Recording level for Event Flags events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_EVFLAGS_LEVEL
-#define OS_EVR_EVFLAGS_LEVEL 0x01U
-#endif
-
-// <h>Timer
-// <i> Recording level for Timer events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_TIMER_LEVEL
-#define OS_EVR_TIMER_LEVEL 0x01U
-#endif
-
-// <h>Mutex
-// <i> Recording level for Mutex events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_MUTEX_LEVEL
-#define OS_EVR_MUTEX_LEVEL 0x01U
-#endif
-
-// <h>Semaphore
-// <i> Recording level for Semaphore events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_SEMAPHORE_LEVEL
-#define OS_EVR_SEMAPHORE_LEVEL 0x01U
-#endif
-
-// <h>Memory Pool
-// <i> Recording level for Memory Pool events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_MEMPOOL_LEVEL
-#define OS_EVR_MEMPOOL_LEVEL 0x01U
-#endif
-
-// <h>Message Queue
-// <i> Recording level for Message Queue events.
-// <o.0>Error events
-// <o.1>API function call events
-// <o.2>Operation events
-// <o.3>Detailed operation events
-// </h>
-#ifndef OS_EVR_MSGQUEUE_LEVEL
-#define OS_EVR_MSGQUEUE_LEVEL 0x01U
-#endif
-
-// </h>
-
-// </e>
-
-// <h>RTOS Event Generation
-// <i> Enables event generation for RTX components (requires RTX source variant).
-
-// <q>Memory Management
-// <i> Enables Memory Management event generation.
-#ifndef OS_EVR_MEMORY
-#define OS_EVR_MEMORY 1
-#endif
-
-// <q>Kernel
-// <i> Enables Kernel event generation.
-#ifndef OS_EVR_KERNEL
-#define OS_EVR_KERNEL 1
-#endif
-
-// <q>Thread
-// <i> Enables Thread event generation.
-#ifndef OS_EVR_THREAD
-#define OS_EVR_THREAD 1
-#endif
-
-// <q>Generic Wait
-// <i> Enables Generic Wait event generation.
-#ifndef OS_EVR_WAIT
-#define OS_EVR_WAIT 1
-#endif
-
-// <q>Thread Flags
-// <i> Enables Thread Flags event generation.
-#ifndef OS_EVR_THFLAGS
-#define OS_EVR_THFLAGS 1
-#endif
-
-// <q>Event Flags
-// <i> Enables Event Flags event generation.
-#ifndef OS_EVR_EVFLAGS
-#define OS_EVR_EVFLAGS 1
-#endif
-
-// <q>Timer
-// <i> Enables Timer event generation.
-#ifndef OS_EVR_TIMER
-#define OS_EVR_TIMER 1
-#endif
-
-// <q>Mutex
-// <i> Enables Mutex event generation.
-#ifndef OS_EVR_MUTEX
-#define OS_EVR_MUTEX 1
-#endif
-
-// <q>Semaphore
-// <i> Enables Semaphore event generation.
-#ifndef OS_EVR_SEMAPHORE
-#define OS_EVR_SEMAPHORE 1
-#endif
-
-// <q>Memory Pool
-// <i> Enables Memory Pool event generation.
-#ifndef OS_EVR_MEMPOOL
-#define OS_EVR_MEMPOOL 1
-#endif
-
-// <q>Message Queue
-// <i> Enables Message Queue event generation.
-#ifndef OS_EVR_MSGQUEUE
-#define OS_EVR_MSGQUEUE 1
-#endif
-
-// </h>
-
-// </h>
-
-// Number of Threads which use standard C/C++ library libspace
-// (when thread specific memory allocation is not used).
-#if (OS_THREAD_OBJ_MEM == 0)
-#ifndef OS_THREAD_LIBSPACE_NUM
-#define OS_THREAD_LIBSPACE_NUM 4
-#endif
-#else
-#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
-#endif
-
-//------------- <<< end of configuration section >>> ---------------------------
-
-#endif // RTX_CONFIG_H_
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h
deleted file mode 100644
index 585d6b8..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h
+++ /dev/null
@@ -1,2483 +0,0 @@
-/* --------------------------------------------------------------------------
- * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All
- * rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * $Date: 25. April 2016
- * $Revision: V2.2.1
- *
- * Project: RTE Device Configuration for NXP LPC43xx
- * -------------------------------------------------------------------------- */
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-
-// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
-// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
-#define RTE_USB_USB0 1
-
-// <h> Pin Configuration
-// <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
-// <i> VBUS drive signal (towards external charge pump or power management unit).
-#define RTE_USB0_PPWR_ID 0
-#if (RTE_USB0_PPWR_ID == 0)
- #define RTE_USB0_PPWR_PIN_EN 0
-#elif (RTE_USB0_PPWR_ID == 1)
- #define RTE_USB0_PPWR_PORT 1
- #define RTE_USB0_PPWR_BIT 7
- #define RTE_USB0_PPWR_FUNC 4
-#elif (RTE_USB0_PPWR_ID == 2)
- #define RTE_USB0_PPWR_PORT 2
- #define RTE_USB0_PPWR_BIT 0
- #define RTE_USB0_PPWR_FUNC 3
-#elif (RTE_USB0_PPWR_ID == 3)
- #define RTE_USB0_PPWR_PORT 2
- #define RTE_USB0_PPWR_BIT 3
- #define RTE_USB0_PPWR_FUNC 7
-#elif (RTE_USB0_PPWR_ID == 4)
- #define RTE_USB0_PPWR_PORT 6
- #define RTE_USB0_PPWR_BIT 3
- #define RTE_USB0_PPWR_FUNC 1
-#else
- #error "Invalid RTE_USB0_PPWR Pin Configuration!"
-#endif
-#ifndef RTE_USB0_PPWR_PIN_EN
- #define RTE_USB0_PPWR_PIN_EN 1
-#endif
-// <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
-// <i> Port power fault signal indicating overcurrent condition.
-// <i> This signal monitors over-current on the USB bus
-// (external circuitry required to detect over-current condition).
-#define RTE_USB0_PWR_FAULT_ID 0
-#if (RTE_USB0_PWR_FAULT_ID == 0)
- #define RTE_USB0_PWR_FAULT_PIN_EN 0
-#elif (RTE_USB0_PWR_FAULT_ID == 1)
- #define RTE_USB0_PWR_FAULT_PORT 1
- #define RTE_USB0_PWR_FAULT_BIT 5
- #define RTE_USB0_PWR_FAULT_FUNC 4
-#elif (RTE_USB0_PWR_FAULT_ID == 2)
- #define RTE_USB0_PWR_FAULT_PORT 2
- #define RTE_USB0_PWR_FAULT_BIT 1
- #define RTE_USB0_PWR_FAULT_FUNC 3
-#elif (RTE_USB0_PWR_FAULT_ID == 3)
- #define RTE_USB0_PWR_FAULT_PORT 2
- #define RTE_USB0_PWR_FAULT_BIT 4
- #define RTE_USB0_PWR_FAULT_FUNC 7
-#elif (RTE_USB0_PWR_FAULT_ID == 4)
- #define RTE_USB0_PWR_FAULT_PORT 6
- #define RTE_USB0_PWR_FAULT_BIT 6
- #define RTE_USB0_PWR_FAULT_FUNC 3
-#elif (RTE_USB0_PWR_FAULT_ID == 5)
- #define RTE_USB0_PWR_FAULT_PORT 8
- #define RTE_USB0_PWR_FAULT_BIT 0
- #define RTE_USB0_PWR_FAULT_FUNC 1
-#else
- #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
-#endif
-#ifndef RTE_USB0_PWR_FAULT_PIN_EN
- #define RTE_USB0_PWR_FAULT_PIN_EN 1
-#endif
-// <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
-// <i> USB0 port indicator LED control output 0
-#define RTE_USB0_IND0_ID 0
-#if (RTE_USB0_IND0_ID == 0)
- #define RTE_USB0_IND0_PIN_EN 0
-#elif (RTE_USB0_IND0_ID == 1)
- #define RTE_USB0_IND0_PORT 1
- #define RTE_USB0_IND0_BIT 4
- #define RTE_USB0_IND0_FUNC 4
-#elif (RTE_USB0_IND0_ID == 2)
- #define RTE_USB0_IND0_PORT 2
- #define RTE_USB0_IND0_BIT 5
- #define RTE_USB0_IND0_FUNC 7
-#elif (RTE_USB0_IND0_ID == 3)
- #define RTE_USB0_IND0_PORT 2
- #define RTE_USB0_IND0_BIT 6
- #define RTE_USB0_IND0_FUNC 3
-#elif (RTE_USB0_IND0_ID == 4)
- #define RTE_USB0_IND0_PORT 6
- #define RTE_USB0_IND0_BIT 8
- #define RTE_USB0_IND0_FUNC 3
-#elif (RTE_USB0_IND0_ID == 5)
- #define RTE_USB0_IND0_PORT 8
- #define RTE_USB0_IND0_BIT 2
- #define RTE_USB0_IND0_FUNC 1
-#else
- #error "Invalid RTE_USB0_IND0 Pin Configuration!"
-#endif
-#ifndef RTE_USB0_IND0_PIN_EN
- #define RTE_USB0_IND0_PIN_EN 1
-#endif
-// <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
-// <i> USB0 port indicator LED control output 1
-#define RTE_USB0_IND1_ID 0
-#if (RTE_USB0_IND1_ID == 0)
- #define RTE_USB0_IND1_PIN_EN 0
-#elif (RTE_USB0_IND1_ID == 1)
- #define RTE_USB0_IND1_PORT 1
- #define RTE_USB0_IND1_BIT 3
- #define RTE_USB0_IND1_FUNC 4
-#elif (RTE_USB0_IND1_ID == 2)
- #define RTE_USB0_IND1_PORT 2
- #define RTE_USB0_IND1_BIT 2
- #define RTE_USB0_IND1_FUNC 3
-#elif (RTE_USB0_IND1_ID == 3)
- #define RTE_USB0_IND1_PORT 6
- #define RTE_USB0_IND1_BIT 7
- #define RTE_USB0_IND1_FUNC 3
-#elif (RTE_USB0_IND1_ID == 4)
- #define RTE_USB0_IND1_PORT 8
- #define RTE_USB0_IND1_BIT 1
- #define RTE_USB0_IND1_FUNC 1
-#else
- #error "Invalid RTE_USB0_IND1 Pin Configuration!"
-#endif
-#ifndef RTE_USB0_IND1_PIN_EN
- #define RTE_USB0_IND1_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> Device [Driver_USBD0]
-// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-// <o.0> High-speed
-// <i> Enable high-speed functionality
-#define RTE_USB_USB0_HS_EN 1
-// </h> Device [Driver_USBD0]
-// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
-
-// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
-// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
-// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
-#define RTE_USB_USB1 0
-
-// <h> Pin Configuration
-// <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
-// <i> VBUS drive signal (towards external charge pump or power management unit).
-#define RTE_USB1_PPWR_ID 1
-#if (RTE_USB1_PPWR_ID == 0)
- #define RTE_USB1_PPWR_PIN_EN 0
-#elif (RTE_USB1_PPWR_ID == 1)
- #define RTE_USB1_PPWR_PORT 9
- #define RTE_USB1_PPWR_BIT 5
- #define RTE_USB1_PPWR_FUNC 2
-#else
- #error "Invalid RTE_USB1_PPWR Pin Configuration!"
-#endif
-#ifndef RTE_USB1_PPWR_PIN_EN
- #define RTE_USB1_PPWR_PIN_EN 1
-#endif
-// <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
-// <i> Port power fault signal indicating overcurrent condition.
-// <i> This signal monitors over-current on the USB bus
-// (external circuitry required to detect over-current condition).
-#define RTE_USB1_PWR_FAULT_ID 1
-#if (RTE_USB1_PWR_FAULT_ID == 0)
- #define RTE_USB1_PWR_FAULT_PIN_EN 0
-#elif (RTE_USB1_PWR_FAULT_ID == 1)
- #define RTE_USB1_PWR_FAULT_PORT 9
- #define RTE_USB1_PWR_FAULT_BIT 6
- #define RTE_USB1_PWR_FAULT_FUNC 2
-#else
- #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
-#endif
-#ifndef RTE_USB1_PWR_FAULT_PIN_EN
- #define RTE_USB1_PWR_FAULT_PIN_EN 1
-#endif
-// <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
-// <i> USB1 port indicator LED control output 0
-#define RTE_USB1_IND0_ID 1
-#if (RTE_USB1_IND0_ID == 0)
- #define RTE_USB1_IND0_PIN_EN 0
-#elif (RTE_USB1_IND0_ID == 1)
- #define RTE_USB1_IND0_PORT 3
- #define RTE_USB1_IND0_BIT 2
- #define RTE_USB1_IND0_FUNC 3
-#elif (RTE_USB1_IND0_ID == 2)
- #define RTE_USB1_IND0_PORT 9
- #define RTE_USB1_IND0_BIT 4
- #define RTE_USB1_IND0_FUNC 2
-#else
- #error "Invalid RTE_USB1_IND0 Pin Configuration!"
-#endif
-#ifndef RTE_USB1_IND0_PIN_EN
- #define RTE_USB1_IND0_PIN_EN 1
-#endif
-// <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
-// <i> USB1 port indicator LED control output 1
-#define RTE_USB1_IND1_ID 1
-#if (RTE_USB1_IND1_ID == 0)
- #define RTE_USB1_IND1_PIN_EN 0
-#elif (RTE_USB1_IND1_ID == 1)
- #define RTE_USB1_IND1_PORT 3
- #define RTE_USB1_IND1_BIT 1
- #define RTE_USB1_IND1_FUNC 3
-#elif (RTE_USB1_IND1_ID == 2)
- #define RTE_USB1_IND1_PORT 9
- #define RTE_USB1_IND1_BIT 3
- #define RTE_USB1_IND1_FUNC 2
-#else
- #error "Invalid RTE_USB1_IND1 Pin Configuration!"
-#endif
-#ifndef RTE_USB1_IND1_PIN_EN
- #define RTE_USB1_IND1_PIN_EN 1
-#endif
-
-// <e> On-chip full-speed PHY
-#define RTE_USB_USB1_FS_PHY_EN 1
-
-// <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
-// <i> Monitors the presence of USB1 bus power.
-#define RTE_USB1_VBUS_ID 1
-#if (RTE_USB1_VBUS_ID == 0)
- #define RTE_USB1_VBUS_PIN_EN 0
-#elif (RTE_USB1_VBUS_ID == 1)
- #define RTE_USB1_VBUS_PORT 2
- #define RTE_USB1_VBUS_BIT 5
- #define RTE_USB1_VBUS_FUNC 2
-#else
- #error "Invalid RTE_USB1_VBUS Pin Configuration!"
-#endif
-#ifndef RTE_USB1_VBUS_PIN_EN
- #define RTE_USB1_VBUS_PIN_EN 1
-#endif
-// </e> On-chip full-speed PHY
-
-// <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
-#define RTE_USB_USB1_HS_PHY_EN 0
-
-// <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
-// <i> USB1 ULPI link CLK signal.
-// <i> 60 MHz clock generated by the PHY.
-#define RTE_USB1_ULPI_CLK_ID 0
-#if (RTE_USB1_ULPI_CLK_ID == 0)
- #define RTE_USB1_ULPI_CLK_PORT 8
- #define RTE_USB1_ULPI_CLK_BIT 8
- #define RTE_USB1_ULPI_CLK_FUNC 1
-#elif (RTE_USB1_ULPI_CLK_ID == 1)
- #define RTE_USB1_ULPI_CLK_PORT 0xC
- #define RTE_USB1_ULPI_CLK_BIT 0
- #define RTE_USB1_ULPI_CLK_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
-#endif
-// <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
-// <i> USB1 ULPI link DIR signal.
-// <i> Controls the ULPI data line direction.
-#define RTE_USB1_ULPI_DIR_ID 0
-#if (RTE_USB1_ULPI_DIR_ID == 0)
- #define RTE_USB1_ULPI_DIR_PORT 0xB
- #define RTE_USB1_ULPI_DIR_BIT 1
- #define RTE_USB1_ULPI_DIR_FUNC 1
-#elif (RTE_USB1_ULPI_DIR_ID == 1)
- #define RTE_USB1_ULPI_DIR_PORT 0xC
- #define RTE_USB1_ULPI_DIR_BIT 11
- #define RTE_USB1_ULPI_DIR_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
-#endif
-// <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
-// <i> USB1 ULPI link STP signal.
-// <i> Asserted to end or interrupt transfers to the PHY.
-#define RTE_USB1_ULPI_STP_ID 0
-#if (RTE_USB1_ULPI_STP_ID == 0)
- #define RTE_USB1_ULPI_STP_PORT 8
- #define RTE_USB1_ULPI_STP_BIT 7
- #define RTE_USB1_ULPI_STP_FUNC 1
-#elif (RTE_USB1_ULPI_STP_ID == 1)
- #define RTE_USB1_ULPI_STP_PORT 0xC
- #define RTE_USB1_ULPI_STP_BIT 10
- #define RTE_USB1_ULPI_STP_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
-#endif
-// <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
-// <i> USB1 ULPI link NXT signal.
-// <i> Data flow control signal from the PHY.
-#define RTE_USB1_ULPI_NXT_ID 0
-#if (RTE_USB1_ULPI_NXT_ID == 0)
- #define RTE_USB1_ULPI_NXT_PORT 8
- #define RTE_USB1_ULPI_NXT_BIT 6
- #define RTE_USB1_ULPI_NXT_FUNC 1
-#elif (RTE_USB1_ULPI_NXT_ID == 1)
- #define RTE_USB1_ULPI_NXT_PORT 0xC
- #define RTE_USB1_ULPI_NXT_BIT 9
- #define RTE_USB1_ULPI_NXT_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
-// <i> USB1 ULPI link bidirectional data line 0.
-#define RTE_USB1_ULPI_D0_ID 0
-#if (RTE_USB1_ULPI_D0_ID == 0)
- #define RTE_USB1_ULPI_D0_PORT 8
- #define RTE_USB1_ULPI_D0_BIT 5
- #define RTE_USB1_ULPI_D0_FUNC 1
-#elif (RTE_USB1_ULPI_D0_ID == 1)
- #define RTE_USB1_ULPI_D0_PORT 0xC
- #define RTE_USB1_ULPI_D0_BIT 8
- #define RTE_USB1_ULPI_D0_FUNC 1
-#elif (RTE_USB1_ULPI_D0_ID == 2)
- #define RTE_USB1_ULPI_D0_PORT 0xD
- #define RTE_USB1_ULPI_D0_BIT 11
- #define RTE_USB1_ULPI_D0_FUNC 5
-#else
- #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
-// <i> USB1 ULPI link bidirectional data line 1.
-#define RTE_USB1_ULPI_D1_ID 0
-#if (RTE_USB1_ULPI_D1_ID == 0)
- #define RTE_USB1_ULPI_D1_PORT 8
- #define RTE_USB1_ULPI_D1_BIT 4
- #define RTE_USB1_ULPI_D1_FUNC 1
-#elif (RTE_USB1_ULPI_D1_ID == 1)
- #define RTE_USB1_ULPI_D1_PORT 0xC
- #define RTE_USB1_ULPI_D1_BIT 7
- #define RTE_USB1_ULPI_D1_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
-// <i> USB1 ULPI link bidirectional data line 2.
-#define RTE_USB1_ULPI_D2_ID 0
-#if (RTE_USB1_ULPI_D2_ID == 0)
- #define RTE_USB1_ULPI_D2_PORT 8
- #define RTE_USB1_ULPI_D2_BIT 3
- #define RTE_USB1_ULPI_D2_FUNC 1
-#elif (RTE_USB1_ULPI_D2_ID == 1)
- #define RTE_USB1_ULPI_D2_PORT 0xC
- #define RTE_USB1_ULPI_D2_BIT 6
- #define RTE_USB1_ULPI_D2_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
-// <i> USB1 ULPI link bidirectional data line 3.
-#define RTE_USB1_ULPI_D3_ID 0
-#if (RTE_USB1_ULPI_D3_ID == 0)
- #define RTE_USB1_ULPI_D3_PORT 0xB
- #define RTE_USB1_ULPI_D3_BIT 6
- #define RTE_USB1_ULPI_D3_FUNC 1
-#elif (RTE_USB1_ULPI_D3_ID == 1)
- #define RTE_USB1_ULPI_D3_PORT 0xC
- #define RTE_USB1_ULPI_D3_BIT 5
- #define RTE_USB1_ULPI_D3_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
-// <i> USB1 ULPI link bidirectional data line 4.
-#define RTE_USB1_ULPI_D4_ID 0
-#if (RTE_USB1_ULPI_D4_ID == 0)
- #define RTE_USB1_ULPI_D4_PORT 0xB
- #define RTE_USB1_ULPI_D4_BIT 5
- #define RTE_USB1_ULPI_D4_FUNC 1
-#elif (RTE_USB1_ULPI_D4_ID == 1)
- #define RTE_USB1_ULPI_D4_PORT 0xC
- #define RTE_USB1_ULPI_D4_BIT 4
- #define RTE_USB1_ULPI_D4_FUNC 1
-#else
- #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
-// <i> USB1 ULPI link bidirectional data line 5.
-#define RTE_USB1_ULPI_D5_ID 0
-#if (RTE_USB1_ULPI_D5_ID == 0)
- #define RTE_USB1_ULPI_D5_PORT 0xB
- #define RTE_USB1_ULPI_D5_BIT 4
- #define RTE_USB1_ULPI_D5_FUNC 1
-#elif (RTE_USB1_ULPI_D5_ID == 1)
- #define RTE_USB1_ULPI_D5_PORT 0xC
- #define RTE_USB1_ULPI_D5_BIT 3
- #define RTE_USB1_ULPI_D5_FUNC 0
-#else
- #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
-// <i> USB1 ULPI link bidirectional data line 6.
-#define RTE_USB1_ULPI_D6_ID 0
-#if (RTE_USB1_ULPI_D6_ID == 0)
- #define RTE_USB1_ULPI_D6_PORT 0xB
- #define RTE_USB1_ULPI_D6_BIT 3
- #define RTE_USB1_ULPI_D6_FUNC 1
-#elif (RTE_USB1_ULPI_D6_ID == 1)
- #define RTE_USB1_ULPI_D6_PORT 0xC
- #define RTE_USB1_ULPI_D6_BIT 2
- #define RTE_USB1_ULPI_D6_FUNC 0
-#else
- #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
-#endif
-// <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
-// <i> USB1 ULPI link bidirectional data line 7.
-#define RTE_USB1_ULPI_D7_ID 0
-#if (RTE_USB1_ULPI_D7_ID == 0)
- #define RTE_USB1_ULPI_D7_PORT 0xB
- #define RTE_USB1_ULPI_D7_BIT 2
- #define RTE_USB1_ULPI_D7_FUNC 1
-#elif (RTE_USB1_ULPI_D7_ID == 1)
- #define RTE_USB1_ULPI_D7_PORT 0xC
- #define RTE_USB1_ULPI_D7_BIT 1
- #define RTE_USB1_ULPI_D7_FUNC 0
-#else
- #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
-#endif
-// </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
-// </h> Pin Configuration
-// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
-
-// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
-// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
-#define RTE_ENET 0
-
-// <e> MII (Media Independent Interface)
-#define RTE_ENET_MII 0
-
-// <o> ENET_TXD0 Pin <0=>P1_18
-#define RTE_ENET_MII_TXD0_PORT_ID 0
-#if (RTE_ENET_MII_TXD0_PORT_ID == 0)
- #define RTE_ENET_MII_TXD0_PORT 1
- #define RTE_ENET_MII_TXD0_PIN 18
- #define RTE_ENET_MII_TXD0_FUNC 3
-#else
- #error "Invalid ENET_TXD0 Pin Configuration!"
-#endif
-// <o> ENET_TXD1 Pin <0=>P1_20
-#define RTE_ENET_MII_TXD1_PORT_ID 0
-#if (RTE_ENET_MII_TXD1_PORT_ID == 0)
- #define RTE_ENET_MII_TXD1_PORT 1
- #define RTE_ENET_MII_TXD1_PIN 20
- #define RTE_ENET_MII_TXD1_FUNC 3
-#else
- #error "Invalid ENET_TXD1 Pin Configuration!"
-#endif
-// <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
-#define RTE_ENET_MII_TXD2_PORT_ID 0
-#if (RTE_ENET_MII_TXD2_PORT_ID == 0)
- #define RTE_ENET_MII_TXD2_PORT 9
- #define RTE_ENET_MII_TXD2_PIN 4
- #define RTE_ENET_MII_TXD2_FUNC 5
-#elif (RTE_ENET_MII_TXD2_PORT_ID == 1)
- #define RTE_ENET_MII_TXD2_PORT 0xC
- #define RTE_ENET_MII_TXD2_PIN 2
- #define RTE_ENET_MII_TXD2_FUNC 3
-#else
- #error "Invalid ENET_TXD2 Pin Configuration!"
-#endif
-// <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
-#define RTE_ENET_MII_TXD3_PORT_ID 0
-#if (RTE_ENET_MII_TXD3_PORT_ID == 0)
- #define RTE_ENET_MII_TXD3_PORT 9
- #define RTE_ENET_MII_TXD3_PIN 5
- #define RTE_ENET_MII_TXD3_FUNC 5
-#elif (RTE_ENET_MII_TXD3_PORT_ID == 1)
- #define RTE_ENET_MII_TXD3_PORT 0xC
- #define RTE_ENET_MII_TXD3_PIN 3
- #define RTE_ENET_MII_TXD3_FUNC 3
-#else
- #error "Invalid ENET_TXD3 Pin Configuration!"
-#endif
-// <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
-#define RTE_ENET_MII_TX_EN_PORT_ID 0
-#if (RTE_ENET_MII_TX_EN_PORT_ID == 0)
- #define RTE_ENET_MII_TX_EN_PORT 0
- #define RTE_ENET_MII_TX_EN_PIN 1
- #define RTE_ENET_MII_TX_EN_FUNC 6
-#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1)
- #define RTE_ENET_MII_TX_EN_PORT 0xC
- #define RTE_ENET_MII_TX_EN_PIN 4
- #define RTE_ENET_MII_TX_EN_FUNC 3
-#else
- #error "Invalid ENET_TX_EN Pin Configuration!"
-#endif
-// <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
-#define RTE_ENET_MII_TX_CLK_PORT_ID 0
-#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
- #define RTE_ENET_MII_TX_CLK_PORT 1
- #define RTE_ENET_MII_TX_CLK_PIN 19
- #define RTE_ENET_MII_TX_CLK_FUNC 0
-#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
- #define RTE_ENET_MII_TX_CLK_PORT 0x10
- #define RTE_ENET_MII_TX_CLK_PIN 0
- #define RTE_ENET_MII_TX_CLK_FUNC 7
-#else
- #error "Invalid ENET_TX_CLK Pin Configuration!"
-#endif
-// <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
-// <i> Optional signal, rarely used
-#define RTE_ENET_MII_TX_ER_PORT_ID 0
-#if (RTE_ENET_MII_TX_ER_PORT_ID == 0)
- #define RTE_ENET_MII_TX_ER_PIN_EN 0
-#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1)
- #define RTE_ENET_MII_TX_ER_PORT 0xC
- #define RTE_ENET_MII_TX_ER_PIN 5
- #define RTE_ENET_MII_TX_ER_FUNC 3
-#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2)
- #define RTE_ENET_MII_TX_ER_PORT 0xC
- #define RTE_ENET_MII_TX_ER_PIN 14
- #define RTE_ENET_MII_TX_ER_FUNC 6
-#else
- #error "Invalid ENET_TX_ER Pin Configuration!"
-#endif
-#ifndef RTE_ENET_MII_TX_ER_PIN_EN
- #define RTE_ENET_MII_TX_ER_PIN_EN 1
-#endif
-// <o> ENET_RXD0 Pin <0=>P1_15
-#define RTE_ENET_MII_RXD0_PORT_ID 0
-#if (RTE_ENET_MII_RXD0_PORT_ID == 0)
- #define RTE_ENET_MII_RXD0_PORT 1
- #define RTE_ENET_MII_RXD0_PIN 15
- #define RTE_ENET_MII_RXD0_FUNC 3
-#else
- #error "Invalid ENET_RXD0 Pin Configuration!"
-#endif
-// <o> ENET_RXD1 Pin <0=>P0_0
-#define RTE_ENET_MII_RXD1_PORT_ID 0
-#if (RTE_ENET_MII_RXD1_PORT_ID == 0)
- #define RTE_ENET_MII_RXD1_PORT 0
- #define RTE_ENET_MII_RXD1_PIN 0
- #define RTE_ENET_MII_RXD1_FUNC 2
-#else
- #error "Invalid ENET_RXD1 Pin Configuration!"
-#endif
-// <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
-#define RTE_ENET_MII_RXD2_PORT_ID 0
-#if (RTE_ENET_MII_RXD2_PORT_ID == 0)
- #define RTE_ENET_MII_RXD2_PORT 9
- #define RTE_ENET_MII_RXD2_PIN 3
- #define RTE_ENET_MII_RXD2_FUNC 5
-#elif (RTE_ENET_MII_RXD2_PORT_ID == 1)
- #define RTE_ENET_MII_RXD2_PORT 0xC
- #define RTE_ENET_MII_RXD2_PIN 6
- #define RTE_ENET_MII_RXD2_FUNC 3
-#else
- #error "Invalid ENET_RXD2 Pin Configuration!"
-#endif
-// <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
-#define RTE_ENET_MII_RXD3_PORT_ID 0
-#if (RTE_ENET_MII_RXD3_PORT_ID == 0)
- #define RTE_ENET_MII_RXD3_PORT 9
- #define RTE_ENET_MII_RXD3_PIN 2
- #define RTE_ENET_MII_RXD3_FUNC 5
-#elif (RTE_ENET_MII_RXD3_PORT_ID == 1)
- #define RTE_ENET_MII_RXD3_PORT 0xC
- #define RTE_ENET_MII_RXD3_PIN 7
- #define RTE_ENET_MII_RXD3_FUNC 3
-#else
- #error "Invalid ENET_RXD3 Pin Configuration!"
-#endif
-// <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
-#define RTE_ENET_MII_RX_DV_PORT_ID 0
-#if (RTE_ENET_MII_RX_DV_PORT_ID == 0)
- #define RTE_ENET_MII_RX_DV_PORT 1
- #define RTE_ENET_MII_RX_DV_PIN 16
- #define RTE_ENET_MII_RX_DV_FUNC 7
-#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1)
- #define RTE_ENET_MII_RX_DV_PORT 0xC
- #define RTE_ENET_MII_RX_DV_PIN 8
- #define RTE_ENET_MII_RX_DV_FUNC 3
-#else
- #error "Invalid ENET_RX_DV Pin Configuration!"
-#endif
-// <o> ENET_RX_CLK Pin <0=>PC_0
-#define RTE_ENET_MII_RX_CLK_PORT_ID 0
-#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
- #define RTE_ENET_MII_RX_CLK_PORT 0xC
- #define RTE_ENET_MII_RX_CLK_PIN 0
- #define RTE_ENET_MII_RX_CLK_FUNC 3
-#else
- #error "Invalid ENET_RX_CLK Pin Configuration!"
-#endif
-// <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
-#define RTE_ENET_MII_RX_ER_PORT_ID 0
-#if (RTE_ENET_MII_RX_ER_PORT_ID == 0)
- #define RTE_ENET_MII_RX_ER_PORT 9
- #define RTE_ENET_MII_RX_ER_PIN 1
- #define RTE_ENET_MII_RX_ER_FUNC 5
-#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1)
- #define RTE_ENET_MII_RX_ER_PORT 0xC
- #define RTE_ENET_MII_RX_ER_PIN 9
- #define RTE_ENET_MII_RX_ER_FUNC 3
-#else
- #error "Invalid ENET_RX_ER Pin Configuration!"
-#endif
-// <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
-#define RTE_ENET_MII_COL_PORT_ID 0
-#if (RTE_ENET_MII_COL_PORT_ID == 0)
- #define RTE_ENET_MII_COL_PORT 0
- #define RTE_ENET_MII_COL_PIN 1
- #define RTE_ENET_MII_COL_FUNC 2
-#elif (RTE_ENET_MII_COL_PORT_ID == 1)
- #define RTE_ENET_MII_COL_PORT 4
- #define RTE_ENET_MII_COL_PIN 1
- #define RTE_ENET_MII_COL_FUNC 7
-#elif (RTE_ENET_MII_COL_PORT_ID == 2)
- #define RTE_ENET_MII_COL_PORT 9
- #define RTE_ENET_MII_COL_PIN 6
- #define RTE_ENET_MII_COL_FUNC 5
-#else
- #error "Invalid ENET_COL Pin Configuration!"
-#endif
-// <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
-#define RTE_ENET_MII_CRS_PORT_ID 0
-#if (RTE_ENET_MII_CRS_PORT_ID == 0)
- #define RTE_ENET_MII_CRS_PORT 1
- #define RTE_ENET_MII_CRS_PIN 16
- #define RTE_ENET_MII_CRS_FUNC 3
-#elif (RTE_ENET_MII_CRS_PORT_ID == 1)
- #define RTE_ENET_MII_CRS_PORT 9
- #define RTE_ENET_MII_CRS_PIN 0
- #define RTE_ENET_MII_CRS_FUNC 5
-#else
- #error "Invalid ENET_CRS Pin Configuration!"
-#endif
-// </e> MII (Media Independent Interface)
-
-// <e> RMII (Reduced Media Independent Interface)
-#define RTE_ENET_RMII 0
-
-// <o> ENET_TXD0 Pin <0=>P1_18
-#define RTE_ENET_RMII_TXD0_PORT_ID 0
-#if (RTE_ENET_RMII_TXD0_PORT_ID == 0)
- #define RTE_ENET_RMII_TXD0_PORT 1
- #define RTE_ENET_RMII_TXD0_PIN 18
- #define RTE_ENET_RMII_TXD0_FUNC 3
-#else
- #error "Invalid ENET_TXD0 Pin Configuration!"
-#endif
-// <o> ENET_TXD1 Pin <0=>P1_20
-#define RTE_ENET_RMII_TXD1_PORT_ID 0
-#if (RTE_ENET_RMII_TXD1_PORT_ID == 0)
- #define RTE_ENET_RMII_TXD1_PORT 1
- #define RTE_ENET_RMII_TXD1_PIN 20
- #define RTE_ENET_RMII_TXD1_FUNC 3
-#else
- #error "Invalid ENET_TXD1 Pin Configuration!"
-#endif
-// <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
-#define RTE_ENET_RMII_TX_EN_PORT_ID 0
-#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
- #define RTE_ENET_RMII_TX_EN_PORT 0
- #define RTE_ENET_RMII_TX_EN_PIN 1
- #define RTE_ENET_RMII_TX_EN_FUNC 6
-#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
- #define RTE_ENET_RMII_TX_EN_PORT 0xC
- #define RTE_ENET_RMII_TX_EN_PIN 4
- #define RTE_ENET_RMII_TX_EN_FUNC 3
-#else
- #error "Invalid ENET_TX_EN Pin Configuration!"
-#endif
-// <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
-#define RTE_ENET_RMII_REF_CLK_PORT_ID 0
-#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
- #define RTE_ENET_RMII_REF_CLK_PORT 1
- #define RTE_ENET_RMII_REF_CLK_PIN 19
- #define RTE_ENET_RMII_REF_CLK_FUNC 0
-#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
- #define RTE_ENET_RMII_REF_CLK_PORT 0x10
- #define RTE_ENET_RMII_REF_CLK_PIN 0
- #define RTE_ENET_RMII_REF_CLK_FUNC 7
-#else
- #error "Invalid ENET_REF_CLK Pin Configuration!"
-#endif
-// <o> ENET_RXD0 Pin <0=>P1_15
-#define RTE_ENET_RMII_RXD0_PORT_ID 0
-#if (RTE_ENET_RMII_RXD0_PORT_ID == 0)
- #define RTE_ENET_RMII_RXD0_PORT 1
- #define RTE_ENET_RMII_RXD0_PIN 15
- #define RTE_ENET_RMII_RXD0_FUNC 3
-#else
- #error "Invalid ENET_RXD0 Pin Configuration!"
-#endif
-// <o> ENET_RXD1 Pin <0=>P0_0
-#define RTE_ENET_RMII_RXD1_PORT_ID 0
-#if (RTE_ENET_RMII_RXD1_PORT_ID == 0)
- #define RTE_ENET_RMII_RXD1_PORT 0
- #define RTE_ENET_RMII_RXD1_PIN 0
- #define RTE_ENET_RMII_RXD1_FUNC 2
-#else
- #error "Invalid ENET_RXD1 Pin Configuration!"
-#endif
-// <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
-#define RTE_ENET_RMII_RX_DV_PORT_ID 0
-#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
- #define RTE_ENET_RMII_RX_DV_PORT 1
- #define RTE_ENET_RMII_RX_DV_PIN 16
- #define RTE_ENET_RMII_RX_DV_FUNC 7
-#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
- #define RTE_ENET_RMII_RX_DV_PORT 0xC
- #define RTE_ENET_RMII_RX_DV_PIN 8
- #define RTE_ENET_RMII_RX_DV_FUNC 3
-#else
- #error "Invalid ENET_RX_DV Pin Configuration!"
-#endif
-// </e> RMII (Reduced Media Independent Interface)
-
-// <h> MIIM (Management Data Interface)
-// <o> ENET_MDIO Pin <0=>P1_17
-#define RTE_ENET_MDI_MDIO_PORT_ID 0
-#if (RTE_ENET_MDI_MDIO_PORT_ID == 0)
- #define RTE_ENET_MDI_MDIO_PORT 1
- #define RTE_ENET_MDI_MDIO_PIN 17
- #define RTE_ENET_MDI_MDIO_FUNC 3
-#else
- #error "Invalid ENET_MDIO Pin Configuration!"
-#endif
-// <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
-#define RTE_ENET_MDI_MDC_PORT_ID 2
-#if (RTE_ENET_MDI_MDC_PORT_ID == 0)
- #define RTE_ENET_MDI_MDC_PORT 2
- #define RTE_ENET_MDI_MDC_PIN 0
- #define RTE_ENET_MDI_MDC_FUNC 7
-#elif (RTE_ENET_MDI_MDC_PORT_ID == 1)
- #define RTE_ENET_MDI_MDC_PORT 7
- #define RTE_ENET_MDI_MDC_PIN 7
- #define RTE_ENET_MDI_MDC_FUNC 6
-#elif (RTE_ENET_MDI_MDC_PORT_ID == 2)
- #define RTE_ENET_MDI_MDC_PORT 0xC
- #define RTE_ENET_MDI_MDC_PIN 1
- #define RTE_ENET_MDI_MDC_FUNC 3
-#else
- #error "Invalid ENET_MDC Pin Configuration!"
-#endif
-// </h> MIIM (Management Data Interface)
-// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
-
-// <e> SD/MMC Interface [Driver_MCI0]
-// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
-#define RTE_SDMMC 0
-
-// <h> SD/MMC Peripheral Bus
-// <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
-#define RTE_SD_CLK_PORT_ID 0
-#if (RTE_SD_CLK_PORT_ID == 0)
- #define RTE_SD_CLK_PORT 0xC
- #define RTE_SD_CLK_PIN 0
- #define RTE_SD_CLK_FUNC 7
-#elif (RTE_SD_CLK_PORT_ID == 1)
- #define RTE_SD_CLK_PORT 0x10
- #define RTE_SD_CLK_PIN 0
- #define RTE_SD_CLK_FUNC 4
-#elif (RTE_SD_CLK_PORT_ID == 2)
- #define RTE_SD_CLK_PORT 0x10
- #define RTE_SD_CLK_PIN 2
- #define RTE_SD_CLK_FUNC 4
-#else
- #error "Invalid SD_CLK Pin Configuration!"
-#endif
-// <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
-#define RTE_SD_CMD_PORT_ID 0
-#if (RTE_SD_CMD_PORT_ID == 0)
- #define RTE_SD_CMD_PORT 1
- #define RTE_SD_CMD_PIN 6
- #define RTE_SD_CMD_FUNC 7
-#elif (RTE_SD_CMD_PORT_ID == 1)
- #define RTE_SD_CMD_PORT 0xC
- #define RTE_SD_CMD_PIN 10
- #define RTE_SD_CMD_FUNC 7
-#else
- #error "Invalid SD_CMD Pin Configuration!"
-#endif
-// <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
-#define RTE_SD_DAT0_PORT_ID 0
-#if (RTE_SD_DAT0_PORT_ID == 0)
- #define RTE_SD_DAT0_PORT 1
- #define RTE_SD_DAT0_PIN 9
- #define RTE_SD_DAT0_FUNC 7
-#elif (RTE_SD_DAT0_PORT_ID == 1)
- #define RTE_SD_DAT0_PORT 0xC
- #define RTE_SD_DAT0_PIN 4
- #define RTE_SD_DAT0_FUNC 7
-#else
- #error "Invalid SD_DAT0 Pin Configuration!"
-#endif
-// <e> SD_DAT[1 .. 3]
-#define RTE_SDMMC_BUS_WIDTH_4 0
-// <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
-#define RTE_SD_DAT1_PORT_ID 0
-#if (RTE_SD_DAT1_PORT_ID == 0)
- #define RTE_SD_DAT1_PORT 1
- #define RTE_SD_DAT1_PIN 10
- #define RTE_SD_DAT1_FUNC 7
-#elif (RTE_SD_DAT1_PORT_ID == 1)
- #define RTE_SD_DAT1_PORT 0xC
- #define RTE_SD_DAT1_PIN 5
- #define RTE_SD_DAT1_FUNC 7
-#else
- #error "Invalid SD_DAT1 Pin Configuration!"
-#endif
-// <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
-#define RTE_SD_DAT2_PORT_ID 0
-#if (RTE_SD_DAT2_PORT_ID == 0)
- #define RTE_SD_DAT2_PORT 1
- #define RTE_SD_DAT2_PIN 11
- #define RTE_SD_DAT2_FUNC 7
-#elif (RTE_SD_DAT2_PORT_ID == 1)
- #define RTE_SD_DAT2_PORT 0xC
- #define RTE_SD_DAT2_PIN 6
- #define RTE_SD_DAT2_FUNC 7
-#else
- #error "Invalid SD_DAT2 Pin Configuration!"
-#endif
-// <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
-#define RTE_SD_DAT3_PORT_ID 0
-#if (RTE_SD_DAT3_PORT_ID == 0)
- #define RTE_SD_DAT3_PORT 1
- #define RTE_SD_DAT3_PIN 12
- #define RTE_SD_DAT3_FUNC 7
-#elif (RTE_SD_DAT3_PORT_ID == 1)
- #define RTE_SD_DAT3_PORT 0xC
- #define RTE_SD_DAT3_PIN 7
- #define RTE_SD_DAT3_FUNC 7
-#else
- #error "Invalid SD_DAT3 Pin Configuration!"
-#endif
-// </e> SD_DAT[1 .. 3]
-// <e> SD_DAT[4 .. 7]
-#define RTE_SDMMC_BUS_WIDTH_8 0
-// <o> SD_DAT4 Pin <0=>PC_11
-#define RTE_SD_DAT4_PORT_ID 0
-#if (RTE_SD_DAT4_PORT_ID == 0)
- #define RTE_SD_DAT4_PORT 0xC
- #define RTE_SD_DAT4_PIN 11
- #define RTE_SD_DAT4_FUNC 7
-#else
- #error "Invalid SD_DAT4 Pin Configuration!"
-#endif
-// <o> SD_DAT5 Pin <0=>PC_12
-#define RTE_SD_DAT5_PORT_ID 0
-#if (RTE_SD_DAT5_PORT_ID == 0)
- #define RTE_SD_DAT5_PORT 0xC
- #define RTE_SD_DAT5_PIN 12
- #define RTE_SD_DAT5_FUNC 7
-#else
- #error "Invalid SD_DAT5 Pin Configuration!"
-#endif
-// <o> SD_DAT6 Pin <0=>PC_13
-#define RTE_SD_DAT6_PORT_ID 0
-#if (RTE_SD_DAT6_PORT_ID == 0)
- #define RTE_SD_DAT6_PORT 0xC
- #define RTE_SD_DAT6_PIN 13
- #define RTE_SD_DAT6_FUNC 7
-#else
- #error "Invalid SD_DAT6 Pin Configuration!"
-#endif
-// <o> SD_DAT7 Pin <0=>PC_14
-#define RTE_SD_DAT7_PORT_ID 0
-#if (RTE_SD_DAT7_PORT_ID == 0)
- #define RTE_SD_DAT7_PORT 0xC
- #define RTE_SD_DAT7_PIN 14
- #define RTE_SD_DAT7_FUNC 7
-#else
- #error "Invalid SD_DAT7 Pin Configuration!"
-#endif
-// </e> SD_DAT[4 .. 7]
-// </h> SD/MMC Peripheral Bus
-
-// <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
-// <i> Configure Pin if exists
-#define RTE_SD_CD_PORT_ID 0
-#if (RTE_SD_CD_PORT_ID == 0)
- #define RTE_SD_CD_PIN_EN 0
-#elif (RTE_SD_CD_PORT_ID == 1)
- #define RTE_SD_CD_PORT 1
- #define RTE_SD_CD_PIN 13
- #define RTE_SD_CD_FUNC 7
-#elif (RTE_SD_CD_PORT_ID == 2)
- #define RTE_SD_CD_PORT 0xC
- #define RTE_SD_CD_PIN 8
- #define RTE_SD_CD_FUNC 7
-#else
- #error "Invalid SD_CD Pin Configuration!"
-#endif
-#ifndef RTE_SD_CD_PIN_EN
- #define RTE_SD_CD_PIN_EN 1
-#endif
-// <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
-// <i> Configure Pin if exists
-#define RTE_SD_WP_PORT_ID 0
-#if (RTE_SD_WP_PORT_ID == 0)
- #define RTE_SD_WP_PIN_EN 0
-#elif (RTE_SD_WP_PORT_ID == 1)
- #define RTE_SD_WP_PORT 0xD
- #define RTE_SD_WP_PIN 15
- #define RTE_SD_WP_FUNC 5
-#elif (RTE_SD_WP_PORT_ID == 2)
- #define RTE_SD_WP_PORT 0xF
- #define RTE_SD_WP_PIN 10
- #define RTE_SD_WP_FUNC 6
-#else
- #error "Invalid SD_WP Pin Configuration!"
-#endif
-#ifndef RTE_SD_WP_PIN_EN
- #define RTE_SD_WP_PIN_EN 1
-#endif
-// <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
-// <i> Configure Pin if exists
-#define RTE_SD_POW_PORT_ID 0
-#if (RTE_SD_POW_PORT_ID == 0)
- #define RTE_SD_POW_PIN_EN 0
-#elif (RTE_SD_POW_PORT_ID == 1)
- #define RTE_SD_POW_PORT 1
- #define RTE_SD_POW_PIN 5
- #define RTE_SD_POW_FUNC 7
-#elif (RTE_SD_POW_PORT_ID == 2)
- #define RTE_SD_POW_PORT 0xC
- #define RTE_SD_POW_PIN 9
- #define RTE_SD_POW_FUNC 7
-#elif (RTE_SD_POW_PORT_ID == 3)
- #define RTE_SD_POW_PORT 0xD
- #define RTE_SD_POW_PIN 1
- #define RTE_SD_POW_FUNC 5
-#else
- #error "Invalid SD_POW Pin Configuration!"
-#endif
-#ifndef RTE_SD_POW_PIN_EN
- #define RTE_SD_POW_PIN_EN 1
-#endif
-// <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
-// <i> Configure Pin if exists
-#define RTE_SD_RST_PORT_ID 0
-#if (RTE_SD_RST_PORT_ID == 0)
- #define RTE_SD_RST_PIN_EN 0
-#elif (RTE_SD_RST_PORT_ID == 1)
- #define RTE_SD_RST_PORT 1
- #define RTE_SD_RST_PIN 3
- #define RTE_SD_RST_FUNC 7
-#elif (RTE_SD_RST_PORT_ID == 2)
- #define RTE_SD_RST_PORT 0xC
- #define RTE_SD_RST_PIN 2
- #define RTE_SD_RST_FUNC 7
-#else
- #error "Invalid SD_RST Pin Configuration!"
-#endif
-#ifndef RTE_SD_RST_PIN_EN
- #define RTE_SD_RST_PIN_EN 1
-#endif
-// </e> SD/MMC Interface [Driver_MCI0]
-
-// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
-// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
-// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
-#define RTE_I2C0 0
-
-// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
-// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
-#define RTE_I2C1 0
-
-// <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
-#define RTE_I2C1_SCL_PORT_ID 0
-#if (RTE_I2C1_SCL_PORT_ID == 0)
- #define RTE_I2C1_SCL_PORT 2
- #define RTE_I2C1_SCL_PIN 4
- #define RTE_I2C1_SCL_FUNC 1
-#elif (RTE_I2C1_SCL_PORT_ID == 1)
- #define RTE_I2C1_SCL_PORT 0xE
- #define RTE_I2C1_SCL_PIN 15
- #define RTE_I2C1_SCL_FUNC 2
-#else
- #error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-// <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
-#define RTE_I2C1_SDA_PORT_ID 0
-#if (RTE_I2C1_SDA_PORT_ID == 0)
- #define RTE_I2C1_SDA_PORT 2
- #define RTE_I2C1_SDA_PIN 3
- #define RTE_I2C1_SDA_FUNC 1
-#elif (RTE_I2C1_SDA_PORT_ID == 1)
- #define RTE_I2C1_SDA_PORT 0xE
- #define RTE_I2C1_SDA_PIN 13
- #define RTE_I2C1_SDA_FUNC 2
-#else
- #error "Invalid I2C1_SDA Pin Configuration!"
-#endif
-// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
-
-// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
-#define RTE_USART0 0
-
-// <h> Pin Configuration
-// <o> TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10
-// <i> USART0 Serial Output pin
-#define RTE_USART0_TX_ID 0
-#if (RTE_USART0_TX_ID == 0)
- #define RTE_USART0_TX_PIN_EN 0
-#elif (RTE_USART0_TX_ID == 1)
- #define RTE_USART0_TX_PORT 2
- #define RTE_USART0_TX_BIT 0
- #define RTE_USART0_TX_FUNC 1
-#elif (RTE_USART0_TX_ID == 2)
- #define RTE_USART0_TX_PORT 6
- #define RTE_USART0_TX_BIT 4
- #define RTE_USART0_TX_FUNC 2
-#elif (RTE_USART0_TX_ID == 3)
- #define RTE_USART0_TX_PORT 9
- #define RTE_USART0_TX_BIT 5
- #define RTE_USART0_TX_FUNC 7
-#elif (RTE_USART0_TX_ID == 4)
- #define RTE_USART0_TX_PORT 0xF
- #define RTE_USART0_TX_BIT 10
- #define RTE_USART0_TX_FUNC 1
-#else
- #error "Invalid USART0_TX Pin Configuration!"
-#endif
-#ifndef RTE_USART0_TX_PIN_EN
- #define RTE_USART0_TX_PIN_EN 1
-#endif
-// <o> RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11
-// <i> USART0 Serial Input pin
-#define RTE_USART0_RX_ID 0
-#if (RTE_USART0_RX_ID == 0)
- #define RTE_USART0_RX_PIN_EN 0
-#elif (RTE_USART0_RX_ID == 1)
- #define RTE_USART0_RX_PORT 2
- #define RTE_USART0_RX_BIT 1
- #define RTE_USART0_RX_FUNC 1
-#elif (RTE_USART0_RX_ID == 2)
- #define RTE_USART0_RX_PORT 6
- #define RTE_USART0_RX_BIT 5
- #define RTE_USART0_RX_FUNC 2
-#elif (RTE_USART0_RX_ID == 3)
- #define RTE_USART0_RX_PORT 9
- #define RTE_USART0_RX_BIT 6
- #define RTE_USART0_RX_FUNC 7
-#elif (RTE_USART0_RX_ID == 4)
- #define RTE_USART0_RX_PORT 0xF
- #define RTE_USART0_RX_BIT 11
- #define RTE_USART0_RX_FUNC 1
-#else
- #error "Invalid USART0_RX Pin Configuration!"
-#endif
-#ifndef RTE_USART0_RX_PIN_EN
- #define RTE_USART0_RX_PIN_EN 1
-#endif
-// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
-// <i> USART0 Serial Clock input/output synchronous mode
-#define RTE_USART0_UCLK_ID 0
-#if (RTE_USART0_UCLK_ID == 0)
- #define RTE_USART0_UCLK_PIN_EN 0
-#elif (RTE_USART0_UCLK_ID == 1)
- #define RTE_USART0_UCLK_PORT 2
- #define RTE_USART0_UCLK_BIT 2
- #define RTE_USART0_UCLK_FUNC 1
-#elif (RTE_USART0_UCLK_ID == 2)
- #define RTE_USART0_UCLK_PORT 6
- #define RTE_USART0_UCLK_BIT 1
- #define RTE_USART0_UCLK_FUNC 2
-#elif (RTE_USART0_UCLK_ID == 3)
- #define RTE_USART0_UCLK_PORT 0xF
- #define RTE_USART0_UCLK_BIT 8
- #define RTE_USART0_UCLK_FUNC 1
-#else
- #error "Invalid USART0_UCLK Pin Configuration!"
-#endif
-#ifndef RTE_USART0_UCLK_PIN_EN
- #define RTE_USART0_UCLK_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11)
-// </e>
-#define RTE_USART0_DMA_TX_EN 0
-#define RTE_USART0_DMA_TX_CH 0
-#define RTE_USART0_DMA_TX_PERI_ID 0
-#if (RTE_USART0_DMA_TX_PERI_ID == 0)
- #define RTE_USART0_DMA_TX_PERI 1
- #define RTE_USART0_DMA_TX_PERI_SEL 1
-#elif (RTE_USART0_DMA_TX_PERI_ID == 1)
- #define RTE_USART0_DMA_TX_PERI 11
- #define RTE_USART0_DMA_TX_PERI_SEL 2
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12)
-// </e>
-#define RTE_USART0_DMA_RX_EN 0
-#define RTE_USART0_DMA_RX_CH 1
-#define RTE_USART0_DMA_RX_PERI_ID 0
-#if (RTE_USART0_DMA_RX_PERI_ID == 0)
- #define RTE_USART0_DMA_RX_PERI 2
- #define RTE_USART0_DMA_RX_PERI_SEL 1
-#elif (RTE_USART0_DMA_RX_PERI_ID == 1)
- #define RTE_USART0_DMA_RX_PERI 12
- #define RTE_USART0_DMA_RX_PERI_SEL 2
-#endif
-// </h> DMA
-// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
-
-// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
-#define RTE_UART1 1
-
-// <h> Pin Configuration
-// <o> TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11
-// <i> UART0 Serial Output pin
-#define RTE_UART1_TX_ID 0
-#if (RTE_UART1_TX_ID == 0)
- #define RTE_UART1_TX_PIN_EN 0
-#elif (RTE_UART1_TX_ID == 1)
- #define RTE_UART1_TX_PORT 1
- #define RTE_UART1_TX_BIT 13
- #define RTE_UART1_TX_FUNC 1
-#elif (RTE_UART1_TX_ID == 2)
- #define RTE_UART1_TX_PORT 3
- #define RTE_UART1_TX_BIT 4
- #define RTE_UART1_TX_FUNC 4
-#elif (RTE_UART1_TX_ID == 3)
- #define RTE_UART1_TX_PORT 5
- #define RTE_UART1_TX_BIT 6
- #define RTE_UART1_TX_FUNC 4
-#elif (RTE_UART1_TX_ID == 4)
- #define RTE_UART1_TX_PORT 0xC
- #define RTE_UART1_TX_BIT 13
- #define RTE_UART1_TX_FUNC 2
-#elif (RTE_UART1_TX_ID == 5)
- #define RTE_UART1_TX_PORT 0xE
- #define RTE_UART1_TX_BIT 11
- #define RTE_UART1_TX_FUNC 2
-#else
- #error "Invalid UART1_TX Pin Configuration!"
-#endif
-#ifndef RTE_UART1_TX_PIN_EN
- #define RTE_UART1_TX_PIN_EN 1
-#endif
-// <o> RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12
-// <i> UART1 Serial Input pin
-#define RTE_UART1_RX_ID 1
-#if (RTE_UART1_RX_ID == 0)
- #define RTE_UART1_RX_PIN_EN 0
-#elif (RTE_UART1_RX_ID == 1)
- #define RTE_UART1_RX_PORT 1
- #define RTE_UART1_RX_BIT 14
- #define RTE_UART1_RX_FUNC 1
-#elif (RTE_UART1_RX_ID == 2)
- #define RTE_UART1_RX_PORT 3
- #define RTE_UART1_RX_BIT 5
- #define RTE_UART1_RX_FUNC 4
-#elif (RTE_UART1_RX_ID == 3)
- #define RTE_UART1_RX_PORT 5
- #define RTE_UART1_RX_BIT 7
- #define RTE_UART1_RX_FUNC 4
-#elif (RTE_UART1_RX_ID == 4)
- #define RTE_UART1_RX_PORT 0xC
- #define RTE_UART1_RX_BIT 14
- #define RTE_UART1_RX_FUNC 2
-#elif (RTE_UART1_RX_ID == 5)
- #define RTE_UART1_RX_PORT 0xE
- #define RTE_UART1_RX_BIT 12
- #define RTE_UART1_RX_FUNC 2
-#else
- #error "Invalid UART1_RX Pin Configuration!"
-#endif
-#ifndef RTE_UART1_RX_PIN_EN
- #define RTE_UART1_RX_PIN_EN 1
-#endif
-
-// <h> Modem Lines
-// <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
-#define RTE_UART1_CTS_ID 0
-#if (RTE_UART1_CTS_ID == 0)
- #define RTE_UART1_CTS_PIN_EN 0
-#elif (RTE_UART1_CTS_ID == 1)
- #define RTE_UART1_CTS_PORT 1
- #define RTE_UART1_CTS_BIT 11
- #define RTE_UART1_CTS_FUNC 1
-#elif (RTE_UART1_CTS_ID == 2)
- #define RTE_UART1_CTS_PORT 5
- #define RTE_UART1_CTS_BIT 4
- #define RTE_UART1_CTS_FUNC 4
-#elif (RTE_UART1_CTS_ID == 3)
- #define RTE_UART1_CTS_PORT 0xC
- #define RTE_UART1_CTS_BIT 2
- #define RTE_UART1_CTS_FUNC 2
-#elif (RTE_UART1_CTS_ID == 4)
- #define RTE_UART1_CTS_PORT 0xE
- #define RTE_UART1_CTS_BIT 7
- #define RTE_UART1_CTS_FUNC 2
-#else
- #error "Invalid UART1_CTS Pin Configuration!"
-#endif
-#ifndef RTE_UART1_CTS_PIN_EN
- #define RTE_UART1_CTS_PIN_EN 1
-#endif
-// <o> RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5
-#define RTE_UART1_RTS_ID 0
-#if (RTE_UART1_RTS_ID == 0)
- #define RTE_UART1_RTS_PIN_EN 0
-#elif (RTE_UART1_RTS_ID == 1)
- #define RTE_UART1_RTS_PORT 1
- #define RTE_UART1_RTS_BIT 9
- #define RTE_UART1_RTS_FUNC 1
-#elif (RTE_UART1_RTS_ID == 2)
- #define RTE_UART1_RTS_PORT 5
- #define RTE_UART1_RTS_BIT 2
- #define RTE_UART1_RTS_FUNC 4
-#elif (RTE_UART1_RTS_ID == 3)
- #define RTE_UART1_RTS_PORT 0xC
- #define RTE_UART1_RTS_BIT 3
- #define RTE_UART1_RTS_FUNC 2
-#elif (RTE_UART1_RTS_ID == 4)
- #define RTE_UART1_RTS_PORT 0xE
- #define RTE_UART1_RTS_BIT 5
- #define RTE_UART1_RTS_FUNC 2
-#else
- #error "Invalid UART1_RTS Pin Configuration!"
-#endif
-#ifndef RTE_UART1_RTS_PIN_EN
- #define RTE_UART1_RTS_PIN_EN 1
-#endif
-// <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
-#define RTE_UART1_DCD_ID 0
-#if (RTE_UART1_DCD_ID == 0)
- #define RTE_UART1_DCD_PIN_EN 0
-#elif (RTE_UART1_DCD_ID == 1)
- #define RTE_UART1_DCD_PORT 1
- #define RTE_UART1_DCD_BIT 12
- #define RTE_UART1_DCD_FUNC 1
-#elif (RTE_UART1_DCD_ID == 2)
- #define RTE_UART1_DCD_PORT 5
- #define RTE_UART1_DCD_BIT 5
- #define RTE_UART1_DCD_FUNC 4
-#elif (RTE_UART1_DCD_ID == 3)
- #define RTE_UART1_DCD_PORT 0xC
- #define RTE_UART1_DCD_BIT 11
- #define RTE_UART1_DCD_FUNC 2
-#elif (RTE_UART1_DCD_ID == 4)
- #define RTE_UART1_DCD_PORT 0xE
- #define RTE_UART1_DCD_BIT 9
- #define RTE_UART1_DCD_FUNC 2
-#else
- #error "Invalid UART1_DCD Pin Configuration!"
-#endif
-#ifndef RTE_UART1_DCD_PIN_EN
- #define RTE_UART1_DCD_PIN_EN 1
-#endif
-// <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
-#define RTE_UART1_DSR_ID 0
-#if (RTE_UART1_DSR_ID == 0)
- #define RTE_UART1_DSR_PIN_EN 0
-#elif (RTE_UART1_DSR_ID == 1)
- #define RTE_UART1_DSR_PORT 1
- #define RTE_UART1_DSR_BIT 7
- #define RTE_UART1_DSR_FUNC 1
-#elif (RTE_UART1_DSR_ID == 2)
- #define RTE_UART1_DSR_PORT 5
- #define RTE_UART1_DSR_BIT 0
- #define RTE_UART1_DSR_FUNC 4
-#elif (RTE_UART1_DSR_ID == 3)
- #define RTE_UART1_DSR_PORT 0xC
- #define RTE_UART1_DSR_BIT 10
- #define RTE_UART1_DSR_FUNC 2
-#elif (RTE_UART1_DSR_ID == 4)
- #define RTE_UART1_DSR_PORT 0xE
- #define RTE_UART1_DSR_BIT 8
- #define RTE_UART1_DSR_FUNC 2
-#else
- #error "Invalid UART1_DSR Pin Configuration!"
-#endif
-#ifndef RTE_UART1_DSR_PIN_EN
- #define RTE_UART1_DSR_PIN_EN 1
-#endif
-// <o> DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10
-#define RTE_UART1_DTR_ID 0
-#if (RTE_UART1_DTR_ID == 0)
- #define RTE_UART1_DTR_PIN_EN 0
-#elif (RTE_UART1_DTR_ID == 1)
- #define RTE_UART1_DTR_PORT 1
- #define RTE_UART1_DTR_BIT 8
- #define RTE_UART1_DTR_FUNC 1
-#elif (RTE_UART1_DTR_ID == 2)
- #define RTE_UART1_DTR_PORT 5
- #define RTE_UART1_DTR_BIT 1
- #define RTE_UART1_DTR_FUNC 4
-#elif (RTE_UART1_DTR_ID == 3)
- #define RTE_UART1_DTR_PORT 0xC
- #define RTE_UART1_DTR_BIT 12
- #define RTE_UART1_DTR_FUNC 2
-#elif (RTE_UART1_DTR_ID == 4)
- #define RTE_UART1_DTR_PORT 0xE
- #define RTE_UART1_DTR_BIT 10
- #define RTE_UART1_DTR_FUNC 2
-#else
- #error "Invalid UART1_DTR Pin Configuration!"
-#endif
-#ifndef RTE_UART1_DTR_PIN_EN
- #define RTE_UART1_DTR_PIN_EN 1
-#endif
-// <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
-#define RTE_UART1_RI_ID 0
-#if (RTE_UART1_RI_ID == 0)
- #define RTE_UART1_RI_PIN_EN 0
-#elif (RTE_UART1_RI_ID == 1)
- #define RTE_UART1_RI_PORT 1
- #define RTE_UART1_RI_BIT 10
- #define RTE_UART1_RI_FUNC 1
-#elif (RTE_UART1_RI_ID == 2)
- #define RTE_UART1_RI_PORT 5
- #define RTE_UART1_RI_BIT 3
- #define RTE_UART1_RI_FUNC 4
-#elif (RTE_UART1_RI_ID == 3)
- #define RTE_UART1_RI_PORT 0xC
- #define RTE_UART1_RI_BIT 1
- #define RTE_UART1_RI_FUNC 2
-#elif (RTE_UART1_RI_ID == 4)
- #define RTE_UART1_RI_PORT 0xE
- #define RTE_UART1_RI_BIT 6
- #define RTE_UART1_RI_FUNC 2
-#else
- #error "Invalid UART1_RI Pin Configuration!"
-#endif
-#ifndef RTE_UART1_RI_PIN_EN
- #define RTE_UART1_RI_PIN_EN 1
-#endif
-// </h> Modem Lines
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>3 (DMAMUXPER3)
-// </e>
-#define RTE_UART1_DMA_TX_EN 0
-#define RTE_UART1_DMA_TX_CH 0
-#define RTE_UART1_DMA_TX_PERI_ID 0
-#if (RTE_UART1_DMA_TX_PERI_ID == 0)
- #define RTE_UART1_DMA_TX_PERI 3
- #define RTE_UART1_DMA_TX_PERI_SEL 1
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>4 (DMAMUXPER4)
-// </e>
-#define RTE_UART1_DMA_RX_EN 0
-#define RTE_UART1_DMA_RX_CH 1
-#define RTE_UART1_DMA_RX_PERI_ID 0
-#if (RTE_UART1_DMA_RX_PERI_ID == 0)
- #define RTE_UART1_DMA_RX_PERI 4
- #define RTE_UART1_DMA_RX_PERI_SEL 1
-#endif
-// </h> DMA
-// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
-
-// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
-#define RTE_USART2 0
-
-// <h> Pin Configuration
-// <o> TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1
-// <i> USART2 Serial Output pin
-#define RTE_USART2_TX_ID 0
-#if (RTE_USART2_TX_ID == 0)
- #define RTE_USART2_TX_PIN_EN 0
-#elif (RTE_USART2_TX_ID == 1)
- #define RTE_USART2_TX_PORT 1
- #define RTE_USART2_TX_BIT 15
- #define RTE_USART2_TX_FUNC 1
-#elif (RTE_USART2_TX_ID == 2)
- #define RTE_USART2_TX_PORT 2
- #define RTE_USART2_TX_BIT 10
- #define RTE_USART2_TX_FUNC 2
-#elif (RTE_USART2_TX_ID == 3)
- #define RTE_USART2_TX_PORT 7
- #define RTE_USART2_TX_BIT 1
- #define RTE_USART2_TX_FUNC 6
-#elif (RTE_USART2_TX_ID == 4)
- #define RTE_USART2_TX_PORT 0xA
- #define RTE_USART2_TX_BIT 1
- #define RTE_USART2_TX_FUNC 3
-#else
- #error "Invalid USART2_TX Pin Configuration!"
-#endif
-#ifndef RTE_USART2_TX_PIN_EN
- #define RTE_USART2_TX_PIN_EN 1
-#endif
-// <o> RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2
-// <i> USART2 Serial Input pin
-#define RTE_USART2_RX_ID 0
-#if (RTE_USART2_RX_ID == 0)
- #define RTE_USART2_RX_PIN_EN 0
-#elif (RTE_USART2_RX_ID == 1)
- #define RTE_USART2_RX_PORT 1
- #define RTE_USART2_RX_BIT 16
- #define RTE_USART2_RX_FUNC 1
-#elif (RTE_USART2_RX_ID == 2)
- #define RTE_USART2_RX_PORT 2
- #define RTE_USART2_RX_BIT 11
- #define RTE_USART2_RX_FUNC 2
-#elif (RTE_USART2_RX_ID == 3)
- #define RTE_USART2_RX_PORT 7
- #define RTE_USART2_RX_BIT 2
- #define RTE_USART2_RX_FUNC 6
-#elif (RTE_USART2_RX_ID == 4)
- #define RTE_USART2_RX_PORT 0xA
- #define RTE_USART2_RX_BIT 2
- #define RTE_USART2_RX_FUNC 3
-#else
- #error "Invalid USART2_RX Pin Configuration!"
-#endif
-#ifndef RTE_USART2_RX_PIN_EN
- #define RTE_USART2_RX_PIN_EN 1
-#endif
-// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
-// <i> USART2 Serial Clock input/output synchronous mode
-#define RTE_USART2_UCLK_ID 0
-#if (RTE_USART2_UCLK_ID == 0)
- #define RTE_USART2_UCLK_PIN_EN 0
-#elif (RTE_USART2_UCLK_ID == 1)
- #define RTE_USART2_UCLK_PORT 1
- #define RTE_USART2_UCLK_BIT 17
- #define RTE_USART2_UCLK_FUNC 1
-#elif (RTE_USART2_UCLK_ID == 2)
- #define RTE_USART2_UCLK_PORT 2
- #define RTE_USART2_UCLK_BIT 12
- #define RTE_USART2_UCLK_FUNC 7
-#else
- #error "Invalid USART2_UCLK Pin Configuration!"
-#endif
-#ifndef RTE_USART2_UCLK_PIN_EN
- #define RTE_USART2_UCLK_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>5 (DMAMUXPER5)
-// </e>
-#define RTE_USART2_DMA_TX_EN 0
-#define RTE_USART2_DMA_TX_CH 0
-#define RTE_USART2_DMA_TX_PERI_ID 0
-#if (RTE_USART2_DMA_TX_PERI_ID == 0)
- #define RTE_USART2_DMA_TX_PERI 5
- #define RTE_USART2_DMA_TX_PERI_SEL 1
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>6 (DMAMUXPER6)
-// </e>
-#define RTE_USART2_DMA_RX_EN 0
-#define RTE_USART2_DMA_RX_CH 1
-#define RTE_USART2_DMA_RX_PERI_ID 0
-#if (RTE_USART2_DMA_RX_PERI_ID == 0)
- #define RTE_USART2_DMA_RX_PERI 6
- #define RTE_USART2_DMA_RX_PERI_SEL 1
-#endif
-// </h> DMA
-// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
-
-// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
-#define RTE_USART3 0
-
-// <h> Pin Configuration
-// <o> TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2
-// <i> USART3 Serial Output pin
-#define RTE_USART3_TX_ID 0
-#if (RTE_USART3_TX_ID == 0)
- #define RTE_USART3_TX_PIN_EN 0
-#elif (RTE_USART3_TX_ID == 1)
- #define RTE_USART3_TX_PORT 2
- #define RTE_USART3_TX_BIT 3
- #define RTE_USART3_TX_FUNC 2
-#elif (RTE_USART3_TX_ID == 2)
- #define RTE_USART3_TX_PORT 4
- #define RTE_USART3_TX_BIT 1
- #define RTE_USART3_TX_FUNC 6
-#elif (RTE_USART3_TX_ID == 3)
- #define RTE_USART3_TX_PORT 9
- #define RTE_USART3_TX_BIT 3
- #define RTE_USART3_TX_FUNC 7
-#elif (RTE_USART3_TX_ID == 4)
- #define RTE_USART3_TX_PORT 0xF
- #define RTE_USART3_TX_BIT 2
- #define RTE_USART3_TX_FUNC 1
-#else
- #error "Invalid USART3_TX Pin Configuration!"
-#endif
-#ifndef RTE_USART3_TX_PIN_EN
- #define RTE_USART3_TX_PIN_EN 1
-#endif
-// <o> RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3
-// <i> USART3 Serial Input pin
-#define RTE_USART3_RX_ID 0
-#if (RTE_USART3_RX_ID == 0)
- #define RTE_USART3_RX_PIN_EN 0
-#elif (RTE_USART3_RX_ID == 1)
- #define RTE_USART3_RX_PORT 2
- #define RTE_USART3_RX_BIT 4
- #define RTE_USART3_RX_FUNC 2
-#elif (RTE_USART3_RX_ID == 2)
- #define RTE_USART3_RX_PORT 4
- #define RTE_USART3_RX_BIT 2
- #define RTE_USART3_RX_FUNC 6
-#elif (RTE_USART3_RX_ID == 3)
- #define RTE_USART3_RX_PORT 9
- #define RTE_USART3_RX_BIT 4
- #define RTE_USART3_RX_FUNC 7
-#elif (RTE_USART3_RX_ID == 4)
- #define RTE_USART3_RX_PORT 0xF
- #define RTE_USART3_RX_BIT 3
- #define RTE_USART3_RX_FUNC 1
-#else
- #error "Invalid USART3_RX Pin Configuration!"
-#endif
-#ifndef RTE_USART3_RX_PIN_EN
- #define RTE_USART3_RX_PIN_EN 1
-#endif
-// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
-// <i> USART3 Serial Clock input/output synchronous mode
-#define RTE_USART3_UCLK_ID 0
-#if (RTE_USART3_UCLK_ID == 0)
- #define RTE_USART3_UCLK_PIN_EN 0
-#elif (RTE_USART3_UCLK_ID == 1)
- #define RTE_USART3_UCLK_PORT 2
- #define RTE_USART3_UCLK_BIT 7
- #define RTE_USART3_UCLK_FUNC 2
-#elif (RTE_USART3_UCLK_ID == 2)
- #define RTE_USART3_UCLK_PORT 4
- #define RTE_USART3_UCLK_BIT 0
- #define RTE_USART3_UCLK_FUNC 6
-#elif (RTE_USART3_UCLK_ID == 3)
- #define RTE_USART3_UCLK_PORT 0xF
- #define RTE_USART3_UCLK_BIT 5
- #define RTE_USART3_UCLK_FUNC 1
-#else
- #error "Invalid USART3_UCLK Pin Configuration!"
-#endif
-#ifndef RTE_USART3_UCLK_PIN_EN
- #define RTE_USART3_UCLK_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14)
-// </e>
-#define RTE_USART3_DMA_TX_EN 0
-#define RTE_USART3_DMA_TX_CH 0
-#define RTE_USART3_DMA_TX_PERI_ID 0
-#if (RTE_USART3_DMA_TX_PERI_ID == 0)
- #define RTE_USART3_DMA_TX_PERI 7
- #define RTE_USART3_DMA_TX_PERI_SEL 1
-#elif (RTE_USART3_DMA_TX_PERI_ID == 1)
- #define RTE_USART3_DMA_TX_PERI 14
- #define RTE_USART3_DMA_TX_PERI_SEL 3
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13)
-// </e>
-#define RTE_USART3_DMA_RX_EN 0
-#define RTE_USART3_DMA_RX_CH 1
-#define RTE_USART3_DMA_RX_PERI_ID 0
-#if (RTE_USART3_DMA_RX_PERI_ID == 0)
- #define RTE_USART3_DMA_RX_PERI 8
- #define RTE_USART3_DMA_RX_PERI_SEL 1
-#elif (RTE_USART3_DMA_RX_PERI_ID == 1)
- #define RTE_USART3_DMA_RX_PERI 13
- #define RTE_USART3_DMA_RX_PERI_SEL 3
-#endif
-// </h> DMA
-// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
-
-// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
-// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
-#define RTE_SSP0 0
-
-// <h> Pin Configuration
-// <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
-// <i> Slave Select for SSP0
-#define RTE_SSP0_SSEL_PIN_SEL 1
-#if (RTE_SSP0_SSEL_PIN_SEL == 0)
-#define RTE_SSP0_SSEL_PIN_EN 0
-#elif (RTE_SSP0_SSEL_PIN_SEL == 1)
- #define RTE_SSP0_SSEL_PORT 1
- #define RTE_SSP0_SSEL_BIT 0
- #define RTE_SSP0_SSEL_FUNC 5
- #define RTE_SSP0_SSEL_GPIO_FUNC 0
- #define RTE_SSP0_SSEL_GPIO_PORT 0
- #define RTE_SSP0_SSEL_GPIO_BIT 4
-#elif (RTE_SSP0_SSEL_PIN_SEL == 2)
- #define RTE_SSP0_SSEL_PORT 3
- #define RTE_SSP0_SSEL_BIT 6
- #define RTE_SSP0_SSEL_FUNC 2
- #define RTE_SSP0_SSEL_GPIO_FUNC 0
- #define RTE_SSP0_SSEL_GPIO_PORT 0
- #define RTE_SSP0_SSEL_GPIO_BIT 6
-#elif (RTE_SSP0_SSEL_PIN_SEL == 3)
- #define RTE_SSP0_SSEL_PORT 3
- #define RTE_SSP0_SSEL_BIT 8
- #define RTE_SSP0_SSEL_FUNC 5
- #define RTE_SSP0_SSEL_GPIO_FUNC 4
- #define RTE_SSP0_SSEL_GPIO_PORT 5
- #define RTE_SSP0_SSEL_GPIO_BIT 11
-#elif (RTE_SSP0_SSEL_PIN_SEL == 4)
- #define RTE_SSP0_SSEL_PORT 9
- #define RTE_SSP0_SSEL_BIT 0
- #define RTE_SSP0_SSEL_FUNC 7
- #define RTE_SSP0_SSEL_GPIO_FUNC 0
- #define RTE_SSP0_SSEL_GPIO_PORT 4
- #define RTE_SSP0_SSEL_GPIO_BIT 12
-#elif (RTE_SSP0_SSEL_PIN_SEL == 5)
- #define RTE_SSP0_SSEL_PORT 0xF
- #define RTE_SSP0_SSEL_BIT 1
- #define RTE_SSP0_SSEL_FUNC 2
- #define RTE_SSP0_SSEL_GPIO_FUNC 4
- #define RTE_SSP0_SSEL_GPIO_PORT 7
- #define RTE_SSP0_SSEL_GPIO_BIT 16
-#else
- #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
-#endif
-#ifndef RTE_SSP0_SSEL_PIN_EN
-#define RTE_SSP0_SSEL_PIN_EN 1
-#endif
-// <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
-// <i> Serial clock for SSP0
-#define RTE_SSP0_SCK_PIN_SEL 0
-#if (RTE_SSP0_SCK_PIN_SEL == 0)
- #define RTE_SSP0_SCK_PORT 3
- #define RTE_SSP0_SCK_BIT 0
- #define RTE_SSP0_SCK_FUNC 4
-#elif (RTE_SSP0_SCK_PIN_SEL == 1)
- #define RTE_SSP0_SCK_PORT 3
- #define RTE_SSP0_SCK_BIT 3
- #define RTE_SSP0_SCK_FUNC 2
-#elif (RTE_SSP0_SCK_PIN_SEL == 2)
- #define RTE_SSP0_SCK_PORT 0xF
- #define RTE_SSP0_SCK_BIT 0
- #define RTE_SSP0_SCK_FUNC 0
-#else
- #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
-#endif
-// <o> SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2
-// <i> Master In Slave Out for SSP0
-#define RTE_SSP0_MISO_PIN_SEL 0
-#if (RTE_SSP0_MISO_PIN_SEL == 0)
- #define RTE_SSP0_MISO_PIN_EN 0
-#elif (RTE_SSP0_MISO_PIN_SEL == 1)
- #define RTE_SSP0_MISO_PORT 1
- #define RTE_SSP0_MISO_BIT 1
- #define RTE_SSP0_MISO_FUNC 5
-#elif (RTE_SSP0_MISO_PIN_SEL == 2)
- #define RTE_SSP0_MISO_PORT 3
- #define RTE_SSP0_MISO_BIT 6
- #define RTE_SSP0_MISO_FUNC 5
-#elif (RTE_SSP0_MISO_PIN_SEL == 3)
- #define RTE_SSP0_MISO_PORT 3
- #define RTE_SSP0_MISO_BIT 7
- #define RTE_SSP0_MISO_FUNC 2
-#elif (RTE_SSP0_MISO_PIN_SEL == 4)
- #define RTE_SSP0_MISO_PORT 9
- #define RTE_SSP0_MISO_BIT 1
- #define RTE_SSP0_MISO_FUNC 7
-#elif (RTE_SSP0_MISO_PIN_SEL == 5)
- #define RTE_SSP0_MISO_PORT 0xF
- #define RTE_SSP0_MISO_BIT 2
- #define RTE_SSP0_MISO_FUNC 2
-#else
- #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
-#endif
-#ifndef RTE_SSP0_MISO_PIN_EN
- #define RTE_SSP0_MISO_PIN_EN 1
-#endif
-// <o> SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3
-// <i> Master Out Slave In for SSP0
-#define RTE_SSP0_MOSI_PIN_SEL 0
-#if (RTE_SSP0_MOSI_PIN_SEL == 0)
- #define RTE_SSP0_MOSI_PIN_EN 0
-#elif (RTE_SSP0_MOSI_PIN_SEL == 1)
- #define RTE_SSP0_MOSI_PORT 1
- #define RTE_SSP0_MOSI_BIT 2
- #define RTE_SSP0_MOSI_FUNC 5
-#elif (RTE_SSP0_MOSI_PIN_SEL == 2)
- #define RTE_SSP0_MOSI_PORT 3
- #define RTE_SSP0_MOSI_BIT 7
- #define RTE_SSP0_MOSI_FUNC 5
-#elif (RTE_SSP0_MOSI_PIN_SEL == 3)
- #define RTE_SSP0_MOSI_PORT 3
- #define RTE_SSP0_MOSI_BIT 8
- #define RTE_SSP0_MOSI_FUNC 2
-#elif (RTE_SSP0_MOSI_PIN_SEL == 4)
- #define RTE_SSP0_MOSI_PORT 9
- #define RTE_SSP0_MOSI_BIT 2
- #define RTE_SSP0_MOSI_FUNC 7
-#elif (RTE_SSP0_MOSI_PIN_SEL == 5)
- #define RTE_SSP0_MOSI_PORT 0xF
- #define RTE_SSP0_MOSI_BIT 3
- #define RTE_SSP0_MOSI_FUNC 2
-#else
- #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
-#endif
-#ifndef RTE_SSP0_MOSI_PIN_EN
- #define RTE_SSP0_MOSI_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>10 (DMAMUXPER10)
-// </e>
-#define RTE_SSP0_DMA_TX_EN 0
-#define RTE_SSP0_DMA_TX_CH 0
-#define RTE_SSP0_DMA_TX_PERI_ID 0
-#if (RTE_SSP0_DMA_TX_PERI_ID == 0)
- #define RTE_SSP0_DMA_TX_PERI 10
- #define RTE_SSP0_DMA_TX_PERI_SEL 0
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>9 (DMAMUXPER9)
-// </e>
-#define RTE_SSP0_DMA_RX_EN 0
-#define RTE_SSP0_DMA_RX_CH 1
-#define RTE_SSP0_DMA_RX_PERI_ID 0
-#if (RTE_SSP0_DMA_RX_PERI_ID == 0)
- #define RTE_SSP0_DMA_RX_PERI 9
- #define RTE_SSP0_DMA_RX_PERI_SEL 0
-#endif
-// </h> DMA
-// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
-
-// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
-// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
-#define RTE_SSP1 0
-
-// <h> Pin Configuration
-// <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
-// <i> Slave Select for SSP1
-#define RTE_SSP1_SSEL_PIN_SEL 1
-#if (RTE_SSP1_SSEL_PIN_SEL == 0)
- #define RTE_SSP1_SSEL_PIN_EN 0
-#elif (RTE_SSP1_SSEL_PIN_SEL == 1)
- #define RTE_SSP1_SSEL_PORT 1
- #define RTE_SSP1_SSEL_BIT 5
- #define RTE_SSP1_SSEL_FUNC 5
- #define RTE_SSP1_SSEL_GPIO_FUNC 0
- #define RTE_SSP1_SSEL_GPIO_PORT 1
- #define RTE_SSP1_SSEL_GPIO_BIT 8
-#elif (RTE_SSP1_SSEL_PIN_SEL == 2)
- #define RTE_SSP1_SSEL_PORT 1
- #define RTE_SSP1_SSEL_BIT 20
- #define RTE_SSP1_SSEL_FUNC 1
- #define RTE_SSP1_SSEL_GPIO_FUNC 0
- #define RTE_SSP1_SSEL_GPIO_PORT 0
- #define RTE_SSP1_SSEL_GPIO_BIT 15
-#elif (RTE_SSP1_SSEL_PIN_SEL == 3)
- #define RTE_SSP1_SSEL_PORT 0xF
- #define RTE_SSP1_SSEL_BIT 5
- #define RTE_SSP1_SSEL_FUNC 2
- #define RTE_SSP1_SSEL_GPIO_FUNC 4
- #define RTE_SSP1_SSEL_GPIO_PORT 7
- #define RTE_SSP1_SSEL_GPIO_BIT 19
-#else
- #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
-#endif
-#ifndef RTE_SSP1_SSEL_PIN_EN
-#define RTE_SSP1_SSEL_PIN_EN 1
-#endif
-// <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
-// <i> Serial clock for SSP1
-#define RTE_SSP1_SCK_PIN_SEL 0
-#if (RTE_SSP1_SCK_PIN_SEL == 0)
- #define RTE_SSP1_SCK_PORT 1
- #define RTE_SSP1_SCK_BIT 19
- #define RTE_SSP1_SCK_FUNC 1
-#elif (RTE_SSP1_SCK_PIN_SEL == 1)
- #define RTE_SSP1_SCK_PORT 0xF
- #define RTE_SSP1_SCK_BIT 4
- #define RTE_SSP1_SCK_FUNC 0
-#elif (RTE_SSP1_SCK_PIN_SEL == 2)
- #define RTE_SSP1_SCK_PORT 0x10
- #define RTE_SSP1_SCK_BIT 0
- #define RTE_SSP1_SCK_FUNC 6
-#else
- #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
-#endif
-// <o> SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6
-// <i> Master In Slave Out for SSP1
-#define RTE_SSP1_MISO_PIN_SEL 0
-#if (RTE_SSP1_MISO_PIN_SEL == 0)
- #define RTE_SSP1_MISO_PIN_EN 0
-#elif (RTE_SSP1_MISO_PIN_SEL == 1)
- #define RTE_SSP1_MISO_PORT 0
- #define RTE_SSP1_MISO_BIT 0
- #define RTE_SSP1_MISO_FUNC 1
-#elif (RTE_SSP1_MISO_PIN_SEL == 2)
- #define RTE_SSP1_MISO_PORT 1
- #define RTE_SSP1_MISO_BIT 3
- #define RTE_SSP1_MISO_FUNC 5
-#elif (RTE_SSP1_MISO_PIN_SEL == 3)
- #define RTE_SSP1_MISO_PORT 0xF
- #define RTE_SSP1_MISO_BIT 6
- #define RTE_SSP1_MISO_FUNC 2
-#else
- #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
-#endif
-#ifndef RTE_SSP1_MISO_PIN_EN
- #define RTE_SSP1_MISO_PIN_EN 1
-#endif
-// <o> SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7
-// <i> Master Out Slave In for SSP1
-#define RTE_SSP1_MOSI_PIN_SEL 0
-#if (RTE_SSP1_MOSI_PIN_SEL == 0)
- #define RTE_SSP1_MOSI_PIN_EN 0
-#elif (RTE_SSP1_MOSI_PIN_SEL == 1)
- #define RTE_SSP1_MOSI_PORT 0
- #define RTE_SSP1_MOSI_BIT 1
- #define RTE_SSP1_MOSI_FUNC 1
-#elif (RTE_SSP1_MOSI_PIN_SEL == 2)
- #define RTE_SSP1_MOSI_PORT 1
- #define RTE_SSP1_MOSI_BIT 4
- #define RTE_SSP1_MOSI_FUNC 5
-#elif (RTE_SSP1_MOSI_PIN_SEL == 3)
- #define RTE_SSP1_MOSI_PORT 0xF
- #define RTE_SSP1_MOSI_BIT 7
- #define RTE_SSP1_MOSI_FUNC 2
-#else
- #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
-#endif
-#ifndef RTE_SSP1_MOSI_PIN_EN
- #define RTE_SSP1_MOSI_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
-// </e>
-#define RTE_SSP1_DMA_TX_EN 0
-#define RTE_SSP1_DMA_TX_CH 0
-#define RTE_SSP1_DMA_TX_PERI_ID 0
-#if (RTE_SSP1_DMA_TX_PERI_ID == 0)
- #define RTE_SSP1_DMA_TX_PERI 3
- #define RTE_SSP1_DMA_TX_PERI_SEL 3
-#elif (RTE_SSP1_DMA_TX_PERI_ID == 1)
- #define RTE_SSP1_DMA_TX_PERI 5
- #define RTE_SSP1_DMA_TX_PERI_SEL 2
-#elif (RTE_SSP1_DMA_TX_PERI_ID == 2)
- #define RTE_SSP1_DMA_TX_PERI 12
- #define RTE_SSP1_DMA_TX_PERI_SEL 0
-#elif (RTE_SSP1_DMA_TX_PERI_ID == 3)
- #define RTE_SSP1_DMA_TX_PERI 14
- #define RTE_SSP1_DMA_TX_PERI_SEL 2
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
-// </e>
-#define RTE_SSP1_DMA_RX_EN 0
-#define RTE_SSP1_DMA_RX_CH 1
-#define RTE_SSP1_DMA_RX_PERI_ID 0
-#if (RTE_SSP1_DMA_RX_PERI_ID == 0)
- #define RTE_SSP1_DMA_RX_PERI 4
- #define RTE_SSP1_DMA_RX_PERI_SEL 3
-#elif (RTE_SSP1_DMA_RX_PERI_ID == 1)
- #define RTE_SSP1_DMA_RX_PERI 6
- #define RTE_SSP1_DMA_RX_PERI_SEL 2
-#elif (RTE_SSP1_DMA_RX_PERI_ID == 2)
- #define RTE_SSP1_DMA_RX_PERI 11
- #define RTE_SSP1_DMA_RX_PERI_SEL 0
-#elif (RTE_SSP1_DMA_RX_PERI_ID == 3)
- #define RTE_SSP1_DMA_RX_PERI 13
- #define RTE_SSP1_DMA_RX_PERI_SEL 2
-#endif
-// </h> DMA
-// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
-
-// <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
-// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
-#define RTE_SPI 0
-
-// <h> Pin Configuration
-// <o> SPI_SSEL <0=>Not used <1=>P3_8
-// <i> Slave Select for SPI
-#define RTE_SPI_SSEL_PIN_SEL 0
-#if (RTE_SPI_SSEL_PIN_SEL == 0)
-#define RTE_SPI_SSEL_PIN_EN 0
-#elif (RTE_SPI_SSEL_PIN_SEL == 1)
- #define RTE_SPI_SSEL_PORT 3
- #define RTE_SPI_SSEL_BIT 8
- #define RTE_SPI_SSEL_FUNC 1
- #define RTE_SPI_SSEL_GPIO_FUNC 4
- #define RTE_SPI_SSEL_GPIO_PORT 5
- #define RTE_SPI_SSEL_GPIO_BIT 11
-#else
- #error "Invalid SPI SPI_SSEL Pin Configuration!"
-#endif
-#ifndef RTE_SPI_SSEL_PIN_EN
-#define RTE_SPI_SSEL_PIN_EN 1
-#endif
-// <o> SPI_SCK <0=>P3_3
-// <i> Serial clock for SPI
-#define RTE_SPI_SCK_PIN_SEL 0
-#if (RTE_SPI_SCK_PIN_SEL == 0)
- #define RTE_SPI_SCK_PORT 3
- #define RTE_SPI_SCK_BIT 3
- #define RTE_SPI_SCK_FUNC 1
-#else
- #error "Invalid SPI SPI_SCK Pin Configuration!"
-#endif
-// <o> SPI_MISO <0=>Not used <1=>P3_6
-// <i> Master In Slave Out for SPI
-#define RTE_SPI_MISO_PIN_SEL 0
-#if (RTE_SPI_MISO_PIN_SEL == 0)
- #define RTE_SPI_MISO_PIN_EN 0
-#elif (RTE_SPI_MISO_PIN_SEL == 1)
- #define RTE_SPI_MISO_PORT 3
- #define RTE_SPI_MISO_BIT 6
- #define RTE_SPI_MISO_FUNC 1
-#else
- #error "Invalid SPI SPI_MISO Pin Configuration!"
-#endif
-#ifndef RTE_SPI_MISO_PIN_EN
- #define RTE_SPI_MISO_PIN_EN 1
-#endif
-// <o> SPI_MOSI <0=>Not used <1=>P3_7
-// <i> Master Out Slave In for SPI
-#define RTE_SPI_MOSI_PIN_SEL 0
-#if (RTE_SPI_MOSI_PIN_SEL == 0)
- #define RTE_SPI_MOSI_PIN_EN 0
-#elif (RTE_SPI_MOSI_PIN_SEL == 1)
- #define RTE_SPI_MOSI_PORT 3
- #define RTE_SPI_MOSI_BIT 7
- #define RTE_SPI_MOSI_FUNC 1
-#else
- #error "Invalid SPI SPI_MOSI Pin Configuration!"
-#endif
-#ifndef RTE_SPI_MOSI_PIN_EN
- #define RTE_SPI_MOSI_PIN_EN 1
-#endif
-// </h> Pin Configuration
-// </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
-
-// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
-// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
-#define RTE_I2S0 0
-
-// <h> Pin Configuration
-// <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
-// <i> Receive clock for I2S0
-#define RTE_I2S0_RX_SCK_PIN_SEL 2
-#if (RTE_I2S0_RX_SCK_PIN_SEL == 0)
-#define RTE_I2S0_RX_SCK_PIN_EN 0
-#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1)
- #define RTE_I2S0_RX_SCK_PORT 3
- #define RTE_I2S0_RX_SCK_BIT 0
- #define RTE_I2S0_RX_SCK_FUNC 0
-#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2)
- #define RTE_I2S0_RX_SCK_PORT 6
- #define RTE_I2S0_RX_SCK_BIT 0
- #define RTE_I2S0_RX_SCK_FUNC 4
-#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3)
- #define RTE_I2S0_RX_SCK_PORT 0xF
- #define RTE_I2S0_RX_SCK_BIT 4
- #define RTE_I2S0_RX_SCK_FUNC 7
-#else
- #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_RX_SCK_PIN_EN
-#define RTE_I2S0_RX_SCK_PIN_EN 1
-#endif
-// <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
-// <i> Receive word select for I2S0
-#define RTE_I2S0_RX_WS_PIN_SEL 2
-#if (RTE_I2S0_RX_WS_PIN_SEL == 0)
-#define RTE_I2S0_RX_WS_PIN_EN 0
-#elif (RTE_I2S0_RX_WS_PIN_SEL == 1)
- #define RTE_I2S0_RX_WS_PORT 3
- #define RTE_I2S0_RX_WS_BIT 1
- #define RTE_I2S0_RX_WS_FUNC 1
-#elif (RTE_I2S0_RX_WS_PIN_SEL == 2)
- #define RTE_I2S0_RX_WS_PORT 6
- #define RTE_I2S0_RX_WS_BIT 1
- #define RTE_I2S0_RX_WS_FUNC 3
-#else
- #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_RX_WS_PIN_EN
-#define RTE_I2S0_RX_WS_PIN_EN 1
-#endif
-// <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
-// <i> Receive master clock for I2S0
-#define RTE_I2S0_RX_SDA_PIN_SEL 2
-#if (RTE_I2S0_RX_SDA_PIN_SEL == 0)
-#define RTE_I2S0_RX_SDA_PIN_EN 0
-#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1)
- #define RTE_I2S0_RX_SDA_PORT 3
- #define RTE_I2S0_RX_SDA_BIT 2
- #define RTE_I2S0_RX_SDA_FUNC 1
-#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2)
- #define RTE_I2S0_RX_SDA_PORT 6
- #define RTE_I2S0_RX_SDA_BIT 2
- #define RTE_I2S0_RX_SDA_FUNC 3
-#else
- #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_RX_SDA_PIN_EN
-#define RTE_I2S0_RX_SDA_PIN_EN 1
-#endif
-// <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
-// <i> Receive master clock for I2S0
-#define RTE_I2S0_RX_MCLK_PIN_SEL 0
-#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
-#define RTE_I2S0_RX_MCLK_PIN_EN 0
-#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
- #define RTE_I2S0_RX_MCLK_PORT 1
- #define RTE_I2S0_RX_MCLK_BIT 19
- #define RTE_I2S0_RX_MCLK_FUNC 6
-#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
- #define RTE_I2S0_RX_MCLK_PORT 3
- #define RTE_I2S0_RX_MCLK_BIT 0
- #define RTE_I2S0_RX_MCLK_FUNC 1
-#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
- #define RTE_I2S0_RX_MCLK_PORT 6
- #define RTE_I2S0_RX_MCLK_BIT 0
- #define RTE_I2S0_RX_MCLK_FUNC 1
-#else
- #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_RX_MCLK_PIN_EN
-#define RTE_I2S0_RX_MCLK_PIN_EN 1
-#endif
-// <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
-// <i> Transmit clock for I2S0
-#define RTE_I2S0_TX_SCK_PIN_SEL 1
-#if (RTE_I2S0_TX_SCK_PIN_SEL == 0)
-#define RTE_I2S0_TX_SCK_PIN_EN 0
-#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1)
- #define RTE_I2S0_TX_SCK_PORT 3
- #define RTE_I2S0_TX_SCK_BIT 0
- #define RTE_I2S0_TX_SCK_FUNC 2
-#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2)
- #define RTE_I2S0_TX_SCK_PORT 4
- #define RTE_I2S0_TX_SCK_BIT 7
- #define RTE_I2S0_TX_SCK_FUNC 7
-#else
- #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_TX_SCK_PIN_EN
-#define RTE_I2S0_TX_SCK_PIN_EN 1
-#endif
-// <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
-// <i> Transmit word select for I2S0
-#define RTE_I2S0_TX_WS_PIN_SEL 4
-#if (RTE_I2S0_TX_WS_PIN_SEL == 0)
-#define RTE_I2S0_TX_WS_PIN_EN 0
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 1)
- #define RTE_I2S0_TX_WS_PORT 0
- #define RTE_I2S0_TX_WS_BIT 0
- #define RTE_I2S0_TX_WS_FUNC 6
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 2)
- #define RTE_I2S0_TX_WS_PORT 3
- #define RTE_I2S0_TX_WS_BIT 1
- #define RTE_I2S0_TX_WS_FUNC 0
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 3)
- #define RTE_I2S0_TX_WS_PORT 3
- #define RTE_I2S0_TX_WS_BIT 4
- #define RTE_I2S0_TX_WS_FUNC 5
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 4)
- #define RTE_I2S0_TX_WS_PORT 7
- #define RTE_I2S0_TX_WS_BIT 1
- #define RTE_I2S0_TX_WS_FUNC 2
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 5)
- #define RTE_I2S0_TX_WS_PORT 9
- #define RTE_I2S0_TX_WS_BIT 1
- #define RTE_I2S0_TX_WS_FUNC 4
-#elif (RTE_I2S0_TX_WS_PIN_SEL == 6)
- #define RTE_I2S0_TX_WS_PORT 0xC
- #define RTE_I2S0_TX_WS_BIT 13
- #define RTE_I2S0_TX_WS_FUNC 6
-#else
- #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_TX_WS_PIN_EN
-#define RTE_I2S0_TX_WS_PIN_EN 1
-#endif
-// <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12
-// <i> Transmit data for I2S0
-#define RTE_I2S0_TX_SDA_PIN_SEL 3
-#if (RTE_I2S0_TX_SDA_PIN_SEL == 0)
-#define RTE_I2S0_TX_SDA_PIN_EN 0
-#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1)
- #define RTE_I2S0_TX_SDA_PORT 3
- #define RTE_I2S0_TX_SDA_BIT 2
- #define RTE_I2S0_TX_SDA_FUNC 0
-#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2)
- #define RTE_I2S0_TX_SDA_PORT 3
- #define RTE_I2S0_TX_SDA_BIT 5
- #define RTE_I2S0_TX_SDA_FUNC 5
-#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3)
- #define RTE_I2S0_TX_SDA_PORT 7
- #define RTE_I2S0_TX_SDA_BIT 2
- #define RTE_I2S0_TX_SDA_FUNC 2
-#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4)
- #define RTE_I2S0_TX_SDA_PORT 9
- #define RTE_I2S0_TX_SDA_BIT 2
- #define RTE_I2S0_TX_SDA_FUNC 4
-#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5)
- #define RTE_I2S0_TX_SDA_PORT 0xC
- #define RTE_I2S0_TX_SDA_BIT 12
- #define RTE_I2S0_TX_SDA_FUNC 6
-#else
- #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_TX_SDA_PIN_EN
-#define RTE_I2S0_TX_SDA_PIN_EN 1
-#endif
-// <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
-// <i> Transmit master clock for I2S0
-#define RTE_I2S0_TX_MCLK_PIN_SEL 2
-#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
-#define RTE_I2S0_TX_MCLK_PIN_EN 0
-#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
- #define RTE_I2S0_TX_MCLK_PORT 3
- #define RTE_I2S0_TX_MCLK_BIT 0
- #define RTE_I2S0_TX_MCLK_FUNC 3
-#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
- #define RTE_I2S0_TX_MCLK_PORT 3
- #define RTE_I2S0_TX_MCLK_BIT 3
- #define RTE_I2S0_TX_MCLK_FUNC 6
-#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
- #define RTE_I2S0_TX_MCLK_PORT 0xf
- #define RTE_I2S0_TX_MCLK_BIT 4
- #define RTE_I2S0_TX_MCLK_FUNC 6
-#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
- #define RTE_I2S0_TX_MCLK_PORT 0x10
- #define RTE_I2S0_TX_MCLK_BIT 2
- #define RTE_I2S0_TX_MCLK_FUNC 6
-#else
- #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
-#endif
-#ifndef RTE_I2S0_TX_MCLK_PIN_EN
-#define RTE_I2S0_TX_MCLK_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>9 (DMAMUXPER9)
-// </e>
-#define RTE_I2S0_DMA_TX_EN 0
-#define RTE_I2S0_DMA_TX_CH 0
-#define RTE_I2S0_DMA_TX_PERI_ID 0
-#if (RTE_I2S0_DMA_TX_PERI_ID == 0)
- #define RTE_I2S0_DMA_TX_PERI 9
- #define RTE_I2S0_DMA_TX_PERI_SEL 1
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>10 (DMAMUXPER10)
-// </e>
-#define RTE_I2S0_DMA_RX_EN 0
-#define RTE_I2S0_DMA_RX_CH 1
-#define RTE_I2S0_DMA_RX_PERI_ID 0
-#if (RTE_I2S0_DMA_RX_PERI_ID == 0)
- #define RTE_I2S0_DMA_RX_PERI 10
- #define RTE_I2S0_DMA_RX_PERI_SEL 1
-#endif
-// </h> DMA
-// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
-
-// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
-// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
-#define RTE_I2S1 0
-
-// <h> Pin Configuration
-// <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
-// <i> Receive clock for I2S1
-#define RTE_I2S1_RX_SCK_PIN_SEL 0
-#if (RTE_I2S1_RX_SCK_PIN_SEL == 0)
-#define RTE_I2S1_RX_SCK_PIN_EN 0
-#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1)
- #define RTE_I2S1_RX_SCK_PORT 0x10
- #define RTE_I2S1_RX_SCK_BIT 2
- #define RTE_I2S1_RX_SCK_FUNC 7
-#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2)
- #define RTE_I2S1_RX_SCK_PORT 0x10
- #define RTE_I2S1_RX_SCK_BIT 3
- #define RTE_I2S1_RX_SCK_FUNC 7
-#else
- #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_RX_SCK_PIN_EN
-#define RTE_I2S1_RX_SCK_PIN_EN 1
-#endif
-// <o> I2S1_RX_WS <0=>Not used <1=>P3_5
-// <i> Receive word select for I2S1
-#define RTE_I2S1_RX_WS_PIN_SEL 0
-#if (RTE_I2S1_RX_WS_PIN_SEL == 0)
-#define RTE_I2S1_RX_WS_PIN_EN 0
-#elif (RTE_I2S1_RX_WS_PIN_SEL == 1)
- #define RTE_I2S1_RX_WS_PORT 3
- #define RTE_I2S1_RX_WS_BIT 5
- #define RTE_I2S1_RX_WS_FUNC 6
-#else
- #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_RX_WS_PIN_EN
-#define RTE_I2S1_RX_WS_PIN_EN 1
-#endif
-// <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
-// <i> Receive master clock for I2S1
-#define RTE_I2S1_RX_SDA_PIN_SEL 0
-#if (RTE_I2S1_RX_SDA_PIN_SEL == 0)
-#define RTE_I2S1_RX_SDA_PIN_EN 0
-#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1)
- #define RTE_I2S1_RX_SDA_PORT 3
- #define RTE_I2S1_RX_SDA_BIT 4
- #define RTE_I2S1_RX_SDA_FUNC 6
-#else
- #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_RX_SDA_PIN_EN
-#define RTE_I2S1_RX_SDA_PIN_EN 1
-#endif
-// <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
-// <i> Receive master clock for I2S1
-#define RTE_I2S1_RX_MCLK_PIN_SEL 0
-#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
-#define RTE_I2S1_RX_MCLK_PIN_EN 0
-#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
- #define RTE_I2S1_RX_MCLK_PORT 0x0A
- #define RTE_I2S1_RX_MCLK_BIT 0
- #define RTE_I2S1_RX_MCLK_FUNC 5
-#else
- #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_RX_MCLK_PIN_EN
-#define RTE_I2S1_RX_MCLK_PIN_EN 1
-#endif
-// <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
-// <i> Transmit clock for I2S1
-#define RTE_I2S1_TX_SCK_PIN_SEL 0
-#if (RTE_I2S1_TX_SCK_PIN_SEL == 0)
-#define RTE_I2S1_TX_SCK_PIN_EN 0
-#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1)
- #define RTE_I2S1_TX_SCK_PORT 1
- #define RTE_I2S1_TX_SCK_BIT 19
- #define RTE_I2S1_TX_SCK_FUNC 7
-#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2)
- #define RTE_I2S1_TX_SCK_PORT 3
- #define RTE_I2S1_TX_SCK_BIT 3
- #define RTE_I2S1_TX_SCK_FUNC 7
-#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3)
- #define RTE_I2S1_TX_SCK_PORT 4
- #define RTE_I2S1_TX_SCK_BIT 7
- #define RTE_I2S1_TX_SCK_FUNC 6
-#else
- #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_TX_SCK_PIN_EN
-#define RTE_I2S1_TX_SCK_PIN_EN 1
-#endif
-// <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
-// <i> Transmit word select for I2S1
-#define RTE_I2S1_TX_WS_PIN_SEL 0
-#if (RTE_I2S1_TX_WS_PIN_SEL == 0)
-#define RTE_I2S1_TX_WS_PIN_EN 0
-#elif (RTE_I2S1_TX_WS_PIN_SEL == 1)
- #define RTE_I2S1_TX_WS_PORT 0
- #define RTE_I2S1_TX_WS_BIT 0
- #define RTE_I2S1_TX_WS_FUNC 7
-#elif (RTE_I2S1_TX_WS_PIN_SEL == 2)
- #define RTE_I2S1_TX_WS_PORT 0x0F
- #define RTE_I2S1_TX_WS_BIT 7
- #define RTE_I2S1_TX_WS_FUNC 7
-#else
- #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_TX_WS_PIN_EN
-#define RTE_I2S1_TX_WS_PIN_EN 1
-#endif
-// <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
-// <i> Transmit data for I2S
-#define RTE_I2S1_TX_SDA_PIN_SEL 0
-#if (RTE_I2S1_TX_SDA_PIN_SEL == 0)
-#define RTE_I2S1_TX_SDA_PIN_EN 0
-#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1)
- #define RTE_I2S1_TX_SDA_PORT 0
- #define RTE_I2S1_TX_SDA_BIT 1
- #define RTE_I2S1_TX_SDA_FUNC 7
-#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2)
- #define RTE_I2S1_TX_SDA_PORT 0x0F
- #define RTE_I2S1_TX_SDA_BIT 6
- #define RTE_I2S1_TX_SDA_FUNC 7
-#else
- #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_TX_SDA_PIN_EN
-#define RTE_I2S1_TX_SDA_PIN_EN 1
-#endif
-// <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
-// <i> Transmit master clock for I2S1
-#define RTE_I2S1_TX_MCLK_PIN_SEL 0
-#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
-#define RTE_I2S1_TX_MCLK_PIN_EN 0
-#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
- #define RTE_I2S1_TX_MCLK_PORT 8
- #define RTE_I2S1_TX_MCLK_BIT 8
- #define RTE_I2S1_TX_MCLK_FUNC 7
-#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
- #define RTE_I2S1_TX_MCLK_PORT 0x0F
- #define RTE_I2S1_TX_MCLK_BIT 0
- #define RTE_I2S1_TX_MCLK_FUNC 7
-#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
- #define RTE_I2S1_TX_MCLK_PORT 0x10
- #define RTE_I2S1_TX_MCLK_BIT 1
- #define RTE_I2S1_TX_MCLK_FUNC 7
-#else
- #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
-#endif
-#ifndef RTE_I2S1_TX_MCLK_PIN_EN
-#define RTE_I2S1_TX_MCLK_PIN_EN 1
-#endif
-// </h> Pin Configuration
-
-// <h> DMA
-// <e> Tx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>3 (DMAMUXPER3)
-// </e>
-#define RTE_I2S1_DMA_TX_EN 0
-#define RTE_I2S1_DMA_TX_CH 0
-#define RTE_I2S1_DMA_TX_PERI_ID 0
-#if (RTE_I2S1_DMA_TX_PERI_ID == 0)
- #define RTE_I2S1_DMA_TX_PERI 3
- #define RTE_I2S1_DMA_TX_PERI_SEL 2
-#endif
-// <e> Rx
-// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <o2> Peripheral <0=>4 (DMAMUXPER4)
-// </e>
-#define RTE_I2S1_DMA_RX_EN 0
-#define RTE_I2S1_DMA_RX_CH 1
-#define RTE_I2S1_DMA_RX_PERI_ID 0
-#if (RTE_I2S1_DMA_RX_PERI_ID == 0)
- #define RTE_I2S1_DMA_RX_PERI 4
- #define RTE_I2S1_DMA_RX_PERI_SEL 2
-#endif
-// </h> DMA
-// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
-
-// <e> CAN0 Controller [Driver_CAN0]
-// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
-#define RTE_CAN_CAN0 0
-
-// <h> Pin Configuration
-// <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
-// <i> CAN0 receiver input.
-#define RTE_CAN0_RD_ID 0
-#if (RTE_CAN0_RD_ID == 0)
- #define RTE_CAN0_RD_PIN_EN 0
-#elif (RTE_CAN0_RD_ID == 1)
- #define RTE_CAN0_RD_PORT 3
- #define RTE_CAN0_RD_BIT 1
- #define RTE_CAN0_RD_FUNC 2
-#elif (RTE_CAN0_RD_ID == 2)
- #define RTE_CAN0_RD_PORT 0xE
- #define RTE_CAN0_RD_BIT 2
- #define RTE_CAN0_RD_FUNC 1
-#else
- #error "Invalid RTE_CAN0_RD Pin Configuration!"
-#endif
-#ifndef RTE_CAN0_RD_PIN_EN
- #define RTE_CAN0_RD_PIN_EN 1
-#endif
-// <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
-// <i> CAN0 transmitter output.
-#define RTE_CAN0_TD_ID 0
-#if (RTE_CAN0_TD_ID == 0)
- #define RTE_CAN0_TD_PIN_EN 0
-#elif (RTE_CAN0_TD_ID == 1)
- #define RTE_CAN0_TD_PORT 3
- #define RTE_CAN0_TD_BIT 2
- #define RTE_CAN0_TD_FUNC 2
-#elif (RTE_CAN0_TD_ID == 2)
- #define RTE_CAN0_TD_PORT 0xE
- #define RTE_CAN0_TD_BIT 3
- #define RTE_CAN0_TD_FUNC 1
-#else
- #error "Invalid RTE_CAN0_TD Pin Configuration!"
-#endif
-#ifndef RTE_CAN0_TD_PIN_EN
- #define RTE_CAN0_TD_PIN_EN 1
-#endif
-// </h> Pin Configuration
-// </e> CAN0 Controller [Driver_CAN0]
-
-// <e> CAN1 Controller [Driver_CAN1]
-// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
-#define RTE_CAN_CAN1 0
-
-// <h> Pin Configuration
-// <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
-// <i> CAN1 receiver input.
-#define RTE_CAN1_RD_ID 0
-#if (RTE_CAN1_RD_ID == 0)
- #define RTE_CAN1_RD_PIN_EN 0
-#elif (RTE_CAN1_RD_ID == 1)
- #define RTE_CAN1_RD_PORT 1
- #define RTE_CAN1_RD_BIT 18
- #define RTE_CAN1_RD_FUNC 5
-#elif (RTE_CAN1_RD_ID == 2)
- #define RTE_CAN1_RD_PORT 4
- #define RTE_CAN1_RD_BIT 9
- #define RTE_CAN1_RD_FUNC 6
-#elif (RTE_CAN1_RD_ID == 3)
- #define RTE_CAN1_RD_PORT 0xE
- #define RTE_CAN1_RD_BIT 1
- #define RTE_CAN1_RD_FUNC 5
-#else
- #error "Invalid RTE_CAN1_RD Pin Configuration!"
-#endif
-#ifndef RTE_CAN1_RD_PIN_EN
- #define RTE_CAN1_RD_PIN_EN 1
-#endif
-// <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
-// <i> CAN1 transmitter output.
-#define RTE_CAN1_TD_ID 0
-#if (RTE_CAN1_TD_ID == 0)
- #define RTE_CAN1_TD_PIN_EN 0
-#elif (RTE_CAN1_TD_ID == 1)
- #define RTE_CAN1_TD_PORT 1
- #define RTE_CAN1_TD_BIT 17
- #define RTE_CAN1_TD_FUNC 5
-#elif (RTE_CAN1_TD_ID == 2)
- #define RTE_CAN1_TD_PORT 4
- #define RTE_CAN1_TD_BIT 8
- #define RTE_CAN1_TD_FUNC 6
-#elif (RTE_CAN1_TD_ID == 3)
- #define RTE_CAN1_TD_PORT 0xE
- #define RTE_CAN1_TD_BIT 0
- #define RTE_CAN1_TD_FUNC 5
-#else
- #error "Invalid RTE_CAN1_TD Pin Configuration!"
-#endif
-#ifndef RTE_CAN1_TD_PIN_EN
- #define RTE_CAN1_TD_PIN_EN 1
-#endif
-// </h> Pin Configuration
-// </e> CAN1 Controller [Driver_CAN1]
-
-
-#endif /* __RTE_DEVICE_H */
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s
deleted file mode 100644
index 19eac6d..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s
+++ /dev/null
@@ -1,333 +0,0 @@
-;/**************************************************************************//**
-; * @file LPC43xx.s
-; * @brief CMSIS Cortex-M4 Core Device Startup File for
-; * NXP LPC43xxDevice Series
-; * @version V1.00
-; * @date 03. September 2013
-; *
-; * @note
-; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
-; *
-; * @par
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M
-; * processor based microcontrollers. This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * @par
-; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; * <<< Use Configuration Wizard in Context Menu >>>
-; ******************************************************************************/
-
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
-
-Sign_Value EQU 0x5A5A5A5A
-
-__Vectors DCD __initial_sp ; 0 Top of Stack
- DCD Reset_Handler ; 1 Reset Handler
- DCD NMI_Handler ; 2 NMI Handler
- DCD HardFault_Handler ; 3 Hard Fault Handler
- DCD MemManage_Handler ; 4 MPU Fault Handler
- DCD BusFault_Handler ; 5 Bus Fault Handler
- DCD UsageFault_Handler ; 6 Usage Fault Handler
- DCD Sign_Value ; 7 Reserved
- DCD 0 ; 8 Reserved
- DCD 0 ; 9 Reserved
- DCD 0 ; 10 Reserved
- DCD SVC_Handler ; 11 SVCall Handler
- DCD DebugMon_Handler ; 12 Debug Monitor Handler
- DCD 0 ; 13 Reserved
- DCD PendSV_Handler ; 14 PendSV Handler
- DCD SysTick_Handler ; 15 SysTick Handler
-
- ; External LPC43xx/M4 Interrupts
- DCD DAC_IRQHandler ; 0 DAC interrupt
- DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
- DCD DMA_IRQHandler ; 2 DMA interrupt
- DCD 0 ; 3 Reserved
- DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
- DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
- DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
- DCD LCD_IRQHandler ; 7 LCD interrupt
- DCD USB0_IRQHandler ; 8 OTG interrupt
- DCD USB1_IRQHandler ; 9 USB1 interrupt
- DCD SCT_IRQHandler ; 10 SCT combined interrupt
- DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
- DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
- DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
- DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
- DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
- DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
- DCD ADC0_IRQHandler ; 17 ADC0 interrupt
- DCD I2C0_IRQHandler ; 18 I2C0 interrupt
- DCD I2C1_IRQHandler ; 19 I2C1 interrupt
- DCD SPI_IRQHandler ; 20 SPI interrupt
- DCD ADC1_IRQHandler ; 21 ADC1 interrupt
- DCD SSP0_IRQHandler ; 22 SSP0 interrupt
- DCD SSP1_IRQHandler ; 23 SSP1 interrupt
- DCD USART0_IRQHandler ; 24 USART0 interrupt
- DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
- DCD USART2_IRQHandler ; 26 USART2 interrupt
- DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
- DCD I2S0_IRQHandler ; 28 I2S0 interrupt
- DCD I2S1_IRQHandler ; 29 I2S1 interrupt
- DCD SPIFI_IRQHandler ; 30 SPISI interrupt
- DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
- DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
- DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
- DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
- DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
- DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
- DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
- DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
- DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
- DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
- DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
- DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
- DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
- DCD 0 ; 44 Reserved
- DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
- DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
- DCD RTC_IRQHandler ; 47 RTC interrupt
- DCD 0 ; 48 Reserved
- DCD WWDT_IRQHandler ; 49 WWDT interrupt
- DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
- DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
- DCD QEI_IRQHandler ; 52 QEI interrupt
-
-
-;CRP address at offset 0x2FC relative to the BOOT Bank address
- IF :LNOT::DEF:NO_CRP
- SPACE (0x2FC - (. - __Vectors))
-; EXPORT CRP_Key
-CRP_Key DCD 0xFFFFFFFF
-; 0xFFFFFFFF => CRP Disabled
-; 0x12345678 => CRP Level 1
-; 0x87654321 => CRP Level 2
-; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
-; 0x4E697370 => NO ISP (ARE YOU SURE?)
- ENDIF
-
- AREA |.text|, CODE, READONLY
-
-; Reset Handler
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT DAC_IRQHandler [WEAK]
- EXPORT M0APP_IRQHandler [WEAK]
- EXPORT DMA_IRQHandler [WEAK]
- EXPORT FLASHEEPROM_IRQHandler [WEAK]
- EXPORT ETHERNET_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT LCD_IRQHandler [WEAK]
- EXPORT USB0_IRQHandler [WEAK]
- EXPORT USB1_IRQHandler [WEAK]
- EXPORT SCT_IRQHandler [WEAK]
- EXPORT RITIMER_IRQHandler [WEAK]
- EXPORT TIMER0_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT TIMER3_IRQHandler [WEAK]
- EXPORT MCPWM_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT SSP0_IRQHandler [WEAK]
- EXPORT SSP1_IRQHandler [WEAK]
- EXPORT USART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT I2S0_IRQHandler [WEAK]
- EXPORT I2S1_IRQHandler [WEAK]
- EXPORT SPIFI_IRQHandler [WEAK]
- EXPORT SGPIO_IRQHandler [WEAK]
- EXPORT PIN_INT0_IRQHandler [WEAK]
- EXPORT PIN_INT1_IRQHandler [WEAK]
- EXPORT PIN_INT2_IRQHandler [WEAK]
- EXPORT PIN_INT3_IRQHandler [WEAK]
- EXPORT PIN_INT4_IRQHandler [WEAK]
- EXPORT PIN_INT5_IRQHandler [WEAK]
- EXPORT PIN_INT6_IRQHandler [WEAK]
- EXPORT PIN_INT7_IRQHandler [WEAK]
- EXPORT GINT0_IRQHandler [WEAK]
- EXPORT GINT1_IRQHandler [WEAK]
- EXPORT EVENTROUTER_IRQHandler [WEAK]
- EXPORT C_CAN1_IRQHandler [WEAK]
- EXPORT ADCHS_IRQHandler [WEAK]
- EXPORT ATIMER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT WWDT_IRQHandler [WEAK]
- EXPORT M0SUB_IRQHandler [WEAK]
- EXPORT C_CAN0_IRQHandler [WEAK]
- EXPORT QEI_IRQHandler [WEAK]
-
-DAC_IRQHandler
-M0APP_IRQHandler
-DMA_IRQHandler
-FLASHEEPROM_IRQHandler
-ETHERNET_IRQHandler
-SDIO_IRQHandler
-LCD_IRQHandler
-USB0_IRQHandler
-USB1_IRQHandler
-SCT_IRQHandler
-RITIMER_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-MCPWM_IRQHandler
-ADC0_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI_IRQHandler
-ADC1_IRQHandler
-SSP0_IRQHandler
-SSP1_IRQHandler
-USART0_IRQHandler
-UART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-SPIFI_IRQHandler
-SGPIO_IRQHandler
-PIN_INT0_IRQHandler
-PIN_INT1_IRQHandler
-PIN_INT2_IRQHandler
-PIN_INT3_IRQHandler
-PIN_INT4_IRQHandler
-PIN_INT5_IRQHandler
-PIN_INT6_IRQHandler
-PIN_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-EVENTROUTER_IRQHandler
-C_CAN1_IRQHandler
-ADCHS_IRQHandler
-ATIMER_IRQHandler
-RTC_IRQHandler
-WWDT_IRQHandler
-M0SUB_IRQHandler
-C_CAN0_IRQHandler
-QEI_IRQHandler
-
- B .
- ENDP
-
- ALIGN
-
-; User Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
-
- END
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c
deleted file mode 100644
index 5c46381..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c
+++ /dev/null
@@ -1,938 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013 - 2017 ARM Ltd.
- *
- * This software is provided 'as-is', without any express or implied warranty.
- * In no event will the authors be held liable for any damages arising from
- * the use of this software. Permission is granted to anyone to use this
- * software for any purpose, including commercial applications, and to alter
- * it and redistribute it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software. If you use this software in
- * a product, an acknowledgment in the product documentation would be
- * appreciated but is not required.
- *
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- *
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * $Date: 10. September 2018
- * $Revision: V1.0.3
- *
- * Project: NXP LPC43xx System initialization
- * -------------------------------------------------------------------------- */
-
-#include "LPC43xx.h"
-
-/*----------------------------------------------------------------------------
- This file configures the clocks as follows:
- -----------------------------------------------------------------------------
- Clock Unit | Output clock | Source clock | Note
- -----------------------------------------------------------------------------
- PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
- -----------------------------------------------------------------------------
- PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
- -----------------------------------------------------------------------------
- CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
- -----------------------------------------------------------------------------
- IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
- -----------------------------------------------------------------------------
- IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
- -----------------------------------------------------------------------------
- IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
- -----------------------------------------------------------------------------
- IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
- -----------------------------------------------------------------------------
- IDIV E | 5.3 MHz | PLL1 | To the LCD controller
- -----------------------------------------------------------------------------*/
-
-
-/*----------------------------------------------------------------------------
- Clock source selection definitions (do not change)
- *----------------------------------------------------------------------------*/
-#define CLK_SRC_32KHZ 0x00
-#define CLK_SRC_IRC 0x01
-#define CLK_SRC_ENET_RX 0x02
-#define CLK_SRC_ENET_TX 0x03
-#define CLK_SRC_GP_CLKIN 0x04
-#define CLK_SRC_XTAL 0x06
-#define CLK_SRC_PLL0U 0x07
-#define CLK_SRC_PLL0A 0x08
-#define CLK_SRC_PLL1 0x09
-#define CLK_SRC_IDIVA 0x0C
-#define CLK_SRC_IDIVB 0x0D
-#define CLK_SRC_IDIVC 0x0E
-#define CLK_SRC_IDIVD 0x0F
-#define CLK_SRC_IDIVE 0x10
-
-
-/*----------------------------------------------------------------------------
- Define external input frequency values
- *----------------------------------------------------------------------------*/
-#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
-#define CLK_IRC 12000000UL /* Internal oscillator frequency */
-#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
-#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
-#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
-#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
-
-
-/*----------------------------------------------------------------------------
- Define clock sources
- *----------------------------------------------------------------------------*/
-#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
-#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
-#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
-#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
-#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
-#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
-#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
-
-
-/*----------------------------------------------------------------------------
- Configure integer divider values
- *----------------------------------------------------------------------------*/
-#define IDIVA_IDIV 2 /* Divide input clock by 3 */
-#define IDIVB_IDIV 1 /* Divide input clock by 2 */
-#define IDIVC_IDIV 0 /* Divide input clock by 1 */
-#define IDIVD_IDIV 0 /* Divide input clock by 1 */
-#define IDIVE_IDIV 33 /* Divide input clock by 34 */
-
-
-/*----------------------------------------------------------------------------
- Define CPU clock input
- *----------------------------------------------------------------------------*/
-#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
-
-
-/*----------------------------------------------------------------------------
- Configure external memory controller options
- *----------------------------------------------------------------------------*/
-#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
-#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
-
-
-/*----------------------------------------------------------------------------
- * Configure PLL1
- *----------------------------------------------------------------------------
- * Integer mode:
- * - PLL1_DIRECT = 0 (Post divider enabled)
- * - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
- * - Output frequency:
- * FCLKOUT = (FCLKIN / N) * M
- * FCCO = FCLKOUT * 2 * P
- *
- * Non-integer:
- * - PLL1_DIRECT = 0 (Post divider enabled)
- * - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
- * - Output frequency:
- * FCLKOUT = (FCLKIN / N) * M / (2 * P)
- * FCCO = FCLKOUT * 2 * P
- *
- * Direct mode:
- * - PLL1_DIRECT = 1 (Post divider disabled)
- * - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
- * - Output frequency:
- * FCLKOUT = (FCLKIN / N) * M
- * FCCO = FCLKOUT
- *
- *----------------------------------------------------------------------------
- * PLL1 requirements:
- * | Frequency | Minimum | Maximum | Note |
- * | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
- * | FCLKIN | 1MHz | 50MHz | |
- * | FCCO | 156MHz | 320MHz | |
- * | FCLKOUT | 9.75MHz | 320MHz | |
- *----------------------------------------------------------------------------
- * Configuration examples:
- * | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
- * | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
- * | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
- * | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
- * | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
- * | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
- * | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
- * | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
- *----------------------------------------------------------------------------
- * Relations beetwen PLL dividers and definitions:
- * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
- *----------------------------------------------------------------------------*/
-
-/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
-#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
-#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
-#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
-
-#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
-#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
-#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
- /* 1: FCLKOUT is used as PLL feedback */
-
-/*----------------------------------------------------------------------------
- * Configure Flash Accelerator
- *----------------------------------------------------------------------------
- * Flash acces time:
- * | CPU clock | FLASHTIM |
- * | up to 21MHz | 0 |
- * | up to 43MHz | 1 |
- * | up to 64MHz | 2 |
- * | up to 86MHz | 3 |
- * | up to 107MHz | 4 |
- * | up to 129MHz | 5 |
- * | up to 150MHz | 6 |
- * | up to 172MHz | 7 |
- * | up to 193MHz | 8 |
- * | up to 204MHz | 9 |
- *----------------------------------------------------------------------------*/
-#define FLASHCFG_FLASHTIM 9
-
-
-/*----------------------------------------------------------------------------
- * Configure PLL0USB
- *----------------------------------------------------------------------------
- *
- * Normal operating mode without post-divider and without pre-divider
- * - PLL0USB_DIRECTI = 1
- * - PLL0USB_DIRECTO = 1
- * - PLL0USB_BYPASS = 0
- * - Output frequency:
- * FOUT = FIN * 2 * M
- * FCCO = FOUT
- *
- * Normal operating mode with post-divider and without pre-divider
- * - PLL0USB_DIRECTI = 1
- * - PLL0USB_DIRECTO = 0
- * - PLL0USB_BYPASS = 0
- * - Output frequency:
- * FOUT = FIN * (M / P)
- * FCCO = FOUT * 2 * P
- *
- * Normal operating mode without post-divider and with pre-divider
- * - PLL0USB_DIRECTI = 0
- * - PLL0USB_DIRECTO = 1
- * - PLL0USB_BYPASS = 0
- * - Output frequency:
- * FOUT = FIN * 2 * M / N
- * FCCO = FOUT
- *
- * Normal operating mode with post-divider and with pre-divider
- * - PLL0USB_DIRECTI = 0
- * - PLL0USB_DIRECTO = 0
- * - PLL0USB_BYPASS = 0
- * - Output frequency:
- * FOUT = FIN * M / (P * N)
- * FCCO = FOUT * 2 * P
- *----------------------------------------------------------------------------
- * PLL0 requirements:
- * | Frequency | Minimum | Maximum | Note |
- * | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
- * | FCLKIN | 14kHz | 150MHz | |
- * | FCCO | 275MHz | 550MHz | |
- * | FCLKOUT | 4.3MHz | 550MHz | |
- *----------------------------------------------------------------------------
- * Configuration examples:
- * | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
- * | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
- * | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
- *----------------------------------------------------------------------------*/
-
-/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
-#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
-#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
-#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
-
-#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
-#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
-#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
-
-
-/*----------------------------------------------------------------------------
- End of configuration
- *----------------------------------------------------------------------------*/
-
-/* PLL0 Setting Check */
-#if (PLL0USB_BYPASS == 0)
- #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
- #define PLL0USB_CLKIN CLK_XTAL
- #else
- #define PLL0USB_CLKIN CLK_IRC
- #endif
-
- #if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
- #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
- #define PLL0USB_FCCO (PLL0USB_FOUT)
- #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
- #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
- #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
- #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
- #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
- #define PLL0USB_FCCO (PLL0USB_FOUT)
- #else /* Mode 1d */
- #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
- #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
- #endif
-
- #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
- #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
- #endif
- #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
- #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
- #endif
-#endif
-
-/* PLL1 Setting Check */
-#if (PLL1_BYPASS == 0)
- #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
- #define PLL1_CLKIN CLK_XTAL
- #else
- #define PLL1_CLKIN CLK_IRC
- #endif
-
- #if (PLL1_DIRECT == 1) /* Direct Mode */
- #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #elif (PLL1_FBSEL == 1) /* Integer Mode */
- #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #else /* Noninteger Mode */
- #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
- #endif
- #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
- #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
- #endif
- #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
- #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
- #endif
-#endif
-
-
-/*----------------------------------------------------------------------------
- System Core Clock variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
-
-
-/******************************************************************************
- * SetClock
- ******************************************************************************/
-void SetClock (void) {
- uint32_t x, i;
- uint32_t selp, seli;
-
-
- /* Set flash accelerator configuration for bank A and B to reset value */
- LPC_CREG->FLASHCFGA |= (0xF << 12);
- LPC_CREG->FLASHCFGB |= (0xF << 12);
-
- /* Set flash wait states to maximum */
- LPC_EMC->STATICWAITRD0 = 0x1F;
-
- /* Switch BASE_M4_CLOCK to IRC */
- LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
- (CLK_SRC_IRC << 24) ; /* Set clock source */
-
- /* Configure input to crystal oscilator */
- LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
- (0 << 1) | /* Operation with crystal connected */
- (0 << 2) ; /* Low-frequency mode */
-
- /* Wait ~250us @ 12MHz */
- for (i = 1500; i; i--);
-
-#if (USE_SPIFI)
-/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
- LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
- (0 << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (CLK_SRC_IRC << 24) ; /* Clock source */
-
- LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
- (0 << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (CLK_SRC_IDIVA << 24) ; /* Clock source */
-#endif
-
-/*----------------------------------------------------------------------------
- PLL1 Setup
- *----------------------------------------------------------------------------*/
- /* Power down PLL */
- LPC_CGU->PLL1_CTRL |= 1;
-
-#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
- /* To run at full speed, CPU must first run at an intermediate speed */
- LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
- (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
- (PLL1_FBSEL << 6) | /* PLL output used as feedback */
- (0 << 7) | /* Direct on/off */
- (PLL1_PSEL << 8) | /* PSEL */
- (0 << 11)| /* Autoblock Disabled */
- (PLL1_NSEL << 12)| /* NSEL */
- (PLL1_MSEL << 16)| /* MSEL */
- (PLL1_CLK_SEL << 24); /* Clock source */
- /* Wait for lock */
- while (!(LPC_CGU->PLL1_STAT & 1));
-
- /* CPU base clock is in the mid frequency range before final clock set */
- LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
- (0x09 << 24) ; /* Clock source: PLL1 */
-
- /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
- for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
-#endif
- /* Configure PLL1 */
- LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
- (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
- (PLL1_FBSEL << 6) | /* PLL output used as feedback */
- (PLL1_DIRECT << 7) | /* Direct on/off */
- (PLL1_PSEL << 8) | /* PSEL */
- (1 << 11)| /* Autoblock En */
- (PLL1_NSEL << 12)| /* NSEL */
- (PLL1_MSEL << 16)| /* MSEL */
- (PLL1_CLK_SEL << 24); /* Clock source */
-
- /* Wait for lock */
- while (!(LPC_CGU->PLL1_STAT & 1));
-
- /* Set CPU base clock source */
- LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
- (CPU_CLK_SEL << 24) ; /* Set clock source */
-
- /* Set flash accelerator configuration for internal flash bank A and B */
- LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
- LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
-
-/*----------------------------------------------------------------------------
- PLL0USB Setup
- *----------------------------------------------------------------------------*/
-
- /* Power down PLL0USB */
- LPC_CGU->PLL0USB_CTRL |= 1;
-
- /* M divider */
- x = 0x00004000;
- switch (PLL0USB_M) {
- case 0: x = 0xFFFFFFFF;
- break;
- case 1: x = 0x00018003;
- break;
- case 2: x = 0x00010003;
- break;
- default:
- for (i = PLL0USB_M; i <= 0x8000; i++) {
- x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
- }
- }
-
- if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
- else selp = 31;
-
- if (PLL0USB_M > 16384) seli = 1;
- else if (PLL0USB_M > 8192) seli = 2;
- else if (PLL0USB_M > 2048) seli = 4;
- else if (PLL0USB_M >= 501) seli = 8;
- else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
- else seli = (PLL0USB_M & 0x3C) + 4;
- LPC_CGU->PLL0USB_MDIV = (selp << 17) |
- (seli << 22) |
- (x << 0);
-
- /* N divider */
- x = 0x80;
- switch (PLL0USB_N) {
- case 0: x = 0xFFFFFFFF;
- break;
- case 1: x = 0x00000302;
- break;
- case 2: x = 0x00000202;
- break;
- default:
- for (i = PLL0USB_N; i <= 0x0100; i++) {
- x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
- }
- }
- LPC_CGU->PLL0USB_NP_DIV = (x << 12);
-
- /* P divider */
- x = 0x10;
- switch (PLL0USB_P) {
- case 0: x = 0xFFFFFFFF;
- break;
- case 1: x = 0x00000062;
- break;
- case 2: x = 0x00000042;
- break;
- default:
- for (i = PLL0USB_P; i <= 0x200; i++) {
- x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
- }
- }
- LPC_CGU->PLL0USB_NP_DIV |= x;
-
- LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
- (1 << 11) | /* Autoblock En */
- (1 << 4 ) | /* PLL0USB clock en */
- (PLL0USB_DIRECTO << 3 ) | /* Direct output */
- (PLL0USB_DIRECTI << 2 ) | /* Direct input */
- (PLL0USB_BYPASS << 1 ) | /* PLL bypass */
- (0 << 0 ) ; /* PLL0USB Enabled */
- while (!(LPC_CGU->PLL0USB_STAT & 1));
-
-
-/*----------------------------------------------------------------------------
- Integer divider Setup
- *----------------------------------------------------------------------------*/
-
- /* Configure integer dividers */
- LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
- (IDIVA_IDIV << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (IDIVA_CLK_SEL << 24) ; /* Clock source */
-
- LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
- (IDIVB_IDIV << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (IDIVB_CLK_SEL << 24) ; /* Clock source */
-
- LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
- (IDIVC_IDIV << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (IDIVC_CLK_SEL << 24) ; /* Clock source */
-
- LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
- (IDIVD_IDIV << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (IDIVD_CLK_SEL << 24) ; /* Clock source */
-
- LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
- (IDIVE_IDIV << 2) | /* IDIV */
- (1 << 11) | /* Autoblock En */
- (IDIVE_CLK_SEL << 24) ; /* Clock source */
-}
-
-
-/*----------------------------------------------------------------------------
- Approximate delay function (must be used after SystemCoreClockUpdate() call)
- *----------------------------------------------------------------------------*/
-#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
-
-static void WaitUs (uint32_t us) {
- uint32_t cyc = us * CPU_NANOSEC(1000)/4;
- while(cyc--);
-}
-
-
-/*----------------------------------------------------------------------------
- External Memory Controller Definitions
- *----------------------------------------------------------------------------*/
-#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
-/* Write Mode register macro */
-#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
-
-/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
-#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
-#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
-
-#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
-#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
-
-typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
-
-const uint16_t emcdivby2_opc[] = {
- 0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
- 0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
- 0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
- 0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
- 0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
- 0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
- 0xD0FC, /* BEQ loop ; Jump if 0 */
- 0x4770, /* BX LR ; Exit */
- 0,
-};
-
-#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
-#define emcdivby2_ram 0x10000000
-
-/*----------------------------------------------------------------------------
- Initialize external memory controller
- *----------------------------------------------------------------------------*/
-
-void SystemInit_ExtMemCtl (void) {
- uint32_t emcdivby2_buf[emcdivby2_szw];
- uint32_t div, n;
-
- /* Select and enable EMC branch clock */
- LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
- while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
-
- /* Set EMC clock output delay */
- if (SystemCoreClock < 80000000UL) {
- LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
- }
- else {
- LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
- }
-
- /* Configure EMC port pins */
- LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
- LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
- LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
- LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
- LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
- LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
- LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
- LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
- LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
- LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
- LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
- LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
- LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
- LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
- LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
-
- LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
- LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
- LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
- LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
- LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
- LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
- LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
- LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
- LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
- LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
- LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
-
- LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
- LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
- LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
- LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
- LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
- LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
- LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
- LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
-
- LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
- LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
- LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
- LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
- LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
- LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
- LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
- LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
- LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
- LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
- LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
- LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
-
- LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
-
- LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
- LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
- LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
- LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
- LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
- LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
- LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
- LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
- LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
- LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
- LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
- LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
- LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
- LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
- LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
- LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
- LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
-
- LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
- LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
- LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
- LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
- LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
- LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
- LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
- LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
- LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
- LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
- LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
- LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
- LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
- LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
- LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
- LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
-
- LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
- LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
-
- div = 0;
- if (SystemCoreClock > 120000000UL) {
- /* Use EMC clock divider and EMC clock output delay */
- div = 1;
- /* Following code must be executed in RAM to ensure stable operation */
- /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
- /* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
- /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
-
- /* This code configures EMC clock divider and is executed in RAM */
- for (n = 0; n < emcdivby2_szw; n++) {
- emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
- *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
- }
- __ISB();
- ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
- for (n = 0; n < emcdivby2_szw; n++) {
- *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
- }
- }
-
- /* Configure EMC clock-out pins */
- LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
- LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
- LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
- LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
-
- /* Static memory configuration (chip select 0) */
-#if (USE_EXT_STAT_MEM_CS0)
- LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
- (2 << 0) | /* Memory width 32-bit */
- (1 << 3); /* Async page mode enable */
-
- LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
-
- LPC_EMC->STATICWAITPAGE0 = 2;
-
- /* Set Static Memory Read Delay for 90ns External NOR Flash */
- LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
- LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
-#endif
-
- /* Dynamic memory configuration (chip select 0) */
-#if (USE_EXT_DYN_MEM_CS0)
-
- /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
- LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
- (0 << 12) | /* AM[12] = 0 */
- (2 << 9) | /* AM[11:9] = 2 */
- (2 << 7) ; /* AM[8:7] = 2 */
-
- LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
- LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
-
- LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
- LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
- LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
- LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
- LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
- LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
- LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
- LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
- LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
- LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
- LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
-
- WaitUs (100);
- LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
- WaitUs (10);
- LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
- WaitUs (1);
- LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
- WaitUs (1);
- LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
- WaitUs (10);
- LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
- WaitUs (10);
- LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
-
- /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
- WR_MODE(((3 << 4) | 2) << 12);
-
- WaitUs (10);
- LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
- LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
-#endif
-}
-
-
-/*----------------------------------------------------------------------------
- Measure frequency using frequency monitor
- *----------------------------------------------------------------------------*/
-uint32_t MeasureFreq (uint32_t clk_sel) {
- uint32_t fcnt, rcnt, fout;
-
- /* Set register values */
- LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
- LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
- LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
- while (LPC_CGU->FREQ_MON & (1 << 23)) {
- fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
- rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
- if (fcnt == 0 && rcnt == 0) {
- return (0); /* No input clock present */
- }
- }
- fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
- fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
-
- return (fout);
-}
-
-
-/*----------------------------------------------------------------------------
- Get PLL1 (divider and multiplier) parameters
- *----------------------------------------------------------------------------*/
-static __inline uint32_t GetPLL1Param (void) {
- uint32_t ctrl;
- uint32_t p;
- uint32_t div, mul;
-
- ctrl = LPC_CGU->PLL1_CTRL;
- div = ((ctrl >> 12) & 0x03) + 1;
- mul = ((ctrl >> 16) & 0xFF) + 1;
- p = 1 << ((ctrl >> 8) & 0x03);
-
- if (ctrl & (1 << 1)) {
- /* Bypass = 1, PLL1 input clock sent to post-dividers */
- if (ctrl & (1 << 7)) {
- div *= (2*p);
- }
- }
- else {
- /* Direct and integer mode */
- if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
- /* Non-integer mode */
- div *= (2*p);
- }
- }
- return ((div << 8) | (mul));
-}
-
-
-/*----------------------------------------------------------------------------
- Get input clock source for specified clock generation block
- *----------------------------------------------------------------------------*/
-int32_t GetClkSel (uint32_t clk_src) {
- uint32_t reg;
- int32_t clk_sel = -1;
-
- switch (clk_src) {
- case CLK_SRC_IRC:
- case CLK_SRC_ENET_RX:
- case CLK_SRC_ENET_TX:
- case CLK_SRC_GP_CLKIN:
- return (clk_src);
-
- case CLK_SRC_32KHZ:
- return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
- case CLK_SRC_XTAL:
- return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
-
- case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
- case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
- case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
-
- case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
- case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
- case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
- case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
- case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
-
- default:
- return (clk_sel);
- }
- if (!(reg & 1)) {
- clk_sel = (reg >> 24) & 0x1F;
- }
- return (clk_sel);
-}
-
-
-/*----------------------------------------------------------------------------
- Get clock frequency for specified clock source
- *----------------------------------------------------------------------------*/
-uint32_t GetClockFreq (uint32_t clk_src) {
- uint32_t tmp;
- uint32_t mul = 1;
- uint32_t div = 1;
- uint32_t main_freq = 0;
- int32_t clk_sel = clk_src;
-
- do {
- switch (clk_sel) {
- case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
- case CLK_SRC_IRC: main_freq = CLK_IRC; break;
- case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
- case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
- case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
- case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
-
- case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
- case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
- case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
- case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
- case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
-
- case CLK_SRC_PLL0U: /* Not implemented */ break;
- case CLK_SRC_PLL0A: /* Not implemented */ break;
-
- case CLK_SRC_PLL1:
- tmp = GetPLL1Param ();
- mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
- div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
- break;
-
- default:
- return (0); /* Clock not running or not supported */
- }
- if (main_freq == 0) {
- clk_sel = GetClkSel (clk_sel);
- }
- }
- while (main_freq == 0);
-
- return ((main_freq * mul) / div);
-}
-
-
-/*----------------------------------------------------------------------------
- System Core Clock update
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) {
- /* Check BASE_M4_CLK connection */
- uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
-
- /* Update core clock frequency */
- SystemCoreClock = GetClockFreq (base_src);
-}
-
-
-extern uint32_t __Vectors; /* see startup_LPC43xx.s */
-
-/*----------------------------------------------------------------------------
- Initialize the system
- *----------------------------------------------------------------------------*/
-void SystemInit (void) {
-
- #if (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
- (3UL << 11*2) ); /* set CP11 Full Access */
- #endif
-
- /* Stop CM0 core */
- LPC_RGU->RESET_CTRL1 = (1 << 24);
-
- /* Disable SysTick timer */
- SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
-
- /* Set vector table pointer */
- SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
-
- /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
- SetClock();
-
- /* Update SystemCoreClock variable */
- SystemCoreClockUpdate();
-
- /* Configure External Memory Controller */
-//SystemInit_ExtMemCtl ();
-}
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_0.c b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_0.c
deleted file mode 100644
index 7b37ed6..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_0.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK Middleware - Component ::USB:Device
- * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
- *------------------------------------------------------------------------------
- * Name: USBD_Config_0.c
- * Purpose: USB Device Configuration
- * Rev.: V5.2.0
- *------------------------------------------------------------------------------
- * Use the following configuration settings in the Device Class configuration
- * files to assign a Device Class to this USB Device 0.
- *
- * Configuration Setting Value
- * --------------------- -----
- * Assign Device Class to USB Device # = 0
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>USB Device 0
-// <o>Connect to hardware via Driver_USBD# <0-255>
-// <i>Select driver control block for hardware interface.
-#define USBD0_PORT 0
-
-// <o.0>High-speed
-// <i>Enable High-speed functionality (if device supports it).
-#define USBD0_HS 1
-
-// <h>Device Settings
-// <i>These settings are used to create the Device Descriptor
-// <o>Max Endpoint 0 Packet Size
-// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
-// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
-#define USBD0_MAX_PACKET0 64
-
-// <o.0..15>Vendor ID <0x0000-0xFFFF>
-// <i>Vendor ID assigned by USB-IF (idVendor).
-#define USBD0_DEV_DESC_IDVENDOR 0xC251
-
-// <o.0..15>Product ID <0x0000-0xFFFF>
-// <i>Product ID assigned by manufacturer (idProduct).
-#define USBD0_DEV_DESC_IDPRODUCT 0xF001
-
-// <o.0..15>Device Release Number <0x0000-0xFFFF>
-// <i>Device Release Number in binary-coded decimal (bcdDevice)
-#define USBD0_DEV_DESC_BCDDEVICE 0x0100
-
-// </h>
-
-// <h>Configuration Settings
-// <i>These settings are used to create the Configuration Descriptor.
-// <o.6>Power
-// <i>Default Power Setting (D6: of bmAttributes).
-// <0=>Bus-powered
-// <1=>Self-powered
-// <o.5>Remote Wakeup
-// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
-#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
-
-// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
-// <i>Maximum Power Consumption of USB Device from bus in this
-// <i>specific configuration when device is fully operational (bMaxPower).
-#define USBD0_CFG_DESC_BMAXPOWER 250
-
-// </h>
-
-// <h>String Settings
-// <i>These settings are used to create the String Descriptor.
-// <o.0..15>Language ID <0x0000-0xFCFF>
-// <i>English (United States) = 0x0409.
-#define USBD0_STR_DESC_LANGID 0x0409
-
-// <s.126>Manufacturer String
-// <i>String Descriptor describing Manufacturer.
-#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
-
-// <s.126>Product String
-// <i>String Descriptor describing Product.
-#define USBD0_STR_DESC_PROD L"LPC-Link2 CMSIS-DAP"
-
-// <e.0>Serial Number String
-// <i>Enable Serial Number String.
-// <i>If disabled Serial Number String will not be assigned to USB Device.
-#define USBD0_STR_DESC_SER_EN 1
-
-// <s.126>Default value
-// <i>Default device's Serial Number String.
-#define USBD0_STR_DESC_SER L"0001A0000000"
-
-// <o.0..7>Maximum Length (in characters) <0-126>
-// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
-// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
-#define USBD0_STR_DESC_SER_MAX_LEN 16
-
-// </e>
-// </h>
-
-// <h>Microsoft OS Descriptors Settings
-// <i>These settings are used to create the Microsoft OS Descriptors.
-// <e.0>OS String
-// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
-#define USBD0_OS_DESC_EN 0
-
-// <o.0..7>Vendor Code <0x01-0xFF>
-// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
-#define USBD0_OS_DESC_VENDOR_CODE 0x01
-
-// </e>
-// </h>
-
-// <o>Control Transfer Buffer Size <64-65536:64>
-// <i>Specifies size of buffer used for Control Transfers.
-// <i>It should be at least as big as maximum packet size for Endpoint 0.
-#define USBD0_EP0_BUF_SIZE 128
-
-// <h>OS Resources Settings
-// <i>These settings are used to optimize usage of OS resources.
-// <o>Core Thread Stack Size <64-65536>
-#define USBD0_CORE_THREAD_STACK_SIZE 512
-
-// Core Thread Priority
-#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
-
-// </h>
-// </h>
-
-
-#include "RTE_Components.h"
-
-#ifdef RTE_USB_Device_CustomClass_0
-#include "USBD_Config_CustomClass_0.h"
-#endif
-#ifdef RTE_USB_Device_CustomClass_1
-#include "USBD_Config_CustomClass_1.h"
-#endif
-#ifdef RTE_USB_Device_CustomClass_2
-#include "USBD_Config_CustomClass_2.h"
-#endif
-#ifdef RTE_USB_Device_CustomClass_3
-#include "USBD_Config_CustomClass_3.h"
-#endif
-
-#ifdef RTE_USB_Device_HID_0
-#include "USBD_Config_HID_0.h"
-#endif
-#ifdef RTE_USB_Device_HID_1
-#include "USBD_Config_HID_1.h"
-#endif
-#ifdef RTE_USB_Device_HID_2
-#include "USBD_Config_HID_2.h"
-#endif
-#ifdef RTE_USB_Device_HID_3
-#include "USBD_Config_HID_3.h"
-#endif
-
-#ifdef RTE_USB_Device_MSC_0
-#include "USBD_Config_MSC_0.h"
-#endif
-#ifdef RTE_USB_Device_MSC_1
-#include "USBD_Config_MSC_1.h"
-#endif
-#ifdef RTE_USB_Device_MSC_2
-#include "USBD_Config_MSC_2.h"
-#endif
-#ifdef RTE_USB_Device_MSC_3
-#include "USBD_Config_MSC_3.h"
-#endif
-
-#ifdef RTE_USB_Device_CDC_0
-#include "USBD_Config_CDC_0.h"
-#endif
-#ifdef RTE_USB_Device_CDC_1
-#include "USBD_Config_CDC_1.h"
-#endif
-#ifdef RTE_USB_Device_CDC_2
-#include "USBD_Config_CDC_2.h"
-#endif
-#ifdef RTE_USB_Device_CDC_3
-#include "USBD_Config_CDC_3.h"
-#endif
-#ifdef RTE_USB_Device_CDC_4
-#include "USBD_Config_CDC_4.h"
-#endif
-#ifdef RTE_USB_Device_CDC_5
-#include "USBD_Config_CDC_5.h"
-#endif
-#ifdef RTE_USB_Device_CDC_6
-#include "USBD_Config_CDC_6.h"
-#endif
-#ifdef RTE_USB_Device_CDC_7
-#include "USBD_Config_CDC_7.h"
-#endif
-
-#ifdef RTE_USB_Device_ADC_0
-#include "USBD_Config_ADC_0.h"
-#endif
-#ifdef RTE_USB_Device_ADC_1
-#include "USBD_Config_ADC_1.h"
-#endif
-#ifdef RTE_USB_Device_ADC_2
-#include "USBD_Config_ADC_2.h"
-#endif
-#ifdef RTE_USB_Device_ADC_3
-#include "USBD_Config_ADC_3.h"
-#endif
-
-#include "usbd_config.h"
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_HID_0.h b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_HID_0.h
deleted file mode 100644
index e6027cc..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_HID_0.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK Middleware - Component ::USB:Device
- * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
- *------------------------------------------------------------------------------
- * Name: USBD_Config_HID_0.h
- * Purpose: USB Device Human Interface Device class (HID) Configuration
- * Rev.: V5.0.2
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>USB Device: Human Interface Device class (HID) 0
-// <o>Assign Device Class to USB Device # <0-3>
-// <i>Select USB Device that is used for this Device Class instance
-#define USBD_HID0_DEV 0
-
-// <h>Interrupt Endpoint Settings
-// <i>By default, the settings match the first USB Class instance in a USB Device.
-// <i>Endpoint conflicts are flagged by compile-time error messages.
-//
-// <h>Interrupt IN Endpoint Settings
-// <o.0..3>Interrupt IN Endpoint Number
-// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
-#define USBD_HID0_EP_INT_IN 1
-
-// <h>Endpoint Settings
-// <i>Parameters are used to create Endpoint Descriptors
-// <i>and for memory allocation in the USB component.
-//
-// <h>Full/Low-speed (High-speed disabled)
-// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
-// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
-// <i>Specifies the physical packet size used for information exchange.
-// <i>Maximum value is 64.
-#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE 64
-
-// <o.0..7>Endpoint polling Interval (in ms) <1-255>
-// <i>Specifies the frequency of requests initiated by USB Host for getting data.
-#define USBD_HID0_EP_INT_IN_BINTERVAL 1
-
-// </h>
-
-// <h>High-speed
-// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
-//
-// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
-// <i>Specifies the physical packet size used for information exchange.
-// <i>Maximum value is 1024.
-// <o.11..12>Additional transactions per microframe
-// <i>Additional transactions improve communication performance.
-// <0=>None <1=>1 additional <2=>2 additional
-#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE 64
-
-// <o.0..4>Endpoint polling Interval (in 125 us intervals)
-// <i>Specifies the frequency of requests initiated by USB Host for getting data.
-// <1=> 1 <2=> 2 <3=> 4 <4=> 8
-// <5=> 16 <6=> 32 <7=> 64 <8=> 128
-// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
-// <13=>4096 <14=>8192 <15=>16384 <16=>32768
-#define USBD_HID0_EP_INT_IN_HS_BINTERVAL 1
-
-// </h>
-// </h>
-// </h>
-
-// <h>Interrupt OUT Endpoint Settings
-// <o.0..3>Interrupt OUT Endpoint Number
-// <i>When OUT Endpoint is set to "Not used" the USB Host uses
-// <i>the Control Endpoint 0 for Out Reports.
-// <0=>Not used
-// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
-#define USBD_HID0_EP_INT_OUT 1
-
-// <h>Endpoint Settings
-// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
-// <i>and for memory allocation in the USB component.
-//
-// <h>Full/Low-speed (High-speed disabled)
-// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
-// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
-// <i>Specifies the physical packet size used for information exchange.
-// <i>Maximum value is 64.
-#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE 64
-
-// <o.0..7>Endpoint polling Interval (in ms) <1-255>
-// <i>Specifies the frequency of requests sent by USB Host for setting data.
-#define USBD_HID0_EP_INT_OUT_BINTERVAL 1
-
-// </h>
-
-// <h>High-speed
-// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
-//
-// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
-// <i>Specifies the physical packet size used for information exchange.
-// <i>Maximum value is 1024.
-// <o.11..12>Additional transactions per microframe
-// <i>Additional transactions improve communication performance.
-// <0=>None <1=>1 additional <2=>2 additional
-#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE 64
-
-// <o.0..4>Endpoint polling Interval (in 125 us intervals)
-// <i>Specifies the frequency of requests sent by USB Host for setting data.
-// <1=> 1 <2=> 2 <3=> 4 <4=> 8
-// <5=> 16 <6=> 32 <7=> 64 <8=> 128
-// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
-// <13=>4096 <14=>8192 <15=>16384 <16=>32768
-#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL 1
-
-// </h>
-// </h>
-// </h>
-// </h>
-
-// <h>Human Interface Device Class Settings
-// <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
-// <i>and for memory allocation in the USB component.
-//
-// <s.126>HID Interface String
-#define USBD_HID0_STR_DESC L"LPC-Link2 CMSIS-DAP"
-
-// <o.0..4>Number of Input Reports <1-32>
-// <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
-#define USBD_HID0_IN_REPORT_NUM 1
-
-// <o.0..4>Number of Output Reports <1-32>
-// <i>Configures max 'rid' value for USBD_HID0_SetReport
-#define USBD_HID0_OUT_REPORT_NUM 1
-
-// <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
-// <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
-// <i>and USBD_HID_GetReportTrigger
-#define USBD_HID0_IN_REPORT_MAX_SZ 1024
-
-// <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
-// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
-// <i>when rtype=HID_REPORT_OUTPUT.
-#define USBD_HID0_OUT_REPORT_MAX_SZ 1024
-
-// <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
-// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
-// <i>when rtype=HID_REPORT_FEATURE
-#define USBD_HID0_FEAT_REPORT_MAX_SZ 1
-
-// <e.0>Use User Provided HID Report Descriptor
-// <i>User needs to provide HID Report Descriptor in array
-// <i>const uint8_t usbd_hid0_report_descriptor[]
-#define USBD_HID0_USER_REPORT_DESCRIPTOR 0
-
-// <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
-#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE 33
-
-// </e>
-// </h>
-
-// <h>OS Resources Settings
-// <i>These settings are used to optimize usage of OS resources.
-// <o>Human Interface Device Class Thread Stack Size <64-65536>
-#define USBD_HID0_THREAD_STACK_SIZE 512
-
-// Human Interface Device Class Thread Priority
-#define USBD_HID0_THREAD_PRIORITY osPriorityAboveNormal
-
-// </h>
-// </h>
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/USBD_User_HID_0.c b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/USBD_User_HID_0.c
deleted file mode 100644
index 206537b..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/USBD_User_HID_0.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK Middleware - Component ::USB:Device
- * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name: USBD_User_HID_0.c
- * Purpose: USB Device Human Interface Device class (HID) User module
- * Rev.: V6.2.3
- *----------------------------------------------------------------------------*/
-/**
- * \addtogroup usbd_hidFunctions
- *
- * USBD_User_HID_0.c implements the application specific functionality of the
- * HID class and is used to receive and send data reports to the USB Host.
- *
- * The implementation must match the configuration file USBD_Config_HID_0.h.
- * The following values in USBD_Config_HID_0.h affect the user code:
- *
- * - 'Endpoint polling Interval' specifies the frequency of requests
- * initiated by USB Host for \ref USBD_HIDn_GetReport.
- *
- * - 'Number of Output Reports' configures the values for \em rid of
- * \ref USBD_HIDn_SetReport.
- *
- * - 'Number of Input Reports' configures the values for \em rid of
- * \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
- *
- * - 'Maximum Input Report Size' specifies the maximum value for:
- * - return of \ref USBD_HIDn_GetReport
- * - len of \ref USBD_HID_GetReportTrigger.
- *
- * - 'Maximum Output Report Size' specifies the maximum value for \em len
- * in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
- *
- * - 'Maximum Feature Report Size' specifies the maximum value for \em len
- * in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
- *
- */
-
-
-//! [code_USBD_User_HID]
-
-#include <stdint.h>
-#include <string.h>
-#include "cmsis_os2.h"
-#define osObjectsExternal
-#include "osObjects.h"
-#include "rl_usb.h"
-#include "RTE\USB\USBD_Config_HID_0.h"
-#include "DAP_config.h"
-#include "DAP.h"
-
-
-#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
-#error "USB HID0 Output Report Size must match DAP Packet Size"
-#endif
-#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
-#error "USB HID Input Report Size must match DAP Packet Size"
-#endif
-
-static volatile uint16_t USB_RequestIndexI; // Request Index In
-static volatile uint16_t USB_RequestIndexO; // Request Index Out
-static volatile uint16_t USB_RequestCountI; // Request Count In
-static volatile uint16_t USB_RequestCountO; // Request Count Out
-
-static volatile uint16_t USB_ResponseIndexI; // Response Index In
-static volatile uint16_t USB_ResponseIndexO; // Response Index Out
-static volatile uint16_t USB_ResponseCountI; // Response Count In
-static volatile uint16_t USB_ResponseCountO; // Response Count Out
-static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
-
-static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
-static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
-
-
-// Called during USBD_Initialize to initialize the USB HID class instance.
-void USBD_HID0_Initialize (void) {
- // Initialize variables
- USB_RequestIndexI = 0U;
- USB_RequestIndexO = 0U;
- USB_RequestCountI = 0U;
- USB_RequestCountO = 0U;
- USB_ResponseIndexI = 0U;
- USB_ResponseIndexO = 0U;
- USB_ResponseCountI = 0U;
- USB_ResponseCountO = 0U;
- USB_ResponseIdle = 1U;
-}
-
-
-// Called during USBD_Uninitialize to de-initialize the USB HID class instance.
-void USBD_HID0_Uninitialize (void) {
-}
-
-
-// \brief Prepare HID Report data to send.
-// \param[in] rtype report type:
-// - HID_REPORT_INPUT = input report requested
-// - HID_REPORT_FEATURE = feature report requested
-// \param[in] req request type:
-// - USBD_HID_REQ_EP_CTRL = control endpoint request
-// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
-// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
-// \param[in] rid report ID (0 if only one report exists).
-// \param[out] buf buffer containing report data to send.
-// \return number of report data bytes prepared to send or invalid report requested.
-// - value >= 0: number of report data bytes prepared to send
-// - value = -1: invalid report requested
-int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
- (void)rid;
-
- switch (rtype) {
- case HID_REPORT_INPUT:
- switch (req) {
- case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
- case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
- break;
- case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
- if (USB_ResponseCountI != USB_ResponseCountO) {
- // Load data from response buffer to be sent back
- memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
- USB_ResponseIndexO++;
- if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
- USB_ResponseIndexO = 0U;
- }
- USB_ResponseCountO++;
- return ((int32_t)DAP_PACKET_SIZE);
- } else {
- USB_ResponseIdle = 1U;
- }
- break;
- }
- break;
- case HID_REPORT_FEATURE:
- break;
- }
- return (0);
-}
-
-
-// \brief Process received HID Report data.
-// \param[in] rtype report type:
-// - HID_REPORT_OUTPUT = output report received
-// - HID_REPORT_FEATURE = feature report received
-// \param[in] req request type:
-// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
-// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
-// \param[in] rid report ID (0 if only one report exists).
-// \param[in] buf buffer that receives report data.
-// \param[in] len length of received report data.
-// \return true received report data processed.
-// \return false received report data not processed or request not supported.
-bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
- (void)req;
- (void)rid;
-
- switch (rtype) {
- case HID_REPORT_OUTPUT:
- if (len == 0) {
- break;
- }
- if (buf[0] == ID_DAP_TransferAbort) {
- DAP_TransferAbort = 1U;
- break;
- }
- if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
- osThreadFlagsSet(DAP_ThreadId, 0x80U);
- break; // Discard packet when buffer is full
- }
- // Store received data into request buffer
- memcpy(USB_Request[USB_RequestIndexI], buf, (uint32_t)len);
- USB_RequestIndexI++;
- if (USB_RequestIndexI == DAP_PACKET_COUNT) {
- USB_RequestIndexI = 0U;
- }
- USB_RequestCountI++;
- osThreadFlagsSet(DAP_ThreadId, 0x01U);
- break;
- case HID_REPORT_FEATURE:
- break;
- }
- return true;
-}
-
-
-// DAP Thread.
-__NO_RETURN void DAP_Thread (void *argument) {
- uint32_t flags;
- uint32_t n;
- (void) argument;
-
- for (;;) {
- osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
-
- // Process pending requests
- while (USB_RequestCountI != USB_RequestCountO) {
-
- // Handle Queue Commands
- n = USB_RequestIndexO;
- while (USB_Request[n][0] == ID_DAP_QueueCommands) {
- USB_Request[n][0] = ID_DAP_ExecuteCommands;
- n++;
- if (n == DAP_PACKET_COUNT) {
- n = 0U;
- }
- if (n == USB_RequestIndexI) {
- flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
- if (flags & 0x80U) {
- break;
- }
- }
- }
-
- // Execute DAP Command (process request and prepare response)
- DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
-
- // Update Request Index and Count
- USB_RequestIndexO++;
- if (USB_RequestIndexO == DAP_PACKET_COUNT) {
- USB_RequestIndexO = 0U;
- }
- USB_RequestCountO++;
-
- // Update Response Index and Count
- USB_ResponseIndexI++;
- if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
- USB_ResponseIndexI = 0U;
- }
- USB_ResponseCountI++;
-
- if (USB_ResponseIdle) {
- if (USB_ResponseCountI != USB_ResponseCountO) {
- // Load data from response buffer to be sent back
- n = USB_ResponseIndexO++;
- if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
- USB_ResponseIndexO = 0U;
- }
- USB_ResponseCountO++;
- USB_ResponseIdle = 0U;
- USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
- }
- }
- }
- }
-}
-
-//! [code_USBD_User_HID]
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/main.c b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/main.c
deleted file mode 100644
index 0443bb6..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/main.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 21. May 2021
- * $Revision: V2.0.0
- *
- * Project: CMSIS-DAP Examples LPC-Link2
- * Title: main.c CMSIS-DAP Main module for LPC-Link2
- *
- *---------------------------------------------------------------------------*/
-
-#include "cmsis_os2.h"
-#include "osObjects.h"
-#include "rl_usb.h"
-#include "DAP_config.h"
-#include "DAP.h"
-
-// Application Main program
-__NO_RETURN void app_main (void *argument) {
- (void)argument;
-
- DAP_Setup(); // DAP Setup
-
- USBD_Initialize(0U); // USB Device Initialization
- USBD_Connect(0U); // USB Device Connect
-
- while (!USBD_Configured(0U)); // Wait for USB Device to configure
-
- LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
- LED_RUNNING_OUT(1U); // Turn on Target Running LED
- Delayms(500U); // Wait for 500ms
- LED_RUNNING_OUT(0U); // Turn off Target Running LED
- LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
-
- // Create DAP Thread
- DAP_ThreadId = osThreadNew(DAP_Thread, NULL, NULL);
-
- osDelay(osWaitForever);
- for (;;) {}
-}
-
-int main (void) {
-
- SystemCoreClockUpdate();
- osKernelInitialize(); // Initialize CMSIS-RTOS
- osThreadNew(app_main, NULL, NULL); // Create application main thread
- if (osKernelGetState() == osKernelReady) {
- osKernelStart(); // Start thread execution
- }
-
- for (;;) {}
-}
diff --git a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/osObjects.h b/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/osObjects.h
deleted file mode 100644
index 56a03ca..0000000
--- a/CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/osObjects.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 1. December 2017
- * $Revision: V2.0.0
- *
- * Project: CMSIS-DAP Examples LPC-Link2
- * Title: osObjects.h CMSIS-DAP RTOS2 Objects for LPC-Link2
- *
- *---------------------------------------------------------------------------*/
-
-#ifndef __osObjects_h__
-#define __osObjects_h__
-
-#include "cmsis_os2.h"
-
-#ifdef osObjectsExternal
-extern osThreadId_t DAP_ThreadId;
-#else
-extern osThreadId_t DAP_ThreadId;
- osThreadId_t DAP_ThreadId;
-#endif
-
-extern void DAP_Thread (void *argument);
-
-extern void app_main (void *argument);
-
-#endif /* __osObjects_h__ */