Enhance component conditions for Dcore="Star-MC1"
- Reworked conditions to reduce duplicate file entries.
- Updated version and history for CMSIS-Core(M)
- Updated PACK.xsd (local copy)
- Enhance gen_pack.sh to update PACK.xsd on the fly
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 8a2af8c..4fd9e8f 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -10,6 +10,8 @@
<releases>
<release version="5.8.1">
Active development ...
+ CMSIS-Core(M): 5.6.0
+ - Arm China STAR-MC1 cpu support
CMSIS-DSP: 1.10.0 (see revision history for details)
CMSIS-NN: 3.1.0 (see revision history for details)
- Support for int16 convolution and fully connected for reference implementation
@@ -1072,15 +1074,24 @@
<accept Dcore="Cortex-M7"/>
<accept Dcore="SC300"/>
</condition>
- <condition id="ARMv8-M Device">
- <description>Armv8-M architecture based device</description>
+ <condition id="ARMv8-MBL Device">
+ <description>Armv8-M base line architecture based device</description>
<accept Dcore="ARMV8MBL"/>
+ <accept Dcore="Cortex-M23"/>
+ </condition>
+ <condition id="ARMv8-MML Device">
+ <description>Armv8-M main line architecture based device</description>
<accept Dcore="ARMV8MML"/>
<accept Dcore="ARMV81MML"/>
- <accept Dcore="Cortex-M23"/>
<accept Dcore="Cortex-M33"/>
<accept Dcore="Cortex-M35P"/>
<accept Dcore="Cortex-M55"/>
+ <accept Dcore="Star-MC1"/>
+ </condition>
+ <condition id="ARMv8-M Device">
+ <description>Armv8-M architecture based device</description>
+ <accept condition="ARMv8-MBL Device"/>
+ <accept condition="ARMv8-MML Device"/>
</condition>
<condition id="ARMv6_7-M Device">
<description>Armv6_7-M architecture based device</description>
@@ -1115,897 +1126,20 @@
<accept Dsecure="Non-secure"/>
<accept Dsecure="TZ-disabled"/>
</condition>
- <condition id="TZ Unavailable">
- <description>TrustZone not available</description>
- <deny Dtz="TZ"/>
- </condition>
- <!-- ARM core -->
- <condition id="CM0">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
- <accept Dcore="Cortex-M0"/>
- <accept Dcore="Cortex-M0+"/>
- <accept Dcore="SC000"/>
- </condition>
- <condition id="CM1">
- <description>Cortex-M1</description>
- <require Dcore="Cortex-M1"/>
- </condition>
- <condition id="CM3">
- <description>Cortex-M3 or SC300 processor based device</description>
- <accept Dcore="Cortex-M3"/>
- <accept Dcore="SC300"/>
- </condition>
- <condition id="CM4">
- <description>Cortex-M4 processor based device</description>
- <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM4_FP">
- <description>Cortex-M4 processor based device using Floating Point Unit</description>
- <accept Dcore="Cortex-M4" Dfpu="FPU"/>
- <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
- <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
- </condition>
- <condition id="CM7">
- <description>Cortex-M7 processor based device</description>
- <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM7_FP">
- <description>Cortex-M7 processor based device using Floating Point Unit</description>
- <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
- <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
- </condition>
- <condition id="CM23">
- <description>Cortex-M23 processor based device</description>
- <require Dcore="Cortex-M23"/>
- </condition>
- <condition id="CM33">
- <description>Cortex-M33 processor based device</description>
- <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM33_FP">
- <description>Cortex-M33 processor based device using Floating Point Unit</description>
- <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
- </condition>
- <condition id="CM35P">
- <description>Cortex-M35P processor based device</description>
- <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM35P_FP">
- <description>Cortex-M35P processor based device using Floating Point Unit</description>
- <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
- </condition>
- <condition id="ARMv8MBL">
- <description>Armv8-M Baseline processor based device</description>
- <require Dcore="ARMV8MBL"/>
- </condition>
- <condition id="ARMv8MML">
- <description>Armv8-M Mainline processor based device</description>
- <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
- </condition>
- <condition id="ARMv8MML_FP">
- <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
- <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
- <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
- </condition>
-
- <condition id="CM55_NOFPU_NOMVE">
- <description>Cortex-M55, no FPU, no MVE</description>
- <require Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="NO_MVE"/>
- </condition>
- <condition id="CM55_NOFPU_MVE">
- <description>Cortex-M55, no FPU, MVE</description>
- <accept Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="MVE"/>
- <accept Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="FP_MVE"/>
- </condition>
- <condition id="CM55_FPU">
- <description>Cortex-M55, FPU</description>
- <accept Dcore="Cortex-M55" Dfpu="SP_FPU"/>
- <accept Dcore="Cortex-M55" Dfpu="DP_FPU"/>
- </condition>
-
- <condition id="CA5_CA9">
- <description>Cortex-A5 or Cortex-A9 processor based device</description>
- <accept Dcore="Cortex-A5"/>
- <accept Dcore="Cortex-A9"/>
- </condition>
-
- <condition id="CA7">
- <description>Cortex-A7 processor based device</description>
- <accept Dcore="Cortex-A7"/>
- </condition>
-
- <!-- ARMCC compiler -->
- <condition id="CA_ARMCC5">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
- <require condition="ARMv7-A Device"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CA_ARMCC6">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
- <require condition="ARMv7-A Device"/>
+ <!-- Startup -->
+ <condition id="Startup ARMCC6 Secure">
+ <description>Startup files for Arm Compiler 6 targeting TrustZone secure mode</description>
<require condition="ARMCC6"/>
- </condition>
-
- <condition id="CM0_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
- <require condition="CM0"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM0_ARMCC5">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler 5</description>
- <require condition="CM0"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM0_ARMCC6">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler 6</description>
- <require condition="CM0"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM0_LE_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM0_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM0_BE_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
- <require condition="CM0_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM1_ARMCC">
- <description>Cortex-M1 based device for the Arm Compiler</description>
- <require condition="CM1"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM1_ARMCC5">
- <description>Cortex-M1 based device for the Arm Compiler 5</description>
- <require condition="CM1"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM1_ARMCC6">
- <description>Cortex-M1 based device for the Arm Compiler 6</description>
- <require condition="CM1"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM1_LE_ARMCC">
- <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
- <require condition="CM1_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM1_BE_ARMCC">
- <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
- <require condition="CM1_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM3_ARMCC">
- <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
- <require condition="CM3"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM3_ARMCC5">
- <description>Cortex-M3 or SC300 processor based device for the Arm Compiler 5</description>
- <require condition="CM3"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM3_ARMCC6">
- <description>Cortex-M3 or SC300 processor based device for the Arm Compiler 6</description>
- <require condition="CM3"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM3_LE_ARMCC">
- <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM3_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM3_BE_ARMCC">
- <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
- <require condition="CM3_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_ARMCC">
- <description>Cortex-M4 processor based device for the Arm Compiler</description>
- <require condition="CM4"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM4_ARMCC5">
- <description>Cortex-M4 processor based device for the Arm Compiler 5</description>
- <require condition="CM4"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM4_ARMCC6">
- <description>Cortex-M4 processor based device for the Arm Compiler 6</description>
- <require condition="CM4"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM4_LE_ARMCC">
- <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM4_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_BE_ARMCC">
- <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
- <require condition="CM4_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_FP_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
- <require condition="CM4_FP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM4_FP_ARMCC5">
- <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler 5</description>
- <require condition="CM4_FP"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM4_FP_ARMCC6">
- <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler 6</description>
- <require condition="CM4_FP"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM4_FP_LE_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
- <require condition="CM4_FP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_FP_BE_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
- <require condition="CM4_FP_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_ARMCC">
- <description>Cortex-M7 processor based device for the Arm Compiler</description>
- <require condition="CM7"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM7_ARMCC5">
- <description>Cortex-M7 processor based device for the Arm Compiler 5</description>
- <require condition="CM7"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM7_ARMCC6">
- <description>Cortex-M7 processor based device for the Arm Compiler 6</description>
- <require condition="CM7"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM7_LE_ARMCC">
- <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM7_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_BE_ARMCC">
- <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
- <require condition="CM7_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_FP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
- <require condition="CM7_FP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM7_FP_ARMCC5">
- <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler 5</description>
- <require condition="CM7_FP"/>
- <require condition="ARMCC5"/>
- </condition>
- <condition id="CM7_FP_ARMCC6">
- <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler 6</description>
- <require condition="CM7_FP"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="CM7_FP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
- <require condition="CM7_FP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_FP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
- <require condition="CM7_FP_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM23_ARMCC">
- <description>Cortex-M23 processor based device for the Arm Compiler</description>
- <require condition="CM23"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM23_LE_ARMCC">
- <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM23_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_ARMCC">
- <description>Cortex-M33 processor based device for the Arm Compiler</description>
- <require condition="CM33"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_LE_ARMCC">
- <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM33_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_FP_ARMCC">
- <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
- <require condition="CM33_FP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_FP_LE_ARMCC">
- <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
- <require condition="CM33_FP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_ARMCC">
- <description>Cortex-M35P processor based device for the Arm Compiler</description>
- <require condition="CM35P"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_LE_ARMCC">
- <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM35P_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_FP_ARMCC">
- <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
- <require condition="CM35P_FP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_FP_LE_ARMCC">
- <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
- <require condition="CM35P_FP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_NOMVE_ARMCC">
- <description>Cortex-M55 processor, no FPU, no MVE, Arm Compiler</description>
- <require condition="CM55_NOFPU_NOMVE"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM55_NOFPU_MVE_ARMCC">
- <description>Cortex-M55 processor, no FPU, MVE, Arm Compiler</description>
- <require condition="CM55_NOFPU_MVE"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM55_FPU_ARMCC">
- <description>Cortex-M55 processor, FPU, Arm Compiler</description>
- <require condition="CM55_FPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM55_NOFPU_NOMVE_LE_ARMCC">
- <description>Cortex-M55 processor, little endian, no FPU, no MVE, Arm Compiler</description>
- <require condition="CM55_NOFPU_NOMVE_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM55_FPU_LE_ARMCC">
- <description>Cortex-M55 processor, little endian, FPU, Arm Compiler</description>
- <require condition="CM55_FPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MBL_ARMCC">
- <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
- <require condition="ARMv8MBL"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MBL_LE_ARMCC">
- <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
- <require condition="ARMv8MBL_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_ARMCC">
- <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
- <require condition="ARMv8MML"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_LE_ARMCC">
- <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
- <require condition="ARMv8MML_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_FP_ARMCC">
- <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
- <require condition="ARMv8MML_FP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_FP_LE_ARMCC">
- <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
- <require condition="ARMv8MML_FP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="TZ Secure ARMCC6">
- <description>TrustZone (Secure), Arm Compiler</description>
<require condition="TZ Secure"/>
+ </condition>
+ <condition id="Startup ARMCC6 Unsecure">
+ <description>Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode</description>
<require condition="ARMCC6"/>
- </condition>
- <condition id="TZ Non-secure ARMCC6">
- <description>TrustZone (Non-secure), Arm Compiler</description>
- <require condition="TZ Non-secure"/>
- <require condition="ARMCC6"/>
- </condition>
- <condition id="TZ Unavailable ARMCC6">
- <description>TrustZone not available, Arm Compiler</description>
- <require condition="TZ Unavailable"/>
- <require condition="ARMCC6"/>
+ <deny condition="TZ Secure"/>
</condition>
- <!-- GCC compiler -->
- <condition id="CA_GCC">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
- <require condition="ARMv7-A Device"/>
- <require Tcompiler="GCC"/>
- </condition>
-
- <condition id="CM0_GCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
- <require condition="CM0"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM0_LE_GCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM0_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM0_BE_GCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
- <require condition="CM0_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM1_GCC">
- <description>Cortex-M1 based device for the GCC Compiler</description>
- <require condition="CM1"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM1_LE_GCC">
- <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description>
- <require condition="CM1_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM1_BE_GCC">
- <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description>
- <require condition="CM1_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM3_GCC">
- <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
- <require condition="CM3"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM3_LE_GCC">
- <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM3_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM3_BE_GCC">
- <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
- <require condition="CM3_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_GCC">
- <description>Cortex-M4 processor based device for the GCC Compiler</description>
- <require condition="CM4"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM4_LE_GCC">
- <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM4_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_BE_GCC">
- <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
- <require condition="CM4_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_FP_GCC">
- <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
- <require condition="CM4_FP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM4_FP_LE_GCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
- <require condition="CM4_FP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_FP_BE_GCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
- <require condition="CM4_FP_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_GCC">
- <description>Cortex-M7 processor based device for the GCC Compiler</description>
- <require condition="CM7"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM7_LE_GCC">
- <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM7_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_BE_GCC">
- <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
- <require condition="CM7_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_FP_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
- <require condition="CM7_FP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM7_FP_LE_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
- <require condition="CM7_FP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_FP_BE_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
- <require condition="CM7_FP_GCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM23_GCC">
- <description>Cortex-M23 processor based device for the GCC Compiler</description>
- <require condition="CM23"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM23_LE_GCC">
- <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM23_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_GCC">
- <description>Cortex-M33 processor based device for the GCC Compiler</description>
- <require condition="CM33"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_LE_GCC">
- <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM33_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_FP_GCC">
- <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
- <require condition="CM33_FP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_FP_LE_GCC">
- <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
- <require condition="CM33_FP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_GCC">
- <description>Cortex-M35P processor based device for the GCC Compiler</description>
- <require condition="CM35P"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_LE_GCC">
- <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM35P_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_FP_GCC">
- <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
- <require condition="CM35P_FP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_FP_LE_GCC">
- <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
- <require condition="CM35P_FP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_NOMVE_GCC">
- <description>Cortex-M55 processor, no FPU, no MVE, GCC Compiler</description>
- <require condition="CM55_NOFPU_NOMVE"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM55_NOFPU_MVE_GCC">
- <description>Cortex-M55 processor, no FPU, MVE, GCC Compiler</description>
- <require condition="CM55_NOFPU_MVE"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM55_FPU_GCC">
- <description>Cortex-M55 processor, FPU, GCC Compiler</description>
- <require condition="CM55_FPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM55_NOFPU_NOMVE_LE_GCC">
- <description>Cortex-M55 processor, little endian, no FPU, no MVE, GCC Compiler</description>
- <require condition="CM55_NOFPU_NOMVE_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM55_FPU_LE_GCC">
- <description>Cortex-M55 processor, little endian, FPU, GCC Compiler</description>
- <require condition="CM55_FPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MBL_GCC">
- <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
- <require condition="ARMv8MBL"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MBL_LE_GCC">
- <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
- <require condition="ARMv8MBL_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_GCC">
- <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
- <require condition="ARMv8MML"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_LE_GCC">
- <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
- <require condition="ARMv8MML_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_FP_GCC">
- <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
- <require condition="ARMv8MML_FP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_FP_LE_GCC">
- <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
- <require condition="ARMv8MML_FP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <!-- IAR compiler -->
- <condition id="CA_IAR">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
- <require condition="ARMv7-A Device"/>
- <require Tcompiler="IAR"/>
- </condition>
-
- <condition id="CM0_IAR">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
- <require condition="CM0"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM0_LE_IAR">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM0_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM0_BE_IAR">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
- <require condition="CM0_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM1_IAR">
- <description>Cortex-M1 based device for the IAR Compiler</description>
- <require condition="CM1"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM1_LE_IAR">
- <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description>
- <require condition="CM1_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM1_BE_IAR">
- <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description>
- <require condition="CM1_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM3_IAR">
- <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
- <require condition="CM3"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM3_LE_IAR">
- <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM3_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM3_BE_IAR">
- <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
- <require condition="CM3_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_IAR">
- <description>Cortex-M4 processor based device for the IAR Compiler</description>
- <require condition="CM4"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM4_LE_IAR">
- <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM4_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_BE_IAR">
- <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
- <require condition="CM4_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM4_FP_IAR">
- <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
- <require condition="CM4_FP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM4_FP_LE_IAR">
- <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
- <require condition="CM4_FP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM4_FP_BE_IAR">
- <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
- <require condition="CM4_FP_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_IAR">
- <description>Cortex-M7 processor based device for the IAR Compiler</description>
- <require condition="CM7"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM7_LE_IAR">
- <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM7_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_BE_IAR">
- <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
- <require condition="CM7_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_FP_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
- <require condition="CM7_FP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM7_FP_LE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
- <require condition="CM7_FP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_FP_BE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
- <require condition="CM7_FP_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM23_IAR">
- <description>Cortex-M23 processor based device for the IAR Compiler</description>
- <require condition="CM23"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM23_LE_IAR">
- <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM23_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_IAR">
- <description>Cortex-M33 processor based device for the IAR Compiler</description>
- <require condition="CM33"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_LE_IAR">
- <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM33_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM33_FP_IAR">
- <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
- <require condition="CM33_FP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_FP_LE_IAR">
- <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
- <require condition="CM33_FP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_IAR">
- <description>Cortex-M35P processor based device for the IAR Compiler</description>
- <require condition="CM35P"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_LE_IAR">
- <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM35P_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM35P_FP_IAR">
- <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
- <require condition="CM35P_FP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_FP_LE_IAR">
- <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
- <require condition="CM35P_FP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_NOMVE_IAR">
- <description>Cortex-M55 processor, no FPU, no MVE, IAR Compiler</description>
- <require condition="CM55_NOFPU_NOMVE"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM55_NOFPU_MVE_IAR">
- <description>Cortex-M55 processor, no FPU, MVE, IAR Compiler</description>
- <require condition="CM55_NOFPU_MVE"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM55_FPU_IAR">
- <description>Cortex-M55 processor, FPU, IAR Compiler</description>
- <require condition="CM55_FPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM55_NOFPU_NOMVE_LE_IAR">
- <description>Cortex-M55 processor, little endian, no FPU, no MVE, IAR Compiler</description>
- <require condition="CM55_NOFPU_NOMVE_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM55_FPU_LE_IAR">
- <description>Cortex-M55 processor, little endian, FPU, IAR Compiler</description>
- <require condition="CM55_FPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MBL_IAR">
- <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
- <require condition="ARMv8MBL"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MBL_LE_IAR">
- <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
- <require condition="ARMv8MBL_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_IAR">
- <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
- <require condition="ARMv8MML"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_LE_IAR">
- <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
- <require condition="ARMv8MML_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="ARMv8MML_FP_IAR">
- <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
- <require condition="ARMv8MML_FP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_FP_LE_IAR">
- <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
- <require condition="ARMv8MML_FP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <!-- conditions selecting single devices and CMSIS Core -->
+ <!-- CMSIS-Core -->
<condition id="ARMCM0 CMSIS">
<description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0"/>
@@ -2175,16 +1309,290 @@
<require Cclass="Device" Cgroup="Startup"/>
</condition>
+ <condition id="ARMCC ARMv6-M LE">
+ <description>Arm Compiler for Armv6-M architecture (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="ARMCC ARMv6-M BE">
+ <description>Arm Compiler for Armv6-M architecture (big endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+ <condition id="ARMCC ARMv7-M NOFP LE">
+ <description>Arm Compiler for Armv7-M architecture without FPU (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="ARMCC ARMv7-M NOFP BE">
+ <description>Arm Compiler for Armv7-M architecture without FPU (big endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="ARMCC ARMv7-M FP LE">
+ <description>Arm Compiler for Armv7-M architecture with FPU (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="ARMCC ARMv7-M FP BE">
+ <description>Arm Compiler for Armv7-M architecture with FPU (big endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="ARMCC ARMv8-MBL LE">
+ <description>Arm Compiler for Armv8-M base line architecture (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv8-MBL Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="ARMCC ARMv8-MML NOFP LE">
+ <description>Arm Compiler for Armv8-M main line architecture without FPU/MVE (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ <require Dmve="NO_MVE"/>
+ </condition>
+ <condition id="ARMCC ARMv8-MML FP LE">
+ <description>Arm Compiler for Armv8-M main line architecture with FPU/MVE (little endian)</description>
+ <require condition="ARMCC"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ <accept Dmve="MVE"/>
+ <accept Dmve="FP_MVE"/>
+ </condition>
+
+ <condition id="GCC ARMv6-M LE">
+ <description>GNU Compiler for Armv6-M architecture (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="GCC ARMv6-M BE">
+ <description>GNU Compiler for Armv6-M architecture (big endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+ <condition id="GCC ARMv7-M NOFP LE">
+ <description>GNU Compiler for Armv7-M architecture without FPU (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="GCC ARMv7-M NOFP BE">
+ <description>GNU Compiler for Armv7-M architecture without FPU (big endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="GCC ARMv7-M FP LE">
+ <description>GNU Compiler for Armv7-M architecture with FPU (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="GCC ARMv7-M FP BE">
+ <description>GNU Compiler for Armv7-M architecture with FPU (big endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="GCC ARMv8-MBL LE">
+ <description>GNU Compiler for Armv8-M base line architecture (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv8-MBL Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="GCC ARMv8-MML NOFP LE">
+ <description>GNU Compiler for Armv8-M main line architecture without FPU/MVE (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ <require Dmve="NO_MVE"/>
+ </condition>
+ <condition id="GCC ARMv8-MML FP LE">
+ <description>GNU Compiler for Armv8-M main line architecture with FPU/MVE (little endian)</description>
+ <require condition="GCC"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ <accept Dmve="MVE"/>
+ <accept Dmve="FP_MVE"/>
+ </condition>
+
+ <condition id="IARCC ARMv6-M LE">
+ <description>IAR Compiler for Armv6-M architecture (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="IARCC ARMv6-M BE">
+ <description>IAR Compiler for Armv6-M architecture (big endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv6-M Device"/>
+ <require Dendian="Big-endian"/>
+ </condition>
+ <condition id="IARCC ARMv7-M NOFP LE">
+ <description>IAR Compiler for Armv7-M architecture without FPU (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="IARCC ARMv7-M NOFP BE">
+ <description>IAR Compiler for Armv7-M architecture without FPU (big endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <require Dfpu="NO_FPU"/>
+ </condition>
+ <condition id="IARCC ARMv7-M FP LE">
+ <description>IAR Compiler for Armv7-M architecture with FPU (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="IARCC ARMv7-M FP BE">
+ <description>IAR Compiler for Armv7-M architecture with FPU (big endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-M Device"/>
+ <require Dendian="Big-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ </condition>
+ <condition id="IARCC ARMv8-MBL LE">
+ <description>IAR Compiler for Armv8-M base line architecture (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv8-MBL Device"/>
+ <require Dendian="Little-endian"/>
+ </condition>
+ <condition id="IARCC ARMv8-MML NOFP LE">
+ <description>IAR Compiler for Armv8-M main line architecture without FPU/MVE (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <require Dfpu="NO_FPU"/>
+ <require Dmve="NO_MVE"/>
+ </condition>
+ <condition id="IARCC ARMv8-MML FP LE">
+ <description>IAR Compiler for Armv8-M main line architecture with FPU/MVE (little endian)</description>
+ <require condition="IAR"/>
+ <require condition="ARMv8-MML Device"/>
+ <require Dendian="Little-endian"/>
+ <accept Dfpu="SP_FPU"/>
+ <accept Dfpu="DP_FPU"/>
+ <accept Dmve="MVE"/>
+ <accept Dmve="FP_MVE"/>
+ </condition>
+
+ <condition id="ARMASM ARMv6-M">
+ <description>Arm Assembler for Armv6-M architecture</description>
+ <require condition="ARMCC5"/>
+ <require condition="ARMv6-M Device"/>
+ </condition>
+ <condition id="GNUASM ARMv6-M">
+ <description>GNU Assembler for Armv6-M architecture</description>
+ <accept condition="ARMCC6"/>
+ <accept condition="GCC"/>
+ <require condition="ARMv6-M Device"/>
+ </condition>
+ <condition id="IARASM ARMv6-M">
+ <description>IAR Assembler for Armv6-M architecture</description>
+ <require condition="IAR"/>
+ <require condition="ARMv6-M Device"/>
+ </condition>
+
+ <condition id="ARMASM ARMv7-M">
+ <description>Arm Assembler for Armv7-M architecture</description>
+ <require condition="ARMCC5"/>
+ <require condition="ARMv7-M Device"/>
+ </condition>
+ <condition id="GNUASM ARMv7-M">
+ <description>GNU Assembler for Armv7-M architecture</description>
+ <accept condition="ARMCC6"/>
+ <accept condition="GCC"/>
+ <require condition="ARMv7-M Device"/>
+ </condition>
+ <condition id="IARASM ARMv7-M">
+ <description>IAR Assembler for Armv7-M architecture</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-M Device"/>
+ </condition>
+
+ <condition id="GNUASM ARMv8-MBL">
+ <description>GNU Assembler for Armv8-M base line architecture</description>
+ <require condition="ARMCC GCC"/>
+ <require condition="ARMv8-MBL Device"/>
+ </condition>
+ <condition id="GNUASM ARMv8-MML">
+ <description>GNU Assembler for Armv8-M main line architecture</description>
+ <require condition="ARMCC GCC"/>
+ <require condition="ARMv8-MML Device"/>
+ </condition>
+ <condition id="IARASM ARMv8-MBL">
+ <description>IAR Assembler for Armv8-M base line architecture</description>
+ <require condition="IAR"/>
+ <require condition="ARMv8-MBL Device"/>
+ </condition>
+ <condition id="IARASM ARMv8-MML">
+ <description>IAR Assembler for Armv8-M main line architecture</description>
+ <require condition="IAR"/>
+ <require condition="ARMv8-MML Device"/>
+ </condition>
+
+ <condition id="ARMASM ARMv7-A">
+ <description>Arm Assembler for Armv7-A architecture</description>
+ <require condition="ARMCC5"/>
+ <require condition="ARMv7-A Device"/>
+ </condition>
+ <condition id="GNUASM ARMv7-A">
+ <description>GNU Assembler for Armv7-A architecture</description>
+ <accept condition="ARMCC6"/>
+ <accept condition="GCC"/>
+ <require condition="ARMv7-A Device"/>
+ </condition>
+ <condition id="IARASM ARMv7-A">
+ <description>IAR Assembler for Armv7-A architecture</description>
+ <require condition="IAR"/>
+ <require condition="ARMv7-A Device"/>
+ </condition>
+
<!-- OS Tick -->
<condition id="OS Tick PTIM">
<description>Components required for OS Tick Private Timer</description>
- <require condition="CA5_CA9"/>
+ <accept Dcore="Cortex-A5"/>
+ <accept Dcore="Cortex-A9"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
<condition id="OS Tick GTIM">
<description>Components required for OS Tick Generic Physical Timer</description>
- <require condition="CA7"/>
+ <accept Dcore="Cortex-A7"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
@@ -2192,8 +1600,8 @@
<components>
<!-- CMSIS-Core component -->
- <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.5.0" condition="ARMv6_7_8-M Device" >
- <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M</description>
+ <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.6.0" condition="ARMv6_7_8-M Device" >
+ <description>CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M</description>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/Core/html/index.html"/>
@@ -2391,9 +1799,8 @@
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM23/Source/startup_ARMCM23.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM23/Source/system_ARMCM23.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2407,9 +1814,8 @@
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S" version="2.0.0" attr="config" condition="ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.1.0" attr="config" condition="IAR"/>
@@ -2427,9 +1833,8 @@
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM33/Source/startup_ARMCM33.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM33/Source/system_ARMCM33.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2443,9 +1848,8 @@
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S" version="2.0.0" attr="config" condition="ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S" version="2.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s" version="1.1.0" attr="config" condition="IAR"/>
@@ -2463,9 +1867,8 @@
<file category="include" name="Device/ARM/ARMCM35P/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2479,9 +1882,8 @@
<file category="include" name="Device/ARM/ARMCM35P/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S" version="2.0.0" attr="config" condition="ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S" version="1.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s" version="2.1.0" attr="config" condition="IAR"/>
@@ -2499,9 +1901,8 @@
<file category="include" name="Device/ARM/ARMCM55/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM55/Source/startup_ARMCM55.c" version="1.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM55/Source/system_ARMCM55.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2573,9 +1974,8 @@
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2589,9 +1989,8 @@
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S" version="2.0.0" attr="config" condition="ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c" version="1.0.1" attr="config" condition="ARMCC GCC"/>
@@ -2608,9 +2007,8 @@
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
@@ -2624,9 +2022,8 @@
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S" version="2.0.0" attr="config" condition="ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S" version="2.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c" version="1.0.1" attr="config" condition="ARMCC GCC"/>
@@ -2643,9 +2040,8 @@
<file category="include" name="Device/ARM/ARMv81MML/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c" version="2.1.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct" version="1.1.0" attr="config" condition="TZ Secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Non-secure ARMCC6"/>
- <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct" version="1.1.0" attr="config" condition="TZ Unavailable ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
+ <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv81MML/Source/system_ARMv81MML.c" version="1.2.1" attr="config"/>
<!-- SAU configuration -->
@@ -2924,50 +2320,26 @@
<!-- CPU and Compiler dependent -->
<!-- ARMCC -->
- <file category="library" condition="CM0_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM0_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM1_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM1_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM3_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM3_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM4_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM7_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM7_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<!-- GCC -->
- <file category="library" condition="CM0_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM0_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM1_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM1_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM3_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM3_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM4_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM4_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM4_FP_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM7_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM7_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM7_FP_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM7_FP_BE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<!-- IAR -->
- <file category="library" condition="CM0_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM0_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM1_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM1_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM3_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM3_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM4_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM4_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM4_FP_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM7_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM7_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM7_FP_LE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
- <file category="library" condition="CM7_FP_BE_IAR" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
+ <file category="library" condition="IARCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
</files>
</component>
<!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
@@ -3001,11 +2373,11 @@
<!-- CPU and Compiler dependent -->
<!-- ARMCC -->
- <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
- <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
+ <file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<!-- GCC -->
- <file category="library" condition="CM4_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
- <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
+ <file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<!-- IAR -->
</files>
</component>
@@ -3062,59 +2434,26 @@
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
- <file category="library" condition="CM0_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
- <file category="library" condition="CM0_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
- <file category="library" condition="CM0_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
@@ -3153,38 +2492,17 @@
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
- <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
- <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="GCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
- <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_NOMVE_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="IARCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5">
@@ -3233,70 +2551,19 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
- <!-- RTX sources (handlers ARMCC) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="CM0_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM0_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="CM1_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM1_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM3_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM3_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM4_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM4_FP_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_FP_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM7_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM7_FP_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_FP_ARMCC6"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_MVE_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_FPU_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_FP_ARMCC"/>
- <!-- RTX sources (handlers GCC) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM0_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM1_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM3_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_MVE_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_FPU_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_FP_GCC"/>
+ <!-- RTX sources (handlers ARMASM) -->
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="ARMASM ARMv6-M"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="ARMASM ARMv7-M"/>
+ <!-- RTX sources (handlers GAS) -->
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="GNUASM ARMv6-M"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="GNUASM ARMv7-M"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="GNUASM ARMv8-MBL"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="GNUASM ARMv8-MML"/>
<!-- RTX sources (handlers IAR) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="CM0_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="CM1_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM3_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM4_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM4_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM7_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM7_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="CM23_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_NOMVE_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_MVE_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_FPU_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="ARMv8MBL_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_FP_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="IARASM ARMv6-M"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="IARASM ARMv7-M"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="IARASM ARMv8-MBL"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="IARASM ARMv8-MML"/>
<!-- OS Tick (SysTick) -->
<file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
</files>
@@ -3349,13 +2616,12 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
- <!-- RTX sources (handlers ARMCC) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s" condition="CA_ARMCC5"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="CA_ARMCC6"/>
- <!-- RTX sources (handlers GCC) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="CA_GCC"/>
+ <!-- RTX sources (handlers ARMASM) -->
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s" condition="ARMASM ARMv7-A"/>
+ <!-- RTX sources (handlers GAS) -->
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="GNUASM ARMv7-A"/>
<!-- RTX sources (handlers IAR) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s" condition="CA_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s" condition="IARASM ARMv7-A"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
@@ -3405,42 +2671,12 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
- <!-- RTX sources (ARMCC handlers) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_MVE_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_FPU_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_FP_ARMCC"/>
- <!-- RTX sources (GCC handlers) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_MVE_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_FPU_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_FP_GCC"/>
+ <!-- RTX sources (GAS handlers) -->
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="GNUASM ARMv8-MBL"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="GNUASM ARMv8-MML"/>
<!-- RTX sources (IAR handlers) -->
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="CM23_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_NOMVE_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_MVE_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_FPU_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="ARMv8MBL_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_FP_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="IARASM ARMv8-MBL"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="IARASM ARMv8-MML"/>
<!-- OS Tick (SysTick) -->
<file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
</files>