Reworked ARM Cortex-M device support files to be more generic (removed peripherals).
Added scatter and C-startup files.
diff --git a/Device/ARM/SVD/ARMCM0.svd b/Device/ARM/SVD/ARMCM0.svd
index e40c842..14bf841 100644
--- a/Device/ARM/SVD/ARMCM0.svd
+++ b/Device/ARM/SVD/ARMCM0.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM0</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M0</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM0</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM0P.svd b/Device/ARM/SVD/ARMCM0P.svd
index 37ab758..ff62fd4 100644
--- a/Device/ARM/SVD/ARMCM0P.svd
+++ b/Device/ARM/SVD/ARMCM0P.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
- <name>ARMCM0P</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <name>ARMCM0P</name> <!-- name of part-->
+ <series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0+ based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM0+</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM1.svd b/Device/ARM/SVD/ARMCM1.svd
index 13eb1d5..b51ac3b 100644
--- a/Device/ARM/SVD/ARMCM1.svd
+++ b/Device/ARM/SVD/ARMCM1.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM1</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0+ based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM1</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM23.svd b/Device/ARM/SVD/ARMCM23.svd
index 83e0631..3e01f8b 100644
--- a/Device/ARM/SVD/ARMCM23.svd
+++ b/Device/ARM/SVD/ARMCM23.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM23</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M23 based device</description>
+ <description>ARM 32-bit Cortex-M23 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM23</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM3.svd b/Device/ARM/SVD/ARMCM3.svd
index 78a53ae..26e6acd 100644
--- a/Device/ARM/SVD/ARMCM3.svd
+++ b/Device/ARM/SVD/ARMCM3.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM3</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M3</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM3</name>
- <revision>r1p1</revision>
+ <revision>r2p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>4</nvicPrioBits>
+ <vtorPresent>true</vtorPresent>
+ <nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM33.svd b/Device/ARM/SVD/ARMCM33.svd
index 000c04d..ab66214 100644
--- a/Device/ARM/SVD/ARMCM33.svd
+++ b/Device/ARM/SVD/ARMCM33.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM33</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Mainline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M33 based device</description>
+ <description>ARM 32-bit Cortex-M33 based device<./description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM33</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMCM4.svd b/Device/ARM/SVD/ARMCM4.svd
index 63a9ac6..a78bc8a 100644
--- a/Device/ARM/SVD/ARMCM4.svd
+++ b/Device/ARM/SVD/ARMCM4.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM4</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M4</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M4 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM4</name>
- <revision>r1p0</revision>
+ <revision>r0p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM7.svd b/Device/ARM/SVD/ARMCM7.svd
index 34adfb1..7b69cb7 100644
--- a/Device/ARM/SVD/ARMCM7.svd
+++ b/Device/ARM/SVD/ARMCM7.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 -2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM7</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M7</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M7 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,22 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM7</name>
- <revision>r0p0</revision>
+ <revision>r1p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
+ <icachePresent>true</icachePresent>
+ <dcachePresent>true</dcachePresent>
+ <itcmPresent>false</itcmPresent>
+ <dtcmPresent>false</dtcmPresent>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +77,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMSC000.svd b/Device/ARM/SVD/ARMSC000.svd
index b3e8637..261edd1 100644
--- a/Device/ARM/SVD/ARMSC000.svd
+++ b/Device/ARM/SVD/ARMSC000.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
- <name>ARMSC000</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <name>ARMSC000</name> <!-- name of part-->
+ <series>ARM Cortex SC000</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-SC000 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>SC000</name>
- <revision>r1p0</revision>
+ <revision>r0p0</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMSC300.svd b/Device/ARM/SVD/ARMSC300.svd
index 3a066dc..8beb8cc 100644
--- a/Device/ARM/SVD/ARMSC300.svd
+++ b/Device/ARM/SVD/ARMSC300.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMSC300</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex SC300</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-SC300 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>SC300</name>
- <revision>r1p0</revision>
+ <revision>r0p0</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMv8MBL.svd b/Device/ARM/SVD/ARMv8MBL.svd
index 14b1d86..722ebe8 100644
--- a/Device/ARM/SVD/ARMv8MBL.svd
+++ b/Device/ARM/SVD/ARMv8MBL.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMv8MBL</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit v8-M Baseline based device</description>
+ <description>ARM 32-bit v8-M Baseline based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
- <name>CM3</name>
+ <name>ARMV8MBL</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMv8MML.svd b/Device/ARM/SVD/ARMv8MML.svd
index b9a639f..bb2c998 100644
--- a/Device/ARM/SVD/ARMv8MML.svd
+++ b/Device/ARM/SVD/ARMv8MML.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMv8MML</name> <!-- name of part-->
<series>ARMV8M</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit v8-M Baseline based device</description>
+ <description>ARM 32-bit v8-M Baseline based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
- <name>CM4</name>
+ <name>ARMV8MML</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>