Reworked ARM Cortex-M device support files to be more generic (removed peripherals).
Added scatter and C-startup files.
diff --git a/Device/ARM/ARMCM0/Include/ARMCM0.h b/Device/ARM/ARMCM0/Include/ARMCM0.h
index 54ada10..93881d5 100644
--- a/Device/ARM/ARMCM0/Include/ARMCM0.h
+++ b/Device/ARM/ARMCM0/Include/ARMCM0.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM0 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 31 are left out */
} IRQn_Type;
@@ -100,10 +88,10 @@
#endif
-/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM0_REV 0x0000U /* Core revision r0p0 */
-#define __MPU_PRESENT 0U /* MPU present or not */
-#define __VTOR_PRESENT 0U /* no VTOR present*/
+#define __MPU_PRESENT 0U /* no MPU present */
+#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -111,97 +99,6 @@
#include "system_ARMCM0.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,52 +119,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM0/Include/system_ARMCM0.h b/Device/ARM/ARMCM0/Include/system_ARMCM0.h
index ceac9d2..7fe7e91 100644
--- a/Device/ARM/ARMCM0/Include/system_ARMCM0.h
+++ b/Device/ARM/ARMCM0/Include/system_ARMCM0.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM0.h
* @brief CMSIS Device System Header File for
- * ARMCM0 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct b/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct b/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct
new file mode 100644
index 0000000..9886def
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s
index 9fc447d..3333bc6 100644
--- a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s
+++ b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM0 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMCM0 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,186 +58,102 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
+ MEND
-Default_Handler PROC
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+; Default exception/interrupt handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6.S b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6.S
new file mode 100644
index 0000000..a217856
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6.S
@@ -0,0 +1,176 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6_sct.S b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6_sct.S
new file mode 100644
index 0000000..eb5fa55
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_ac6_sct.S
@@ -0,0 +1,131 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.c b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.c
new file mode 100644
index 0000000..f796faf
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.c
@@ -0,0 +1,136 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.s b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.s
new file mode 100644
index 0000000..640ad88
--- /dev/null
+++ b/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0_sct.s
@@ -0,0 +1,123 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S
index 9c0daba..686d3da 100644
--- a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S
+++ b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM0.s
+ * @file startup_ARMCM0.S
* @brief CMSIS Core Device Startup File for
- * ARMCM0 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,288 +23,273 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv6-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv6-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
- subs r3, r2
- ble .L_loop1_done
+ subs r3, r2
+ ble .L_loop1_done
.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
.L_loop2_0_done:
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
+ movs r0, 0
+ subs r2, r1
+ ble .L_loop3_done
.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
index 6be97a4..b4fcfce 100644
--- a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
+++ b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM0.s
+ * @file startup_ARMCM0.c
* @brief CMSIS Core Device Startup File for
- * ARMCM0 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,94 +86,59 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M0 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM0 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M0 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
};
@@ -184,41 +149,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -228,40 +194,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -270,15 +236,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -287,5 +246,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s b/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s
index 34caef0..c74cee0 100644
--- a/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s
+++ b/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM0 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMCM0 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,232 +39,109 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0
- DCD 0
- DCD 0
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD 0
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 ( 22) ; Interrupts 10 .. 31 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM0/Source/system_ARMCM0.c b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
index 0703ff8..66a364c 100644
--- a/Device/ARM/ARMCM0/Source/system_ARMCM0.c
+++ b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
- * ARMCM0 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -28,15 +28,15 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h b/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
index 167d549..b406733 100644
--- a/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
+++ b/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM0plus.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 31 are left out */
} IRQn_Type;
@@ -100,10 +88,10 @@
#endif
-/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
-#define __CM0PLUS_REV 0x0000U /* Core revision r0p0 */
-#define __MPU_PRESENT 0U /* MPU present or not */
-#define __VTOR_PRESENT 0U /* VTOR present or not */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */
+#define __MPU_PRESENT 0U /* no MPU present */
+#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -111,97 +99,6 @@
#include "system_ARMCM0plus.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,52 +119,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h b/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
index 4d7d13f..802cbfe 100644
--- a/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
+++ b/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file ARMCM0plus.h
+ * @file ARMCM0plus_MPU.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0plus Device (configured for CM0+ with MPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,8 +23,8 @@
* limitations under the License.
*/
-#ifndef ARMCM0plus_H
-#define ARMCM0plus_H
+#ifndef ARMCM0plus_MPU_H
+#define ARMCM0plus_MPU_H
#ifdef __cplusplus
extern "C" {
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 31 are left out */
} IRQn_Type;
@@ -100,10 +88,10 @@
#endif
-/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
-#define __CM0PLUS_REV 0x0000U /* Core revision r0p0 */
-#define __MPU_PRESENT 1U /* MPU present or not */
-#define __VTOR_PRESENT 0U /* VTOR present or not */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
+#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -111,97 +99,6 @@
#include "system_ARMCM0plus.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,54 +119,8 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
-#endif /* ARMCM0plus_H */
+#endif /* ARMCM0plus_MPU_H */
diff --git a/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h b/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
index fa1c5cb..214799c 100644
--- a/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
+++ b/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM0plus.h
* @brief CMSIS Device System Header File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct b/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct b/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct
new file mode 100644
index 0000000..4381a2c
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s
index 3b78e6e..ede76a2 100644
--- a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s
+++ b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM0plus.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM0plus Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMCM0plus Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,186 +58,102 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
+ MEND
-Default_Handler PROC
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+; Default exception/interrupt handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6.S b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6.S
new file mode 100644
index 0000000..0c8aacd
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6.S
@@ -0,0 +1,176 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0plus.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6_sct.S b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6_sct.S
new file mode 100644
index 0000000..c2d8c44
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_ac6_sct.S
@@ -0,0 +1,131 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0plus_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.c b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.c
new file mode 100644
index 0000000..f36cd7f
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.c
@@ -0,0 +1,136 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0plus_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.s b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.s
new file mode 100644
index 0000000..d36b587
--- /dev/null
+++ b/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus_sct.s
@@ -0,0 +1,123 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0plus_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0plus Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S
index 7fa38a9..e506264 100644
--- a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S
+++ b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file startup_ARMCM0plus.s
* @brief CMSIS Core Device Startup File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,288 +23,273 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv6-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv6-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
- subs r3, r2
- ble .L_loop1_done
+ subs r3, r2
+ ble .L_loop1_done
.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
.L_loop2_0_done:
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
+ movs r0, 0
+ subs r2, r1
+ ble .L_loop3_done
.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
index 7c927f8..88451d6 100644
--- a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
+++ b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file startup_ARMCM0plus.s
* @brief CMSIS Core Device Startup File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,94 +86,59 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M0+ Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM0plus Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M0+ Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
};
@@ -184,41 +149,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -228,40 +194,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -270,15 +236,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -287,5 +246,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s b/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s
index 4178ccc..9e315be 100644
--- a/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s
+++ b/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM0plus.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM0plus Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMCM0plus Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,232 +39,109 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0
- DCD 0
- DCD 0
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD 0
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 ( 22) ; Interrupts 10 .. 31 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
index 1bb66ec..837093b 100644
--- a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
+++ b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM0plus.c
* @brief CMSIS Device System Source File for
- * ARMCM0plus Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM0plus Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -28,9 +28,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMCM23/Include/ARMCM23.h b/Device/ARM/ARMCM23/Include/ARMCM23.h
index f599c2b..d07061d 100644
--- a/Device/ARM/ARMCM23/Include/ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/ARMCM23.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM23.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,29 @@
typedef enum IRQn
{
-/* -------------------- ARMCM23 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-
-/* -------------------- ARMCM23 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -101,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M23 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM23_REV 0x0100U /* Core revision r1p0 */
#define __SAUREGION_PRESENT 0U /* SAU regions are not present */
#define __MPU_PRESENT 1U /* MPU is present */
@@ -113,97 +100,6 @@
#include "system_ARMCM23.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -224,52 +120,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h b/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
index b0d3fb3..880f1ff 100644
--- a/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
+++ b/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file ARMCM23.h
+ * @file ARMCM23_TZ.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM23 Device (configured for TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,8 +23,8 @@
* limitations under the License.
*/
-#ifndef ARMCM23_H
-#define ARMCM23_H
+#ifndef ARMCM23_TZ_H
+#define ARMCM23_TZ_H
#ifdef __cplusplus
extern "C" {
@@ -35,42 +35,29 @@
typedef enum IRQn
{
-/* -------------------- ARMCM23 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-
-/* -------------------- ARMCM23 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -101,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M23 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM23_REV 0x0100U /* Core revision r1p0 */
#define __SAUREGION_PRESENT 1U /* SAU regions are present */
#define __MPU_PRESENT 1U /* MPU is present */
@@ -113,97 +100,6 @@
#include "system_ARMCM23.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -224,54 +120,8 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
-#endif /* ARMCM23_H */
+#endif /* ARMCM23_TZ_H */
diff --git a/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h b/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
index 165b8f5..d3402da 100644
--- a/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file partition_ARMCM23.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version V5.00
- * @date 10. January 2018
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -708,374 +708,6 @@
*/
/*
-// <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8 0
-
-/*
-// Interrupts 0..31
-// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9 0
-
-/*
-// Interrupts 32..63
-// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10 0
-
-/*
-// Interrupts 64..95
-// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11 0
-
-/*
-// Interrupts 96..127
-// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12 0
-
-/*
-// Interrupts 128..159
-// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13 0
-
-/*
-// Interrupts 160..191
-// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14 0
-
-/*
-// Interrupts 192..223
-// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
-// <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15 0
-
-/*
-// Interrupts 224..255
-// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
-// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
-// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
-// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
-// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
-// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
-// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
-// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
-// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
-// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
-// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL 0x00000000
-
-/*
-// </e>
-*/
-
-/*
// </h>
*/
@@ -1193,38 +825,6 @@
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
- #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
- NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
- NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
- NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
- NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
- NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
- NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
- NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
- #endif
-
- #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
- NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
- #endif
-
/* repeat this for all possible ITNS elements */
}
diff --git a/Device/ARM/ARMCM23/Include/system_ARMCM23.h b/Device/ARM/ARMCM23/Include/system_ARMCM23.h
index f584ff3..68da1f9 100644
--- a/Device/ARM/ARMCM23/Include/system_ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/system_ARMCM23.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM23.h
* @brief CMSIS Device System Header File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct b/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct
new file mode 100644
index 0000000..694b9dd
--- /dev/null
+++ b/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct
@@ -0,0 +1,73 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+; *(Veneer$$CMSE) ; uncomment for secure applications
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s
index 3f2eb00..d454154 100644
--- a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s
+++ b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM23.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM23 Device Series
-; * @version V5.00
-; * @date 21. October 2016
+; * ARMCM23 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,186 +58,105 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =__stack_limit
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
+ MEND
-Default_Handler PROC
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+; Default exception/interrupt handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6.S b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6.S
new file mode 100644
index 0000000..ae615b3
--- /dev/null
+++ b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6.S
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file startup_ARMCM23.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =__stack_limit
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6_sct.S b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6_sct.S
new file mode 100644
index 0000000..93cd384
--- /dev/null
+++ b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMCM23_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$base /* Linker symbol from scatter file */
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$base
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.c b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.c
new file mode 100644
index 0000000..fa9fb4c
--- /dev/null
+++ b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.c
@@ -0,0 +1,138 @@
+/**************************************************************************//**
+ * @file startup_ARMCM23_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+#define __stack_limit Image$$ARM_LIB_STACK$$ZI$$Base
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ __set_MSPLIM((uint32_t)&__stack_limit);
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.s b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.s
new file mode 100644
index 0000000..b887da8
--- /dev/null
+++ b/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM23_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM23 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Base|| ; Linker symbol from scatter file
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =||Image$$ARM_LIB_STACK$$ZI$$Base||
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld
index b987fd1..f2c16dd 100644
--- a/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -76,6 +67,17 @@
KEEP(*(.eh_frame*))
} > FLASH
+/* SG veneers:
+ All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ must be set, either with the command line option ‘--section-start’ or in a linker script,
+ to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -122,7 +124,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +175,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S
index 60084bf..fb84bc2 100644
--- a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S
+++ b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM23.s
+ * @file startup_ARMCM23.S
* @brief CMSIS Core Device Startup File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 21. October 2016
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,288 +23,276 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv6-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv8-m.base
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
- subs r3, r2
- ble .L_loop1_done
+ subs r3, r2
+ ble .L_loop1_done
.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
.L_loop2_0_done:
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
+ movs r0, 0
+ subs r2, r1
+ ble .L_loop3_done
.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ ldr r0, =__StackLimit
+ msr msplim, r0
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ bl SystemInit
+ bl _start
- .pool
- .size Reset_Handler, . - Reset_Handler
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
index 8580338..deec98a 100644
--- a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
+++ b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM23.s
+ * @file startup_ARMCM23.c
* @brief CMSIS Core Device Startup File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -39,6 +43,7 @@
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,94 +86,59 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* ARMCM23 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM23 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* ARMCM23 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
};
@@ -184,41 +149,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -228,40 +194,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -270,15 +236,10 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
+ __set_MSPLIM((uint32_t)&__StackLimit);
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -287,5 +248,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s b/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s
index 40fd786..baa9cad 100644
--- a/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s
+++ b/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM23.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM23 Device Series
-; * @version V5.00
-; * @date 21. October 2016
+; * ARMCM23 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,234 +39,109 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0
- DCD 0
- DCD 0
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD 0
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM23/Source/system_ARMCM23.c b/Device/ARM/ARMCM23/Source/system_ARMCM23.c
index 32e8946..5443ca8 100644
--- a/Device/ARM/ARMCM23/Source/system_ARMCM23.c
+++ b/Device/ARM/ARMCM23/Source/system_ARMCM23.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM23.c
* @brief CMSIS Device System Source File for
- * ARMCM23 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM23 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -38,9 +38,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMCM3/Include/ARMCM3.h b/Device/ARM/ARMCM3/Include/ARMCM3.h
index 0fb5ea7..44c0c23 100644
--- a/Device/ARM/ARMCM3/Include/ARMCM3.h
+++ b/Device/ARM/ARMCM3/Include/ARMCM3.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM3.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM3 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM3 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,10 +88,10 @@
#endif
-/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM3_REV 0x0201U /* Core revision r2p1 */
#define __MPU_PRESENT 1U /* MPU present */
-#define __VTOR_PRESENT 1U /* VTOR present or not */
+#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -111,97 +99,6 @@
#include "system_ARMCM3.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,52 +119,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM3/Include/system_ARMCM3.h b/Device/ARM/ARMCM3/Include/system_ARMCM3.h
index 3835987..a91db7c 100644
--- a/Device/ARM/ARMCM3/Include/system_ARMCM3.h
+++ b/Device/ARM/ARMCM3/Include/system_ARMCM3.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM3.h
* @brief CMSIS Device System Header File for
- * ARMCM3 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct b/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct b/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct
new file mode 100644
index 0000000..7d5fd25
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s
index 16e56b0..2bf6f19 100644
--- a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s
+++ b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM3 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMCM3 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,206 +58,106 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6.S b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6.S
new file mode 100644
index 0000000..f18b32a
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6.S
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file startup_ARMCM3.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6_sct.S b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6_sct.S
new file mode 100644
index 0000000..6317033
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMCM3_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.c b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.c
new file mode 100644
index 0000000..56f996a
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.c
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file startup_ARMCM3_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.s b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.s
new file mode 100644
index 0000000..3eb6200
--- /dev/null
+++ b/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S
index 64bb5eb..64ca45e 100644
--- a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S
+++ b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM3.s
+ * @file startup_ARMCM3.S
* @brief CMSIS Core Device Startup File for
- * ARMCM3 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,282 +23,268 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv7-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
index d7de2ab..8290157 100644
--- a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
+++ b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM3.s
+ * @file startup_ARMCM3.c
* @brief CMSIS Core Device Startup File for
- * ARMCM3 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,98 +86,63 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M3 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM3 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M3 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
};
@@ -188,41 +153,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -232,40 +198,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -274,15 +240,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -291,5 +250,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s b/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s
index 81f28ce..a0d2505 100644
--- a/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s
+++ b/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM3 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMCM3 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,254 +39,117 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM3/Source/system_ARMCM3.c b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
index 3f9abfd..f56b85f 100644
--- a/Device/ARM/ARMCM3/Source/system_ARMCM3.c
+++ b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
- * ARMCM3 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -28,9 +28,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33.h b/Device/ARM/ARMCM33/Include/ARMCM33.h
index e3353c7..9593c61 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM33.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM33 Device Series (configured for ARMCM33 without FPU, without DSP extension, without TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, without TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- ARMCM33 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMCM33 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -115,97 +103,6 @@
#include "system_ARMCM33.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
index 16d39f3..d303bea 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM33_DSP_FP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM33 Device Series (configured for ARMCM33 with FPU, with DSP extension)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- ARMCM33 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMCM33 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -115,97 +103,6 @@
#include "system_ARMCM33.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
index 6fd00e4..0d78c79 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM33_DSP_FP_TZ.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM33 Device Series (configured for ARMCM33 with FPU, with DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- ARMCM33 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMCM33 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -115,97 +103,6 @@
#include "system_ARMCM33.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h b/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
index e448230..3912a11 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM33_TZ.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM33 Device Series (configured for ARMCM33 without FPU, without DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- ARMCM33 Processor Exceptions Numbers -------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMCM33 Specific Interrupt Numbers ---------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -115,97 +103,6 @@
#include "system_ARMCM33.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
index f065734..d338254 100644
--- a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file partition_ARMCM33.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version V5.0.1
- * @date 10. January 2018
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -734,7 +734,7 @@
#define NVIC_INIT_ITNS8 0
/*
-// Interrupts 0..31
+// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
#define NVIC_INIT_ITNS9 0
/*
-// Interrupts 32..63
+// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
#define NVIC_INIT_ITNS10 0
/*
-// Interrupts 64..95
+// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
#define NVIC_INIT_ITNS11 0
/*
-// Interrupts 96..127
+// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
#define NVIC_INIT_ITNS12 0
/*
-// Interrupts 128..159
+// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
#define NVIC_INIT_ITNS13 0
/*
-// Interrupts 160..191
+// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
#define NVIC_INIT_ITNS14 0
/*
-// Interrupts 192..223
+// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
#define NVIC_INIT_ITNS15 0
/*
-// Interrupts 224..255
+// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
diff --git a/Device/ARM/ARMCM33/Include/system_ARMCM33.h b/Device/ARM/ARMCM33/Include/system_ARMCM33.h
index c4b7197..42d07ec 100644
--- a/Device/ARM/ARMCM33/Include/system_ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/system_ARMCM33.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM33.h
* @brief CMSIS Device System Header File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct b/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct
new file mode 100644
index 0000000..6014a59
--- /dev/null
+++ b/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct
@@ -0,0 +1,73 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+; *(Veneer$$CMSE) ; uncomment for secure applications
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s
index 1e28f2e..7e41339 100644
--- a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s
+++ b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM33.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM33 Device Series
-; * @version V5.00
-; * @date 21. October 2016
+; * ARMCM33 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,211 +58,110 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD SecureFault_Handler ; -9 Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =__stack_limit
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6.S b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6.S
new file mode 100644
index 0000000..9aa1302
--- /dev/null
+++ b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6.S
@@ -0,0 +1,184 @@
+/**************************************************************************//**
+ * @file startup_ARMCM33.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =__stack_limit
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6_sct.S b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6_sct.S
new file mode 100644
index 0000000..447e3c5
--- /dev/null
+++ b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_ac6_sct.S
@@ -0,0 +1,139 @@
+/**************************************************************************//**
+ * @file startup_ARMCM33_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$base
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.c b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.c
new file mode 100644
index 0000000..e5de963
--- /dev/null
+++ b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.c
@@ -0,0 +1,143 @@
+/**************************************************************************//**
+ * @file startup_ARMCM33_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+#define __stack_limit Image$$ARM_LIB_STACK$$ZI$$Base
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ __set_MSPLIM((uint32_t)&__stack_limit);
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.s b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.s
new file mode 100644
index 0000000..42df219
--- /dev/null
+++ b/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33_sct.s
@@ -0,0 +1,132 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM33_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM33 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD SecureFault_Handler ; -9 Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Base|| ; Linker symbol from scatter file
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =||Image$$ARM_LIB_STACK$$ZI$$Base||
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld
index b987fd1..f2c16dd 100644
--- a/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -76,6 +67,17 @@
KEEP(*(.eh_frame*))
} > FLASH
+/* SG veneers:
+ All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ must be set, either with the command line option ‘--section-start’ or in a linker script,
+ to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -122,7 +124,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +175,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S
index 6cf62be..115557d 100644
--- a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S
+++ b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM33.s
+ * @file startup_ARMCM33.S
* @brief CMSIS Core Device Startup File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 21. October 2016
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,283 +23,272 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv8-m.main
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ ldr r0, =__StackLimit
+ msr msplim, r0
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ bl SystemInit
+ bl _start
- .pool
- .size Reset_Handler, . - Reset_Handler
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
index e8411d6..eab9755 100644
--- a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
+++ b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM33.s
+ * @file startup_ARMCM33.c
* @brief CMSIS Core Device Startup File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -39,6 +43,7 @@
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,99 +86,64 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* ARMCM33 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM33 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* ARMCM33 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- SecureFault_Handler, /* Secure Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
};
@@ -189,41 +154,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -233,40 +199,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -275,15 +241,10 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
+ __set_MSPLIM((uint32_t)&__StackLimit);
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -292,5 +253,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s b/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s
index 505632c..5d6bdc4 100644
--- a/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s
+++ b/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM33.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM33 Device Series
-; * @version V5.00
-; * @date 21. October 2016
+; * ARMCM33 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,259 +39,119 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD SecureFault_Handler
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD SecureFault_Handler ; -9 Security Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (470) ; Interrupts 10 .. 480 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SecureFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SecureFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SecureFault_Handler
- B SecureFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM33/Source/system_ARMCM33.c b/Device/ARM/ARMCM33/Source/system_ARMCM33.c
index 9006f8e..1767923 100644
--- a/Device/ARM/ARMCM33/Source/system_ARMCM33.c
+++ b/Device/ARM/ARMCM33/Source/system_ARMCM33.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM33.c
* @brief CMSIS Device System Source File for
- * ARMCM33 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM33 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -46,9 +46,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMCM4/Include/ARMCM4.h b/Device/ARM/ARMCM4/Include/ARMCM4.h
index 68e96fc..c1a9877 100644
--- a/Device/ARM/ARMCM4/Include/ARMCM4.h
+++ b/Device/ARM/ARMCM4/Include/ARMCM4.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM4.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM4 Device Series (configured for CM4 without FPU)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM4 Device (configured for CM4 without FPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM4 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM4_REV 0x0001U /* Core revision r0p1 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
@@ -112,97 +100,6 @@
#include "system_ARMCM4.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -223,52 +120,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM4/Include/ARMCM4_FP.h b/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
index 61af3b9..6e53824 100644
--- a/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
+++ b/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM4_FP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM4 Device Series (configured for CM4 with FPU)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM4 Device (configured for CM4 with FPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM4 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM4_REV 0x0001U /* Core revision r0p1 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
@@ -112,97 +100,6 @@
#include "system_ARMCM4.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -223,52 +120,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM4/Include/system_ARMCM4.h b/Device/ARM/ARMCM4/Include/system_ARMCM4.h
index f0fe73d..2557390 100644
--- a/Device/ARM/ARMCM4/Include/system_ARMCM4.h
+++ b/Device/ARM/ARMCM4/Include/system_ARMCM4.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM4.h
* @brief CMSIS Device System Header File for
- * ARMCM4 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct b/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct b/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct
new file mode 100644
index 0000000..434a755
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s
index dae6439..f5270c0 100644
--- a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s
+++ b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM4 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMCM4 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,206 +58,106 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6.S b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6.S
new file mode 100644
index 0000000..eeea868
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6.S
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file startup_ARMCM4.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6_sct.S b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6_sct.S
new file mode 100644
index 0000000..3470379
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMCM4_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.c b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.c
new file mode 100644
index 0000000..77512a1
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.c
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file startup_ARMCM4_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.s b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.s
new file mode 100644
index 0000000..94247e4
--- /dev/null
+++ b/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM4_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
index b987fd1..d6a1f96 100644
--- a/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
@@ -5,9 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
@@ -33,13 +30,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +42,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +112,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +163,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S
index 886bdd7..3f884f5 100644
--- a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S
+++ b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM4.s
+ * @file startup_ARMCM4.S
* @brief CMSIS Core Device Startup File for
- * ARMCM4 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,282 +23,268 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv7e-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
index 3b967c8..8afd38d 100644
--- a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
+++ b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM4.s
+ * @file startup_ARMCM4.c
* @brief CMSIS Core Device Startup File for
- * ARMCM4 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,98 +86,63 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M4 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM4 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M4 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
};
@@ -188,41 +153,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -232,40 +198,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -274,15 +240,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -291,5 +250,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s b/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s
index 689e85d..eaed8da 100644
--- a/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s
+++ b/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM4 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMCM4 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,254 +39,117 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM4/Source/system_ARMCM4.c b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
index 7f634ab..731facd 100644
--- a/Device/ARM/ARMCM4/Source/system_ARMCM4.c
+++ b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
- * ARMCM4 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -34,9 +34,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -49,7 +49,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
@@ -71,8 +71,8 @@
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
- SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
- (3U << 11U*2U) ); /* set CP11 Full Access */
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7.h b/Device/ARM/ARMCM7/Include/ARMCM7.h
index 827e21b..4db9527 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM7.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM7 Device Series (configured for CM7 without FPU)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device (configured for CM7 without FPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM7 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M7 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM7_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
@@ -117,97 +105,6 @@
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -228,52 +125,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
index e8a1ea1..d1626fa 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM7_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM7 Device Series (configured for CM7 with double precision FPU)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device (configured for CM7 with double precision FPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM7 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M7 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM7_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
@@ -117,97 +105,6 @@
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -228,52 +125,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
index 3e78430..c993210 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMCM7_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMCM7 Device Series (configured for CM7 with single precision FPU)
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device (configured for CM7 with single precision FPU)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMCM7 Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M7 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM7_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
@@ -117,97 +105,6 @@
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -228,52 +125,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMCM7/Include/system_ARMCM7.h b/Device/ARM/ARMCM7/Include/system_ARMCM7.h
index 66291a6..ec831e0 100644
--- a/Device/ARM/ARMCM7/Include/system_ARMCM7.h
+++ b/Device/ARM/ARMCM7/Include/system_ARMCM7.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM7.h
* @brief CMSIS Device System Header File for
- * ARMCM7 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct b/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct b/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct
new file mode 100644
index 0000000..ad5c0f6
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s
index b69f038..abddc8d 100644
--- a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s
+++ b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM7 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMCM7 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,206 +58,106 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6.S b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6.S
new file mode 100644
index 0000000..dbd282b
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6.S
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file startup_ARMCM7.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6_sct.S b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6_sct.S
new file mode 100644
index 0000000..e8aed23
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMCM7_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.c b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.c
new file mode 100644
index 0000000..89ddaf8
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.c
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file startup_ARMCM7_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.s b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.s
new file mode 100644
index 0000000..04b2ad2
--- /dev/null
+++ b/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM7_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM7 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S
index 3f4ac77..bfe2513 100644
--- a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S
+++ b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMCM7.s
+ * @file startup_ARMCM7.S
* @brief CMSIS Core Device Startup File for
- * ARMCM7 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,282 +23,268 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv7e-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
index 1c050b8..8487c28 100644
--- a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
+++ b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMCM7.s
+ * @file startup_ARMCM7.c
* @brief CMSIS Core Device Startup File for
- * ARMCM7 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,98 +86,63 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M7 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMCM7 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M7 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
};
@@ -188,41 +153,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -232,40 +198,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -274,15 +240,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -291,5 +250,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s b/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s
index 002c438..69ce2ac 100644
--- a/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s
+++ b/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
-; * ARMCM7 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMCM7 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,254 +39,117 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMCM7/Source/system_ARMCM7.c b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
index 9245dcf..69e2a8d 100644
--- a/Device/ARM/ARMCM7/Source/system_ARMCM7.c
+++ b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMCM7.c
* @brief CMSIS Device System Source File for
- * ARMCM7 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -36,9 +36,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -51,7 +51,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
@@ -73,8 +73,8 @@
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
- SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
- (3U << 11U*2U) ); /* set CP11 Full Access */
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
diff --git a/Device/ARM/ARMSC000/Include/ARMSC000.h b/Device/ARM/ARMSC000/Include/ARMSC000.h
index ae0ec25..f7e77b1 100644
--- a/Device/ARM/ARMSC000/Include/ARMSC000.h
+++ b/Device/ARM/ARMSC000/Include/ARMSC000.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMSC000.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMSC000 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* --------------------- SC000 Processor Exceptions Numbers --------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* ---------------------- ARMSC000 Specific Interrupt Numbers ------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 31 are left out */
} IRQn_Type;
@@ -100,7 +88,7 @@
#endif
-/* -------- Configuration of the SC000 Processor and Core Peripherals ----------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __SC000_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present*/
@@ -111,97 +99,6 @@
#include "system_ARMSC000.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,52 +119,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMSC000/Include/system_ARMSC000.h b/Device/ARM/ARMSC000/Include/system_ARMSC000.h
index 4e05e35..46a00c5 100644
--- a/Device/ARM/ARMSC000/Include/system_ARMSC000.h
+++ b/Device/ARM/ARMSC000/Include/system_ARMSC000.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMSC000.h
* @brief CMSIS Device System Header File for
- * ARMSC000 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct b/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct b/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct
new file mode 100644
index 0000000..88fc3d7
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=sc000 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s
index 3cd6b23..886eced 100644
--- a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s
+++ b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMSC000.s
; * @brief CMSIS Core Device Startup File for
-; * ARMSC000 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMSC000 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,186 +58,102 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
+ MEND
-Default_Handler PROC
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+; Default exception/interrupt handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6.S b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6.S
new file mode 100644
index 0000000..8d486c7
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6.S
@@ -0,0 +1,176 @@
+/**************************************************************************//**
+ * @file startup_ARMSC000.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6_sct.S b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6_sct.S
new file mode 100644
index 0000000..5d92326
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_ac6_sct.S
@@ -0,0 +1,131 @@
+/**************************************************************************//**
+ * @file startup_ARMSC000_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv6-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.c b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.c
new file mode 100644
index 0000000..776dfba
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.c
@@ -0,0 +1,136 @@
+/**************************************************************************//**
+ * @file startup_ARMSC000_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.s b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.s
new file mode 100644
index 0000000..cf34b88
--- /dev/null
+++ b/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000_sct.s
@@ -0,0 +1,123 @@
+;/**************************************************************************//**
+; * @file startup_ARMSC000_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMSC000 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld b/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S
index 5dea413..5a816c1 100644
--- a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S
+++ b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file startup_ARMSC000.s
* @brief CMSIS Core Device Startup File for
- * ARMSC000 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,288 +23,273 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv6-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv6-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space ( 22 * 4) /* Interrupts 10 .. 31 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
- subs r3, r2
- ble .L_loop1_done
+ subs r3, r2
+ ble .L_loop1_done
.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
.L_loop2_0_done:
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
+ movs r0, 0
+ subs r2, r1
+ ble .L_loop3_done
.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
index 6490592..61a222f 100644
--- a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
+++ b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file startup_ARMSC000.s
* @brief CMSIS Core Device Startup File for
- * ARMSC000 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,94 +86,59 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M0 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/*ARMSC000 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M0 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[ 48];
+ const pFunc __Vectors[ 48] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 31 are left out */
};
@@ -184,41 +149,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -228,40 +194,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -270,15 +236,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -287,5 +246,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s b/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s
index f8dc0f1..d884cbd 100644
--- a/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s
+++ b/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMSC000.s
; * @brief CMSIS Core Device Startup File for
-; * for ARMSC000 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * for ARMSC000 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,232 +39,109 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0
- DCD 0
- DCD 0
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD 0
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 ( 22) ; Interrupts 10 .. 31 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMSC000/Source/system_ARMSC000.c b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
index af3668e..067edc4 100644
--- a/Device/ARM/ARMSC000/Source/system_ARMSC000.c
+++ b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMSC000.c
* @brief CMSIS Device System Source File for
- * for ARMSC000 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * for ARMSC000 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -28,15 +28,15 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMSC300/Include/ARMSC300.h b/Device/ARM/ARMSC300/Include/ARMSC300.h
index 74dc714..9486749 100644
--- a/Device/ARM/ARMSC300/Include/ARMSC300.h
+++ b/Device/ARM/ARMSC300/Include/ARMSC300.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMSC300.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMSC300 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,41 +35,29 @@
typedef enum IRQn
{
-/* --------------------- SC300 Processor Exceptions Numbers --------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* --------------------- ARMSC300 Specific Interrupt Numbers -------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 224 are left out */
} IRQn_Type;
@@ -100,10 +88,10 @@
#endif
-/* -------- Configuration of the SC300 Processor and Core Peripherals ----------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __SC300_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
-#define __VTOR_PRESENT 1U /* VTOR present or not */
+#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -111,97 +99,6 @@
#include "system_ARMSC300.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -222,52 +119,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMSC300/Include/system_ARMSC300.h b/Device/ARM/ARMSC300/Include/system_ARMSC300.h
index f9df630..2b10071 100644
--- a/Device/ARM/ARMSC300/Include/system_ARMSC300.h
+++ b/Device/ARM/ARMSC300/Include/system_ARMSC300.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMSC300.h
* @brief CMSIS Device System Header File for
- * ARMSC300 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct b/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct
new file mode 100644
index 0000000..6881119
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct
@@ -0,0 +1,72 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct b/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct
new file mode 100644
index 0000000..b4073a8
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct
@@ -0,0 +1,72 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=sc300 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s
index e6675e2..69e15b7 100644
--- a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s
+++ b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMSC300.s
; * @brief CMSIS Core Device Startup File for
-; * ARMSC300 Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMSC300 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,206 +58,106 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6.S b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6.S
new file mode 100644
index 0000000..dbe9b6c
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6.S
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file startup_ARMSC300.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6_sct.S b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6_sct.S
new file mode 100644
index 0000000..5e7f907
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMSC300_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.c b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.c
new file mode 100644
index 0000000..c73e709
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.c
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file startup_ARMSC300_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.s b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.s
new file mode 100644
index 0000000..558833d
--- /dev/null
+++ b/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMSC300_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMSC300 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld b/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
index b987fd1..d5f780f 100644
--- a/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -122,7 +113,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +164,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S
index a5a48b6..7a79a4f 100644
--- a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S
+++ b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMSC300.s
+ * @file startup_ARMSC300.S
* @brief CMSIS Core Device Startup File for
- * ARMSC300 Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,282 +23,268 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv7-m
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ bl SystemInit
+ bl _start
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .pool
- .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
index bb1ef02..95422d3 100644
--- a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
+++ b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMSC300.s
+ * @file startup_ARMSC300.c
* @brief CMSIS Core Device Startup File for
- * ARMSC300 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -40,6 +44,7 @@
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,98 +86,63 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Cortex-M3 Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMSC300 Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Cortex-M3 Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[240];
+ const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 224 are left out */
};
@@ -188,41 +153,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -232,40 +198,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -274,15 +240,8 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -291,5 +250,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s b/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s
index 895e1b2..6b132e0 100644
--- a/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s
+++ b/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMSC300.s
; * @brief CMSIS Core Device Startup File for
-; * for ARMSC300 Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMSC300 Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,254 +39,117 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (214) ; Interrupts 10 .. 224 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMSC300/Source/system_ARMSC300.c b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
index d81c17e..79f763c 100644
--- a/Device/ARM/ARMSC300/Source/system_ARMSC300.c
+++ b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMSC300.c
* @brief CMSIS Device System Source File for
- * ARMSC300 Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMSC300 Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -28,9 +28,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
index 625edce..36ecddf 100644
--- a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMv8MBL.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MBL Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,29 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MBL Processor Exceptions Numbers ------------------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-
-/* -------------------- ARMv8MBL Specific Interrupt Numbers --------------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,11 +88,11 @@
#endif
-/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
#define __SAUREGION_PRESENT 1U /* SAU regions are present */
-#define __MPU_PRESENT 0U /* MPU present or not */
-#define __VTOR_PRESENT 0U /* VTOR present or not */
+#define __MPU_PRESENT 0U /* no MPU present */
+#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
@@ -113,97 +100,6 @@
#include "system_ARMv8MBL.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -224,52 +120,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
index 27603ae..bc7d27a 100644
--- a/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file partition_ARMv8MBL.h
- * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8M
- * @version V5.00
- * @date 10. January 2018
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8MBL
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -713,7 +713,7 @@
#define NVIC_INIT_ITNS8 0
/*
-// Interrupts 0..31
+// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -759,7 +759,7 @@
#define NVIC_INIT_ITNS9 0
/*
-// Interrupts 32..63
+// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -805,7 +805,7 @@
#define NVIC_INIT_ITNS10 0
/*
-// Interrupts 64..95
+// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -851,7 +851,7 @@
#define NVIC_INIT_ITNS11 0
/*
-// Interrupts 96..127
+// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -897,7 +897,7 @@
#define NVIC_INIT_ITNS12 0
/*
-// Interrupts 128..159
+// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -943,7 +943,7 @@
#define NVIC_INIT_ITNS13 0
/*
-// Interrupts 160..191
+// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -989,7 +989,7 @@
#define NVIC_INIT_ITNS14 0
/*
-// Interrupts 192..223
+// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1035,7 +1035,7 @@
#define NVIC_INIT_ITNS15 0
/*
-// Interrupts 224..255
+// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
diff --git a/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
index 9822a36..f732185 100644
--- a/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMv8MBL.h
* @brief CMSIS Device System Header File for
- * ARMv8MBL Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct b/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct
new file mode 100644
index 0000000..90cbc5a
--- /dev/null
+++ b/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct
@@ -0,0 +1,73 @@
+#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+; *(Veneer$$CMSE) ; uncomment for secure applications
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s
index 5b9352a..12fb6e3 100644
--- a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s
+++ b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMv8MBL.s
; * @brief CMSIS Core Device Startup File for
-; * ARMv8MBL Device Series
-; * @version V5.00
-; * @date 25. April 2016
+; * ARMv8MBL Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,186 +58,105 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =__stack_limit
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
+ MEND
-Default_Handler PROC
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+; Default exception/interrupt handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6.S b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6.S
new file mode 100644
index 0000000..9f23636
--- /dev/null
+++ b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6.S
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MBL.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =__stack_limit
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6_sct.S b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6_sct.S
new file mode 100644
index 0000000..6bea44c
--- /dev/null
+++ b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_ac6_sct.S
@@ -0,0 +1,135 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MBL_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv8-m.base
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$base /* Linker symbol from scatter file */
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$base
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.c b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.c
new file mode 100644
index 0000000..71df2f1
--- /dev/null
+++ b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.c
@@ -0,0 +1,138 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MBL_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+#define __stack_limit Image$$ARM_LIB_STACK$$ZI$$Base
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ __set_MSPLIM((uint32_t)&__stack_limit);
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.s b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.s
new file mode 100644
index 0000000..801cfc0
--- /dev/null
+++ b/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL_sct.s
@@ -0,0 +1,127 @@
+;/**************************************************************************//**
+; * @file startup_ARMv8MBL_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMv8MBL Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Base|| ; Linker symbol from scatter file
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =||Image$$ARM_LIB_STACK$$ZI$$Base||
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld b/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
index b987fd1..f2c16dd 100644
--- a/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -76,6 +67,17 @@
KEEP(*(.eh_frame*))
} > FLASH
+/* SG veneers:
+ All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ must be set, either with the command line option ‘--section-start’ or in a linker script,
+ to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -122,7 +124,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +175,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S
index ace43f9..abe4f57 100644
--- a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S
+++ b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
- * @file startup_ARMv8MBL.s
+ * @file startup_ARMv8MBL.S
* @brief CMSIS Core Device Startup File for
- * ARMv8MBL Device Series
- * @version V5.00
- * @date 25. April 2016
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,288 +23,276 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv6-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv8-m.base
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
- subs r3, r2
- ble .L_loop1_done
+ subs r3, r2
+ ble .L_loop1_done
.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
.L_loop2_0_done:
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
+ movs r0, 0
+ subs r2, r1
+ ble .L_loop3_done
.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ ldr r0, =__StackLimit
+ msr msplim, r0
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ bl SystemInit
+ bl _start
- .pool
- .size Reset_Handler, . - Reset_Handler
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
index 0719fb9..3313414 100644
--- a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
+++ b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMv8MBL.s
+ * @file startup_ARMv8MBL.c
* @brief CMSIS Core Device Startup File for
- * ARMv8MBL Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -39,6 +43,7 @@
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,94 +86,59 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* ARMv8MBL Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMv8MBL Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* ARMv8MBL Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
};
@@ -184,41 +149,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -228,40 +194,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -270,15 +236,10 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
+ __set_MSPLIM((uint32_t)&__StackLimit);
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -287,5 +248,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s b/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s
index f4b83dc..420b7f2 100644
--- a/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s
+++ b/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMv8MBL.s
; * @brief CMSIS Core Device Startup File for
-; * ARMv8MBL Device Series
-; * @version V5.00
-; * @date 25. April 2016
+; * ARMv8MBL Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,234 +39,109 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0
- DCD 0
- DCD 0
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
__vector_table_0x1c
- DCD 0
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD 0
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (470) ; Interrupts 10 .. 480 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
index 10dfa0b..bf19506 100644
--- a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
+++ b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMv8MBL.c
* @brief CMSIS Device System Source File for
- * Armv8-M Baseline Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MBL Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -32,9 +32,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -47,7 +47,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML.h b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
index 3e6d101..51a979c 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMv8MML.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline without FPU, without DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device (configured for ARMv8MML without FPU, without DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,9 +89,9 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
-#define __SAUREGION_PRESENT 1U /* SAU regions are present */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
@@ -115,97 +103,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
index 33b8721..07d4c95 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMv8MML_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-MML Device Series (configured for Armv8-MML with double precision FPU, without DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device (configured for ARMv8MML with double precision FPU, without DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8 Mainline Specific Interrupt Numbers --------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -116,97 +104,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -227,52 +124,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
index 1d38d18..b384ea9 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file ARMv8MML.h
+ * @file ARMv8MML_DSP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline without FPU, with DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Mainline Device (configured for ARMv8MML without FPU, with DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,9 +89,9 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
-#define __SAUREGION_PRESENT 1U /* SAU regions are present */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
@@ -115,97 +103,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -226,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
index 0c816e2..e9cb095 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
@@ -1,9 +1,8 @@
/**************************************************************************//**
- * @file ARMv8MML_DP.h
+ * @file ARMv8MML_DSP_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with double precision FPU, with DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Mainline Device (configured for Armv8-M MainlineARMv8MML
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +34,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +88,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -116,97 +103,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -227,52 +123,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
index a534dd0..7fe514c 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file ARMv8MML_SP.h
+ * @file ARMv8MML_DSP_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with single precision FPU, with DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Mainline Device (configured for ARMv8MML with single precision FPU, with DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -116,97 +104,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -227,52 +124,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
index 490bde3..a087222 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file ARMv8MML_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with single precision FPU, without DSP extension, with TrustZone)
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device (configured for ARMv8MML with single precision FPU, without DSP extension, with TrustZone)
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,42 +35,30 @@
typedef enum IRQn
{
-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+/* ------------------- Processor Exceptions Numbers ----------------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
- WDT_IRQn = 0, /* Watchdog Timer Interrupt */
- RTC_IRQn = 1, /* Real Time Clock Interrupt */
- TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
- TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */
- MCIA_IRQn = 4, /* MCIa Interrupt */
- MCIB_IRQn = 5, /* MCIb Interrupt */
- UART0_IRQn = 6, /* UART0 Interrupt */
- UART1_IRQn = 7, /* UART1 Interrupt */
- UART2_IRQn = 8, /* UART2 Interrupt */
- UART4_IRQn = 9, /* UART4 Interrupt */
- AACI_IRQn = 10, /* AACI / AC97 Interrupt */
- CLCD_IRQn = 11, /* CLCD Combined Interrupt */
- ENET_IRQn = 12, /* Ethernet Interrupt */
- USBDC_IRQn = 13, /* USB Device Interrupt */
- USBHC_IRQn = 14, /* USB Host Controller Interrupt */
- CHLCD_IRQn = 15, /* Character LCD Interrupt */
- FLEXRAY_IRQn = 16, /* Flexray Interrupt */
- CAN_IRQn = 17, /* CAN Interrupt */
- LIN_IRQn = 18, /* LIN Interrupt */
- I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */
- CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */
- UART3_IRQn = 30, /* UART3 Interrupt */
- SPI_IRQn = 31 /* SPI Touchscreen Interrupt */
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
} IRQn_Type;
@@ -101,7 +89,7 @@
#endif
-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
@@ -116,97 +104,6 @@
#include "system_ARMv8MML.h" /* System Header */
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/* ================================================================================ */
-/* ================ CPU FPGA System (CPU_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
- __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
- uint32_t RESERVED0[2U];
- __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
- __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
- __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
- uint32_t RESERVED1[3U];
- __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
- __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
-} ARM_CPU_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ DUT FPGA System (DUT_SYS) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
- __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
- __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
- __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
- __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
- __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
- __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
-} ARM_DUT_SYS_TypeDef;
-
-
-/* ================================================================================ */
-/* ================ Timer (TIM) ================ */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
- __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
- __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
- __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
- __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
- __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
- __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
- __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
- __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
- __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
- __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
-} ARM_TIM_TypeDef;
-
-
-/* ================================================================================ */
-/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
-/* ================================================================================ */
-typedef struct
-{
- __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */
- union {
- __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
- __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
- };
- uint32_t RESERVED0[4U];
- __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */
- uint32_t RESERVED1[1U];
- __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
- __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
- __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
- __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
- __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */
- __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
- __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
- __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
- __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
- __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
- __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
-} ARM_UART_TypeDef;
-
-
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
@@ -227,52 +124,6 @@
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA memory map ------------------------------- */
-#define ARM_FLASH_BASE (0x00000000UL)
-#define ARM_RAM_BASE (0x20000000UL)
-#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
-#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
-
-#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL)
-#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL)
-
-/* -------------------------- DUT FPGA memory map ------------------------------- */
-#define ARM_APB_BASE (0x40000000UL)
-#define ARM_AHB_BASE (0x4FF00000UL)
-#define ARM_DMC_BASE (0x60000000UL)
-#define ARM_SMC_BASE (0xA0000000UL)
-
-#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL)
-#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL)
-#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL)
-#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL)
-#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL)
-#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL)
-#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL)
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-/* -------------------------- CPU FPGA Peripherals ------------------------------ */
-#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
-#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
-
-/* -------------------------- DUT FPGA Peripherals ------------------------------ */
-#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
-#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
-#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
-#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
-#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
-#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
-#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
index 1d1c4c2..9254c32 100644
--- a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file partition_ARMv8MML.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8-M Mainline
- * @version V5.0.1
- * @date 10. January 2018
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -734,7 +734,7 @@
#define NVIC_INIT_ITNS8 0
/*
-// Interrupts 0..31
+// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
#define NVIC_INIT_ITNS9 0
/*
-// Interrupts 32..63
+// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
#define NVIC_INIT_ITNS10 0
/*
-// Interrupts 64..95
+// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
#define NVIC_INIT_ITNS11 0
/*
-// Interrupts 96..127
+// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
#define NVIC_INIT_ITNS12 0
/*
-// Interrupts 128..159
+// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
#define NVIC_INIT_ITNS13 0
/*
-// Interrupts 160..191
+// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
#define NVIC_INIT_ITNS14 0
/*
-// Interrupts 192..223
+// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
#define NVIC_INIT_ITNS15 0
/*
-// Interrupts 224..255
+// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
diff --git a/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h b/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
index deff40d..bbd6381 100644
--- a/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMv8MML.h
* @brief CMSIS Device System Header File for
- * Armv8-M Mainline Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
diff --git a/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct b/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct
new file mode 100644
index 0000000..d00df4b
--- /dev/null
+++ b/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct
@@ -0,0 +1,73 @@
+#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+//#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+; *(Veneer$$CMSE) ; uncomment for secure applications
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s
index 68d56a7..43de19c 100644
--- a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s
+++ b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMv8MML.s
; * @brief CMSIS Core Device Startup File for
-; * ARMv8MML Device Series
-; * @version V5.00
-; * @date 02. March 2016
+; * ARMv8MML Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -23,32 +23,33 @@
; * limitations under the License.
; */
-;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Stack_Size EQU 0x00000400
+Stack_Size EQU 0x00000400
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
__initial_sp
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
-Heap_Size EQU 0x00000C00
+Heap_Size EQU 0x00000C00
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
-Heap_Mem SPACE Heap_Size
+Heap_Mem SPACE Heap_Size
__heap_limit
+ ENDIF
PRESERVE8
@@ -57,211 +58,110 @@
; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD SecureFault_Handler ; Secure Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD SecureFault_Handler ; -9 Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
-__Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
-
+ AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =__stack_limit
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-Default_Handler PROC
+; Default exception/interrupt handler
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT TIM0_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT MCIA_IRQHandler [WEAK]
- EXPORT MCIB_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT UART2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT AACI_IRQHandler [WEAK]
- EXPORT CLCD_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT USBDC_IRQHandler [WEAK]
- EXPORT USBHC_IRQHandler [WEAK]
- EXPORT CHLCD_IRQHandler [WEAK]
- EXPORT FLEXRAY_IRQHandler [WEAK]
- EXPORT CAN_IRQHandler [WEAK]
- EXPORT LIN_IRQHandler [WEAK]
- EXPORT I2C_IRQHandler [WEAK]
- EXPORT CPU_CLCD_IRQHandler [WEAK]
- EXPORT SPI_IRQHandler [WEAK]
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
- B .
-
- ENDP
-
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
ALIGN
-; User Initial Stack & Heap
+; User setup Stack & Heap
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
ENDIF
-
END
diff --git a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6.S b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6.S
new file mode 100644
index 0000000..225d188
--- /dev/null
+++ b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6.S
@@ -0,0 +1,184 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MML.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section STACK, "w",%nobits
+ .align 3
+__stack_limit:
+ .space Stack_Size
+ .size __stack_limit, . - __stack_limit
+__initial_sp:
+ .size __initial_sp, . - __initial_sp
+
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section HEAP, "w",%nobits
+ .align 3
+__heap_base:
+ .space Heap_Size
+ .size __heap_base, . - __heap_base
+__heap_limit:
+ .size __heap_limit, . - __heap_limit
+ .endif
+
+
+ .section RESET
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __initial_sp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =__stack_limit
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+/* User setup Stack & Heap */
+
+ .global __stack_limit
+ .global __initial_sp
+ .if Heap_Size != 0 /* Heap is provided */
+ .global __heap_base
+ .global __heap_limit
+ .endif
+
+ .end
diff --git a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6_sct.S b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6_sct.S
new file mode 100644
index 0000000..c71c22d
--- /dev/null
+++ b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_ac6_sct.S
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MML_sct.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .eabi_attribute Tag_ABI_align_preserved, 1
+
+
+ .section RESET
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$Limit /* Linker symbol from scatter file */
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+ .globl Image$$ARM_LIB_STACK$$ZI$$base /* Linker symbol from scatter file */
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+ .cantunwind
+Reset_Handler:
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$base
+ msr msplim, r0
+
+ bl SystemInit
+ bl __main
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+ .cantunwind
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.c b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.c
new file mode 100644
index 0000000..36c8f7b
--- /dev/null
+++ b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.c
@@ -0,0 +1,143 @@
+/**************************************************************************//**
+ * @file startup_ARMv8MML_sct.c
+ * @brief CMSIS Core Device Startup File for
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern void __main (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#define __initial_sp Image$$ARM_LIB_STACK$$ZI$$Limit
+#define __stack_limit Image$$ARM_LIB_STACK$$ZI$$Base
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section ("RESET"))) = {
+ (pFunc)(&__initial_sp), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+
+ __set_MSPLIM((uint32_t)&__stack_limit);
+
+ SystemInit(); /* CMSIS System Initialization */
+ __main(); /* Enter PreeMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.s b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.s
new file mode 100644
index 0000000..0434ef1
--- /dev/null
+++ b/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML_sct.s
@@ -0,0 +1,132 @@
+;/**************************************************************************//**
+; * @file startup_ARMv8MML_sct.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMv8MML Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD SecureFault_Handler ; -9 Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Base|| ; Linker symbol from scatter file
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =||Image$$ARM_LIB_STACK$$ZI$$Base||
+ MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+ END
diff --git a/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld b/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
index b987fd1..f2c16dd 100644
--- a/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
@@ -5,8 +5,6 @@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -33,13 +31,10 @@
* __bss_end__
* __end__
* end
- * __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
- * __Vectors_End
- * __Vectors_Size
*/
ENTRY(Reset_Handler)
@@ -48,10 +43,6 @@
.text :
{
KEEP(*(.vectors))
- __Vectors_End = .;
- __Vectors_Size = __Vectors_End - __Vectors;
- __end__ = .;
-
*(.text*)
KEEP(*(.init))
@@ -76,6 +67,17 @@
KEEP(*(.eh_frame*))
} > FLASH
+/* SG veneers:
+ All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ must be set, either with the command line option ‘--section-start’ or in a linker script,
+ to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -122,7 +124,10 @@
} > FLASH
*/
- __etext = .;
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 4byte aligned */
+ __etext = ALIGN (4);
.data : AT (__etext)
{
@@ -170,19 +175,18 @@
.heap (COPY):
{
- __HeapBase = .;
__end__ = .;
- end = __end__;
- KEEP(*(.heap*))
+ PROVIDE(end = .);
+ *(.heap*)
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
+ /* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
- KEEP(*(.stack*))
+ *(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
diff --git a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S
index f1c6d97..1a2a553 100644
--- a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S
+++ b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file startup_ARMv8MML.s
* @brief CMSIS Core Device Startup File for
- * ARMv8MML Device Series
- * @version V5.00
- * @date 02. March 2016
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,283 +23,272 @@
* limitations under the License.
*/
- .syntax unified
- .arch armv7-m
+/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0x00000400
-#endif
- .globl __StackTop
- .globl __StackLimit
+ .syntax unified
+ .arch armv8-m.main
+
+
+/*
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Stack_Size, 0x00000400
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
__StackTop:
- .size __StackTop, . - __StackTop
+ .size __StackTop, . - __StackTop
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0x00000C00
-#endif
- .globl __HeapBase
- .globl __HeapLimit
+
+/*
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+*/
+ .equ Heap_Size, 0x00000C00
+
+ .if Heap_Size != 0 /* Heap is provided */
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .size __HeapLimit, . - __HeapLimit
+ .endif
- .section .vectors
- .align 2
- .globl __Vectors
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
__Vectors:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long SecureFault_Handler /* -9 Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVCall Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
- /* External interrupts */
- .long WDT_IRQHandler /* 0: Watchdog Timer */
- .long RTC_IRQHandler /* 1: Real Time Clock */
- .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
- .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
- .long MCIA_IRQHandler /* 4: MCIa */
- .long MCIB_IRQHandler /* 5: MCIb */
- .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
- .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
- .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
- .long UART4_IRQHandler /* 9: UART4 - not connected */
- .long AACI_IRQHandler /* 10: AACI / AC97 */
- .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
- .long ENET_IRQHandler /* 12: Ethernet */
- .long USBDC_IRQHandler /* 13: USB Device */
- .long USBHC_IRQHandler /* 14: USB Host Controller */
- .long CHLCD_IRQHandler /* 15: Character LCD */
- .long FLEXRAY_IRQHandler /* 16: Flexray */
- .long CAN_IRQHandler /* 17: CAN */
- .long LIN_IRQHandler /* 18: LIN */
- .long I2C_IRQHandler /* 19: I2C ADC/DAC */
- .long 0 /* 20: Reserved */
- .long 0 /* 21: Reserved */
- .long 0 /* 22: Reserved */
- .long 0 /* 23: Reserved */
- .long 0 /* 24: Reserved */
- .long 0 /* 25: Reserved */
- .long 0 /* 26: Reserved */
- .long 0 /* 27: Reserved */
- .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
- .long 0 /* 29: Reserved - CPU FPGA */
- .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
- .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
- .size __Vectors, . - __Vectors
+ .space (470 * 4) /* Interrupts 10 .. 480 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
- adds r4, #12
- b .L_loop0
+ adds r4, #12
+ b .L_loop0
.L_loop0_done:
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
- adds r3, #8
- b .L_loop2
+ adds r3, #8
+ b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
- movs r0, 0
+ movs r0, 0
.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- bl SystemInit
-#endif
+ ldr r0, =__StackLimit
+ msr msplim, r0
-#ifndef __START
-#define __START _start
-#endif
- bl __START
+ bl SystemInit
+ bl _start
- .pool
- .size Reset_Handler, . - Reset_Handler
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WDT_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler TIM0_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler MCIA_IRQHandler
- def_irq_handler MCIB_IRQHandler
- def_irq_handler UART0_IRQHandler
- def_irq_handler UART1_IRQHandler
- def_irq_handler UART2_IRQHandler
- def_irq_handler UART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler AACI_IRQHandler
- def_irq_handler CLCD_IRQHandler
- def_irq_handler ENET_IRQHandler
- def_irq_handler USBDC_IRQHandler
- def_irq_handler USBHC_IRQHandler
- def_irq_handler CHLCD_IRQHandler
- def_irq_handler FLEXRAY_IRQHandler
- def_irq_handler CAN_IRQHandler
- def_irq_handler LIN_IRQHandler
- def_irq_handler I2C_IRQHandler
- def_irq_handler CPU_CLCD_IRQHandler
- def_irq_handler SPI_IRQHandler
+/* Default exception/interrupt handler */
- .end
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SecureFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end
diff --git a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
index 564523c..4e303ca 100644
--- a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
+++ b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
- * @file startup_ARMv8MML.s
+ * @file startup_ARMv8MML.c
* @brief CMSIS Core Device Startup File for
- * Armv8-M Mainline Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -23,6 +23,10 @@
* limitations under the License.
*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
#include <stdint.h>
@@ -39,6 +43,7 @@
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
-#ifndef __START
-extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
-#else
-extern int __START(void) __attribute__((noreturn)); /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void); /* CMSIS System Initialization */
-#endif
+extern void _start (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void); /* CMSIS System Initialization */
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
-void Default_Handler(void); /* Default empty handler */
-void Reset_Handler(void); /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler (void) __attribute__ ((noreturn));
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
- #define __STACK_SIZE 0x00000400
-#endif
+//<h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __STACK_SIZE 0x00000400
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-#ifndef __HEAP_SIZE
- #define __HEAP_SIZE 0x00000C00
-#endif
+//<h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define __HEAP_SIZE 0x00000C00
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
@@ -86,99 +86,64 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* Armv8-M Mainline Processor Exceptions */
-void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* Armv8-M Mainline Specific Interrupts */
-void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* Armv8-M Mainline Exceptions Handler */
- (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* NMI Handler */
- HardFault_Handler, /* Hard Fault Handler */
- MemManage_Handler, /* MPU Fault Handler */
- BusFault_Handler, /* Bus Fault Handler */
- UsageFault_Handler, /* Usage Fault Handler */
- SecureFault_Handler, /* Secure Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* SVCall Handler */
- DebugMon_Handler, /* Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* PendSV Handler */
- SysTick_Handler, /* SysTick Handler */
+extern const pFunc __Vectors[496];
+ const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+ (pFunc)(&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
- /* External interrupts */
- WDT_IRQHandler, /* 0: Watchdog Timer */
- RTC_IRQHandler, /* 1: Real Time Clock */
- TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
- TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
- MCIA_IRQHandler, /* 4: MCIa */
- MCIB_IRQHandler, /* 5: MCIb */
- UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
- UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
- UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
- UART4_IRQHandler, /* 9: UART4 - not connected */
- AACI_IRQHandler, /* 10: AACI / AC97 */
- CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
- ENET_IRQHandler, /* 12: Ethernet */
- USBDC_IRQHandler, /* 13: USB Device */
- USBHC_IRQHandler, /* 14: USB Host Controller */
- CHLCD_IRQHandler, /* 15: Character LCD */
- FLEXRAY_IRQHandler, /* 16: Flexray */
- CAN_IRQHandler, /* 17: CAN */
- LIN_IRQHandler, /* 18: LIN */
- I2C_IRQHandler, /* 19: I2C ADC/DAC */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- 0, /* 26: Reserved */
- 0, /* 27: Reserved */
- CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
- 0, /* 29: Reserved - CPU FPGA */
- UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
- SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
};
@@ -189,41 +154,42 @@
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
- pSrc = (uint32_t*)*(pTable + 0);
- pDest = (uint32_t*)*(pTable + 1);
- for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
*pDest++ = *pSrc++;
- }
- }
+ }
+ }
#else
-/* Single section scheme.
+/* Single section scheme.
*
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
*
- * All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
@@ -233,40 +199,40 @@
}
#endif /*__STARTUP_COPY_MULTIPLE */
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
*
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
*
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
+/* Multiple sections scheme.
*
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
- pDest = (uint32_t*)*(pTable + 0);
- for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
*pDest++ = 0;
- }
- }
+ }
+ }
#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
+/* Single BSS section scheme.
*
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
*
- * Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
@@ -275,15 +241,10 @@
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-#ifndef __NO_SYSTEM_INIT
- SystemInit();
-#endif
+ __set_MSPLIM((uint32_t)&__StackLimit);
-#ifndef __START
-#define __START _start
-#endif
- __START();
-
+ SystemInit(); /* CMSIS System Initialization */
+ _start(); /* Enter PreeMain (C library entry point) */
}
@@ -292,5 +253,5 @@
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
- while(1);
+ while(1);
}
diff --git a/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s b/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s
index 3d3e747..21b5c2c 100644
--- a/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s
+++ b/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s
@@ -1,12 +1,12 @@
;/**************************************************************************//**
; * @file startup_ARMv8MML.s
; * @brief CMSIS Core Device Startup File for
-; * ARMv8MML Device Series
-; * @version V5.00
-; * @date 08. March 2016
+; * ARMv8MML Device
+; * @version V5.3.1
+; * @date 09. July 2018
; ******************************************************************************/
;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -39,259 +39,119 @@
; Cortex-M version
;
- MODULE ?cstartup
+ MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
- PUBLIC __vector_table_0x1c
- PUBLIC __Vectors
- PUBLIC __Vectors_End
- PUBLIC __Vectors_Size
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
- DATA
+ DATA
__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler
-
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD MemManage_Handler
- DCD BusFault_Handler
- DCD UsageFault_Handler
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
- DCD SecureFault_Handler
- DCD 0
- DCD 0
- DCD 0
- DCD SVC_Handler
- DCD DebugMon_Handler
- DCD 0
- DCD PendSV_Handler
- DCD SysTick_Handler
+ DCD SecureFault_Handler ; -9 Security Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
- ; External Interrupts
- DCD WDT_IRQHandler ; 0: Watchdog Timer
- DCD RTC_IRQHandler ; 1: Real Time Clock
- DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
- DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
- DCD MCIA_IRQHandler ; 4: MCIa
- DCD MCIB_IRQHandler ; 5: MCIb
- DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
- DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
- DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
- DCD UART4_IRQHandler ; 9: UART4 - not connected
- DCD AACI_IRQHandler ; 10: AACI / AC97
- DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
- DCD ENET_IRQHandler ; 12: Ethernet
- DCD USBDC_IRQHandler ; 13: USB Device
- DCD USBHC_IRQHandler ; 14: USB Host Controller
- DCD CHLCD_IRQHandler ; 15: Character LCD
- DCD FLEXRAY_IRQHandler ; 16: Flexray
- DCD CAN_IRQHandler ; 17: CAN
- DCD LIN_IRQHandler ; 18: LIN
- DCD I2C_IRQHandler ; 19: I2C ADC/DAC
- DCD 0 ; 20: Reserved
- DCD 0 ; 21: Reserved
- DCD 0 ; 22: Reserved
- DCD 0 ; 23: Reserved
- DCD 0 ; 24: Reserved
- DCD 0 ; 25: Reserved
- DCD 0 ; 26: Reserved
- DCD 0 ; 27: Reserved
- DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
- DCD 0 ; 29: Reserved - CPU FPGA
- DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
- DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ DS32 (470) ; Interrupts 10 .. 480 are left out
__Vectors_End
-__Vectors EQU __vector_table
-__Vectors_Size EQU __Vectors_End - __Vectors
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
+ THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SecureFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+
+ PUBWEAK Interrupt0_Handler
+ PUBWEAK Interrupt1_Handler
+ PUBWEAK Interrupt2_Handler
+ PUBWEAK Interrupt3_Handler
+ PUBWEAK Interrupt4_Handler
+ PUBWEAK Interrupt5_Handler
+ PUBWEAK Interrupt6_Handler
+ PUBWEAK Interrupt7_Handler
+ PUBWEAK Interrupt8_Handler
+ PUBWEAK Interrupt9_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SecureFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SecureFault_Handler
- B SecureFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
- B SysTick_Handler
- PUBWEAK WDT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
- B WDT_IRQHandler
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+ B .
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
- PUBWEAK TIM0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
- B TIM0_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK MCIA_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
- B MCIA_IRQHandler
-
- PUBWEAK MCIB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
- B MCIB_IRQHandler
-
- PUBWEAK UART0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
- B UART0_IRQHandler
-
- PUBWEAK UART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
- B UART1_IRQHandler
-
- PUBWEAK UART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
- B UART2_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK AACI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
- B AACI_IRQHandler
-
- PUBWEAK CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
- B CLCD_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK USBDC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
- B USBDC_IRQHandler
-
- PUBWEAK USBHC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
- B USBHC_IRQHandler
-
- PUBWEAK CHLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
- B CHLCD_IRQHandler
-
- PUBWEAK FLEXRAY_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
- B FLEXRAY_IRQHandler
-
- PUBWEAK CAN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
- B CAN_IRQHandler
-
- PUBWEAK LIN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
- B LIN_IRQHandler
-
- PUBWEAK I2C_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
- B I2C_IRQHandler
-
- PUBWEAK CPU_CLCD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
- B CPU_CLCD_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK SPI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
- B SPI_IRQHandler
-
- END
+ END
diff --git a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
index bb044c0..416207d 100644
--- a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
+++ b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
@@ -1,9 +1,9 @@
/**************************************************************************//**
* @file system_ARMv8MML.c
* @brief CMSIS Device System Source File for
- * Armv8-M Mainline Device Series
- * @version V5.00
- * @date 10. January 2018
+ * ARMv8MML Device
+ * @version V5.3.1
+ * @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -46,9 +46,9 @@
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
-#define XTAL ( 5000000UL) /* Oscillator frequency */
+#define XTAL (50000000UL) /* Oscillator frequency */
-#define SYSTEM_CLOCK (5U * XTAL)
+#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
diff --git a/Device/ARM/SVD/ARMCM0.svd b/Device/ARM/SVD/ARMCM0.svd
index e40c842..14bf841 100644
--- a/Device/ARM/SVD/ARMCM0.svd
+++ b/Device/ARM/SVD/ARMCM0.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM0</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M0</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM0</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM0P.svd b/Device/ARM/SVD/ARMCM0P.svd
index 37ab758..ff62fd4 100644
--- a/Device/ARM/SVD/ARMCM0P.svd
+++ b/Device/ARM/SVD/ARMCM0P.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
- <name>ARMCM0P</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <name>ARMCM0P</name> <!-- name of part-->
+ <series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0+ based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM0+</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM1.svd b/Device/ARM/SVD/ARMCM1.svd
index 13eb1d5..b51ac3b 100644
--- a/Device/ARM/SVD/ARMCM1.svd
+++ b/Device/ARM/SVD/ARMCM1.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM1</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M0+ based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM1</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM23.svd b/Device/ARM/SVD/ARMCM23.svd
index 83e0631..3e01f8b 100644
--- a/Device/ARM/SVD/ARMCM23.svd
+++ b/Device/ARM/SVD/ARMCM23.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM23</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M23 based device</description>
+ <description>ARM 32-bit Cortex-M23 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM23</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM3.svd b/Device/ARM/SVD/ARMCM3.svd
index 78a53ae..26e6acd 100644
--- a/Device/ARM/SVD/ARMCM3.svd
+++ b/Device/ARM/SVD/ARMCM3.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM3</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M3</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM3</name>
- <revision>r1p1</revision>
+ <revision>r2p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>4</nvicPrioBits>
+ <vtorPresent>true</vtorPresent>
+ <nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM33.svd b/Device/ARM/SVD/ARMCM33.svd
index 000c04d..ab66214 100644
--- a/Device/ARM/SVD/ARMCM33.svd
+++ b/Device/ARM/SVD/ARMCM33.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM33</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Mainline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M33 based device</description>
+ <description>ARM 32-bit Cortex-M33 based device<./description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM33</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMCM4.svd b/Device/ARM/SVD/ARMCM4.svd
index 63a9ac6..a78bc8a 100644
--- a/Device/ARM/SVD/ARMCM4.svd
+++ b/Device/ARM/SVD/ARMCM4.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM4</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M4</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M4 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM4</name>
- <revision>r1p0</revision>
+ <revision>r0p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMCM7.svd b/Device/ARM/SVD/ARMCM7.svd
index 34adfb1..7b69cb7 100644
--- a/Device/ARM/SVD/ARMCM7.svd
+++ b/Device/ARM/SVD/ARMCM7.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 -2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMCM7</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex M7</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M7 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,22 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM7</name>
- <revision>r0p0</revision>
+ <revision>r1p1</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
+ <icachePresent>true</icachePresent>
+ <dcachePresent>true</dcachePresent>
+ <itcmPresent>false</itcmPresent>
+ <dtcmPresent>false</dtcmPresent>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +77,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>
diff --git a/Device/ARM/SVD/ARMSC000.svd b/Device/ARM/SVD/ARMSC000.svd
index b3e8637..261edd1 100644
--- a/Device/ARM/SVD/ARMSC000.svd
+++ b/Device/ARM/SVD/ARMSC000.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
- <name>ARMSC000</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <name>ARMSC000</name> <!-- name of part-->
+ <series>ARM Cortex SC000</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-SC000 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>SC000</name>
- <revision>r1p0</revision>
+ <revision>r0p0</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
+ <vtorPresent>false</vtorPresent>
+ <nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMSC300.svd b/Device/ARM/SVD/ARMSC300.svd
index 3a066dc..8beb8cc 100644
--- a/Device/ARM/SVD/ARMSC300.svd
+++ b/Device/ARM/SVD/ARMSC300.svd
@@ -3,12 +3,12 @@
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
-<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMSC300</name> <!-- name of part-->
- <series>ARMCM</series> <!-- device series the device belongs to -->
- <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <series>ARM Cortex SC300</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-SC300 based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,15 +52,18 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
<name>SC300</name>
- <revision>r1p0</revision>
+ <revision>r0p0</revision>
<endian>little</endian>
- <mpuPresent>false</mpuPresent>
+ <mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -70,211 +73,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <peripheral>
- <name>SysTick</name>
- <description>24Bit System Tick Timer for use in RTOS</description>
- <baseAddress>0xE000E010</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>SysTick Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enable SysTick Timer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>TICKINT</name>
- <description>Generate Tick Interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Enable SysTick Exception</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Disable SysTick Exception</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Source to count from</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>External Clock</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>CPU Clock</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>SysTick counted to zero</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <description>SysTick Reload Value Register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>Value to auto reload SysTick after reaching zero</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <description>SysTick Current Value Register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <description>SysTick Calibration Value Register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Reload value to use for 10ms timing</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SKEW</name>
- <description>Clock Skew</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>10ms calibration value is exact</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>10ms calibration value is inexact, because of the clock frequency</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>NOREF</name>
- <description>No Ref</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>0</name>
- <description>Ref Clk available</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1</name>
- <description>Ref Clk not available</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-
- <peripheral>
- <name>WDT</name>
- <description>Watchdog Timer</description>
- <baseAddress>0x40001000</baseAddress>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x10</size>
- <usage>registers</usage>
- </addressBlock>
-
- <interrupt>
- <name>WDT</name>
- <value>1</value>
- </interrupt>
-
- <registers>
- <register>
- <name>CSR</name>
- <description>Watchdog Control and Status Register</description>
- <addressOffset>0</addressOffset>
- <size>32</size>
- <resetValue>0x4</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMv8MBL.svd b/Device/ARM/SVD/ARMv8MBL.svd
index 14b1d86..722ebe8 100644
--- a/Device/ARM/SVD/ARMv8MBL.svd
+++ b/Device/ARM/SVD/ARMv8MBL.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMv8MBL</name> <!-- name of part-->
- <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit v8-M Baseline based device</description>
+ <description>ARM 32-bit v8-M Baseline based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
- <name>CM3</name>
+ <name>ARMV8MBL</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
+ </device>
diff --git a/Device/ARM/SVD/ARMv8MML.svd b/Device/ARM/SVD/ARMv8MML.svd
index b9a639f..bb2c998 100644
--- a/Device/ARM/SVD/ARMv8MML.svd
+++ b/Device/ARM/SVD/ARMv8MML.svd
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="utf-8"?>
-<!-- File naming: <part/series name>.svd -->
+<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
- Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+ Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
- for demonstration purposes only.
-
+ for demonstration purposes only.
+
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
@@ -16,30 +16,30 @@
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
-
+
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
<vendorID>ARM</vendorID> <!-- device vendor short name -->
<name>ARMv8MML</name> <!-- name of part-->
<series>ARMV8M</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit v8-M Baseline based device</description>
+ <description>ARM 32-bit v8-M Baseline based device.</description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
@@ -52,12 +52,14 @@
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
+
<cpu> <!-- details about the cpu embedded in the device -->
- <name>CM4</name>
+ <name>ARMV8MML</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
+ <vtorPresent>true</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>4</sauNumRegions>
@@ -87,8 +89,8 @@
<access>n</access>
</region>
</sauRegionsConfig>
-
</cpu>
+
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
@@ -98,165 +100,4 @@
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
- <peripherals>
- <!-- Timer 0 -->
- <peripheral>
- <name>SAU</name>
- <version>1.0</version>
- <description>Security Attribution Unit</description>
- <groupName>SAU</groupName>
- <baseAddress>0xE000EDD0</baseAddress>
- <size>32</size>
- <access>read-write</access>
-
- <addressBlock>
- <offset>0</offset>
- <size>0x20</size>
- <usage>registers</usage>
- </addressBlock>
-
- <registers>
- <!-- CTRL: Control Register -->
- <register>
- <name>CTRL</name>
- <description>Control Register</description>
- <addressOffset>0x00</addressOffset>
- <fields>
- <!-- EN: Enable -->
- <field>
- <name>ENABLE</name>
- <description>Enable</description>
- <bitRange>[0:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable</name>
- <description>SAU is disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable</name>
- <description>SAU is enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
-
- <!-- RST: Reset -->
- <field>
- <name>ALLNS</name>
- <description>Security attribution if SAU disabled</description>
- <bitRange>[1:1]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>Secure</name>
- <description>Memory is marked as secure</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Non_Secure</name>
- <description>Memory is marked as non-secure</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- TYPE: -->
- <register>
- <name>TYPE</name>
- <description>Type Register</description>
- <addressOffset>0x04</addressOffset>
- <access>read-only</access>
- <fields>
- <!-- SREGION: -->
- <field>
- <name>SREGION</name>
- <description>Number of implemented SAU regions</description>
- <bitRange>[7:0]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RNR: -->
- <register>
- <name>RNR</name>
- <description>Region Number Register</description>
- <addressOffset>0x08</addressOffset>
- <fields>
- <!-- REGION: -->
- <field>
- <name>REGION</name>
- <description>Currently selected SAU region</description>
- <bitRange>[7:0]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>SAU_Region_0</name>
- <description>Select SAU Region 0</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_1</name>
- <description>Select SAU Region 1</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_2</name>
- <description>Select SAU Region 2</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SAU_Region_3</name>
- <description>Select SAU Region 3</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RBAR</name>
- <description>Region Base Address Register</description>
- <addressOffset>0x0C</addressOffset>
- <fields>
- <!-- BADDR: -->
- <field>
- <name>BADDR</name>
- <description>Base Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- </fields>
- </register>
-
- <!-- RBAR: -->
- <register>
- <name>RLAR</name>
- <description>Region Limit Address Register</description>
- <addressOffset>0x10</addressOffset>
- <fields>
- <!-- LADDR: -->
- <field>
- <name>LADDR</name>
- <description>Limit Address</description>
- <bitRange>[31:5]</bitRange>
- </field>
- <!-- NSC: -->
- <field>
- <name>NSC</name>
- <description>Non-Secure Callable</description>
- <bitRange>[1:1]</bitRange>
- </field>
- <!-- ENABLE: -->
- <field>
- <name>ENABLE</name>
- <description>SAU Region enabled</description>
- <bitRange>[0:0]</bitRange>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
</device>