CMSIS-Core_A:
- Added ARM Compiler 6 support
- Updated Cortex-A core functions
- Updated Startup and System files
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 6529cf4..5724381 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,12 +8,18 @@
<url>http://www.keil.com/pack/</url>
<releases>
+ <release version="5.0.2-dev3">
+ CMSIS-Core_A:
+ - Added ARM Compiler 6 support
+ - Updated Cortex-A core functions
+ - Updated Startup and System files
+ </release>
<release version="5.0.2-dev2">
CMSIS-RTOS2:
- RTX 5.1.1 (see revision history for details)
</release>
<release version="5.0.2-dev1">
- CMSIS CORE_A:
+ CMSIS-Core_A:
- Added Cortex-A core support, ARMCC specific:
- Core specific register definitions
- Generic Interrupt Controller functions
@@ -655,8 +661,12 @@
<!-- conditions are dependency rules that can apply to a component or an individual file -->
<conditions>
<!-- compiler -->
+ <condition id="ARMCC6">
+ <accept Tcompiler="ARMCC" Toptions="AC6"/>
+ <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
+ </condition>
<condition id="ARMCC">
- <require Tcompiler="ARMCC"/>
+ <require Tcompiler="ARMCC" Toptions="AC5"/>
</condition>
<condition id="GCC">
<require Tcompiler="GCC"/>
@@ -2116,12 +2126,15 @@
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA5/Include/"/>
<!-- startup / system / mmu files -->
- <file category="sourceC" name="Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.0" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct" version="1.0.0" attr="config"/>
+
</files>
</component>
@@ -2132,12 +2145,14 @@
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA7/Include/"/>
<!-- startup / system / mmu files -->
- <file category="sourceC" name="Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.0" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA7/Include/system_ARMCA7.h" version="1.0.0" attr="config"/>
- <file category="header" name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h" version="1.0.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCA7/Source/ARM/ARMCA7.sct" version="1.0.0" attr="config"/>
+ <file category="header" name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h" version="1.0.0" attr="config"/>
</files>
</component>
@@ -2148,12 +2163,14 @@
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA9/Include/"/>
<!-- startup / system / mmu files -->
- <file category="sourceC" name="Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/system_ARMCA9.c" version="1.0.0" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA9/Include/system_ARMCA9.h" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h" version="1.0.0" attr="config"/>
- <file category="linkerScript" name="Device/ARM/ARMCA9/Source/ARM/ARMCA9.sct" version="1.0.0" attr="config"/>
</files>
</component>
diff --git a/CMSIS/Core_A/Include/cmsis_armcc.h b/CMSIS/Core_A/Include/cmsis_armcc.h
index a6c0d16..3ddf232 100644
--- a/CMSIS/Core_A/Include/cmsis_armcc.h
+++ b/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -36,34 +36,49 @@
/* CMSIS compiler specific defines */
#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __STATIC_ASM
- #define __STATIC_ASM static __asm
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __declspec(noreturn)
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
- #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_ASM
+ #define __STATIC_ASM static __asm
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
- #define __PACKED __attribute__((packed))
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
#endif
@@ -209,6 +224,90 @@
*/
#define __CLZ __clz
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
/** \brief Get CPSR Register
\return CPSR Register value
*/
@@ -239,9 +338,8 @@
\param [in] mode Mode value to set
*/
__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
- MOV r1, lr
MSR CPSR_C, r0
- BX r1
+ BX lr
}
/** \brief Set Stack Pointer
@@ -253,10 +351,10 @@
BX lr
}
-/** \brief Set Process Stack Pointer
+/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
-__STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack)
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
{
ARM
PRESERVE8
@@ -270,16 +368,6 @@
BX LR
}
-/** \brief Set User Mode
- */
-__STATIC_INLINE __ASM void __set_CPS_USR(void)
-{
- ARM
-
- CPS #0x10
- BX LR
-}
-
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
@@ -304,6 +392,24 @@
#endif
}
+/** \brief Get ACTLR
+ \return Auxiliary Control register value
+ */
+__STATIC_INLINE uint32_t __get_ACTLR(void)
+{
+ register uint32_t __regACTLR __ASM("cp15:0:c1:c0:1");
+ return __regACTLR;
+}
+
+/** \brief Set ACTLR
+ \param [in] actlr Auxiliary Control value to set
+ */
+__STATIC_INLINE void __set_ACTLR(uint32_t actlr)
+{
+ register uint32_t __regACTLR __ASM("cp15:0:c1:c0:1");
+ __regACTLR = actlr;
+}
+
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
@@ -314,7 +420,7 @@
}
/** \brief Set CPACR
- \param [in] cpacr Coprocessor Acccess Control value to set
+ \param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
@@ -539,8 +645,6 @@
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
*/
-#pragma push
-#pragma arm
__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
ARM
@@ -595,14 +699,11 @@
POP {R4-R11}
BX lr
}
-#pragma pop
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
-#pragma push
-#pragma arm
__STATIC_INLINE __ASM void __FPU_Enable(void) {
ARM
@@ -668,6 +769,5 @@
BX LR
}
-#pragma pop
#endif /* __CMSIS_ARMCC_H */
diff --git a/CMSIS/Core_A/Include/cmsis_armclang.h b/CMSIS/Core_A/Include/cmsis_armclang.h
index 243f6fd..597efdf 100644
--- a/CMSIS/Core_A/Include/cmsis_armclang.h
+++ b/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -31,34 +31,68 @@
/* CMSIS compiler specific defines */
#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __STATIC_ASM
- #define __STATIC_ASM static __asm
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __declspec(noreturn)
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
- #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_ASM
+ #define __STATIC_ASM static __asm
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
- #define __PACKED __attribute__((packed))
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
#endif
@@ -210,6 +244,67 @@
*/
#define __CLZ __builtin_clz
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
/** \brief Get CPSR Register
\return CPSR Register value
*/
@@ -220,6 +315,14 @@
return(result);
}
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
/** \brief Get Mode
\return Processor Mode
*/
@@ -242,10 +345,10 @@
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
-/** \brief Set Process Stack Pointer
+/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+__STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack)
{
__ASM volatile(
".preserve8 \n"
@@ -258,13 +361,6 @@
);
}
-/** \brief Set User Mode
- */
-__STATIC_INLINE void __set_CPS_USR(void)
-{
- __ASM volatile("CPS #0x10");
-}
-
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
@@ -289,6 +385,23 @@
#endif
}
+/** \brief Get ACTLR
+ \return Auxiliary Control register value
+ */
+__STATIC_INLINE uint32_t __get_ACTLR(void)
+{
+ uint32_t result;
+ __ASM volatile("MRS %0, actlr" : "=r" (result) );
+ return(result);
+}
+
+/** \brief Set ACTLR
+ \param [in] actlr Auxiliary Control value to set
+ */
+__STATIC_INLINE void __set_ACTLR(uint32_t actlr)
+{
+ __ASM volatile ("MSR fpexc, %0" : : "r" (actlr) : "memory");
+}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
@@ -300,7 +413,7 @@
}
/** \brief Set CPACR
- \param [in] cpacr Coprocessor Acccess Control value to set
+ \param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
diff --git a/CMSIS/Core_A/Include/core_ca.h b/CMSIS/Core_A/Include/core_ca.h
index 6d1e29f..6eceeff 100644
--- a/CMSIS/Core_A/Include/core_ca.h
+++ b/CMSIS/Core_A/Include/core_ca.h
@@ -352,6 +352,47 @@
#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
+/* CP15 Register ACTLR */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */
+ uint32_t SMP:1; /*!< bit: 6 Enables coherent requests to the processor */
+ uint32_t _reserved1:3; /*!< bit: 7.. 9 Reserved */
+ uint32_t DODMBS:1; /*!< bit: 10 Disable optimized data memory barrier behavior */
+ uint32_t L2RADIS:1; /*!< bit: 11 L2 Data Cache read-allocate mode disable */
+ uint32_t L1RADIS:1; /*!< bit: 12 L1 Data Cache read-allocate mode disable */
+ uint32_t L1PCTL:2; /*!< bit:13..14 L1 Data prefetch control */
+ uint32_t DDVM:1; /*!< bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
+ uint32_t _reserved3:12; /*!< bit:16..27 Reserved */
+ uint32_t DDI:1; /*!< bit: 28 Disable dual issue */
+ uint32_t _reserved7:3; /*!< bit:29..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos 28U /*!< ACTLR: DDI Position */
+#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< ACTLR: DDI Mask */
+
+#define ACTLR_DDVM_Pos 15U /*!< ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos 13U /*!< ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< ACTLR: L1PCTL Mask */
+
+#define ACTLR_L1RADIS_Pos 12U /*!< ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< ACTLR: L1RADIS Mask */
+
+#define ACTLR_L2RADIS_Pos 11U /*!< ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos 10U /*!< ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< ACTLR: DODMBS Mask */
+
+#define ACTLR_SMP_Pos 6U /*!< ACTLR: SMP Position */
+#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< ACTLR: SMP Mask */
+
/* CP15 Register CPACR */
typedef union
{
@@ -533,22 +574,50 @@
*/
typedef struct
{
- __IO uint32_t ICDDCR;
- __I uint32_t ICDICTR;
- __I uint32_t ICDIIDR;
- uint32_t RESERVED0[29];
- __IO uint32_t ICDISR[32];
- __IO uint32_t ICDISER[32];
- __IO uint32_t ICDICER[32];
- __IO uint32_t ICDISPR[32];
- __IO uint32_t ICDICPR[32];
- __I uint32_t ICDABR[32];
- uint32_t RESERVED1[32];
- __IO uint32_t ICDIPR[256];
- __IO uint32_t ICDIPTR[256];
- __IO uint32_t ICDICFR[64];
- uint32_t RESERVED2[128];
- __IO uint32_t ICDSGIR;
+ __IOM uint32_t D_CTLR; /*!< \brief +0x000 (R/W) Distributor Control Register */
+ __IM uint32_t D_TYPER; /*!< \brief +0x004 (R/ ) Interrupt Controller Type Register */
+ __IM uint32_t D_IIDR; /*!< \brief +0x008 (R/ ) Distributor Implementer Identification Register */
+ uint32_t RESERVED1[29];
+ __IOM uint32_t D_IGROUPR[16]; /*!< \brief +0x080 - 0x0BC (R/W) Interrupt Group Registers */
+ uint32_t RESERVED2[16];
+ __IOM uint32_t D_ISENABLER[16]; /*!< \brief +0x100 - 0x13C (R/W) Interrupt Set-Enable Registers */
+ uint32_t RESERVED3[16];
+ __IOM uint32_t D_ICENABLER[16]; /*!< \brief +0x180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */
+ uint32_t RESERVED4[16];
+ __IOM uint32_t D_ISPENDR[16]; /*!< \brief +0x200 - 0x23C (R/W) Interrupt Set-Pending Registers */
+ uint32_t RESERVED5[16];
+ __IOM uint32_t D_ICPENDR[16]; /*!< \brief +0x280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */
+ uint32_t RESERVED6[16];
+ __IOM uint32_t D_ISACTIVER[16]; /*!< \brief +0x300 - 0x33C (R/W) Interrupt Set-Active Registers */
+ uint32_t RESERVED7[16];
+ __IOM uint32_t D_ICACTIVER[16]; /*!< \brief +0x380 - 0x3BC (R/W) Interrupt Clear-Active Registers */
+ uint32_t RESERVED8[16];
+ __IOM uint8_t D_IPRIORITYR[512]; /*!< \brief +0x400 - 0x5FC (R/W) Interrupt Priority Registers */
+ uint32_t RESERVED9[128];
+ __IOM uint8_t D_ITARGETSR[512]; /*!< \brief +0x800 - 0x9FC (R/W) Interrupt Targets Registers */
+ uint32_t RESERVED10[128];
+ __IOM uint32_t D_ICFGR[32]; /*!< \brief +0xC00 - 0xC7C (R/W) Interrupt Configuration Registers */
+ uint32_t RESERVED11[32];
+ __IM uint32_t D_PPISR; /*!< \brief +0xD00 (R/ ) Private Peripheral Interrupt Status Register */
+ __IM uint32_t D_SPISR[15]; /*!< \brief +0xD04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */
+ uint32_t RESERVED12[112];
+ __OM uint32_t D_SGIR; /*!< \brief +0xF00 ( /W) Software Generated Interrupt Register */
+ uint32_t RESERVED13[3];
+ __IOM uint8_t D_CPENDSGIR[16]; /*!< \brief +0xF10 - 0xF1C (R/W) SGI Clear-Pending Registers */
+ __IOM uint8_t D_SPENDSGIR[16]; /*!< \brief +0xF20 - 0xF2C (R/W) SGI Set-Pending Registers */
+ uint32_t RESERVED14[40];
+ __IM uint32_t D_PIDR4; /*!< \brief +0xFD0 (R/ ) Peripheral ID4 Register */
+ __IM uint32_t D_PIDR5; /*!< \brief +0xFD4 (R/ ) Peripheral ID5 Register */
+ __IM uint32_t D_PIDR6; /*!< \brief +0xFD8 (R/ ) Peripheral ID6 Register */
+ __IM uint32_t D_PIDR7; /*!< \brief +0xFDC (R/ ) Peripheral ID7 Register */
+ __IM uint32_t D_PIDR0; /*!< \brief +0xFE0 (R/ ) Peripheral ID0 Register */
+ __IM uint32_t D_PIDR1; /*!< \brief +0xFE4 (R/ ) Peripheral ID1 Register */
+ __IM uint32_t D_PIDR2; /*!< \brief +0xFE8 (R/ ) Peripheral ID2 Register */
+ __IM uint32_t D_PIDR3; /*!< \brief +0xFEC (R/ ) Peripheral ID3 Register */
+ __IM uint32_t D_CIDR0; /*!< \brief +0xFF0 (R/ ) Component ID0 Register */
+ __IM uint32_t D_CIDR1; /*!< \brief +0xFF4 (R/ ) Component ID1 Register */
+ __IM uint32_t D_CIDR2; /*!< \brief +0xFF8 (R/ ) Component ID2 Register */
+ __IM uint32_t D_CIDR3; /*!< \brief +0xFFC (R/ ) Component ID3 Register */
} GICDistributor_Type;
#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
@@ -557,16 +626,25 @@
*/
typedef struct
{
- __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
- __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
- __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
- __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
- __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
- __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
- __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
- __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
- uint32_t RESERVED[55];
- __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
+ __IOM uint32_t C_CTLR; /*!< \brief +0x000 (R/W) CPU Interface Control Register */
+ __IOM uint32_t C_PMR; /*!< \brief +0x004 (R/W) Interrupt Priority Mask Register */
+ __IOM uint32_t C_BPR; /*!< \brief +0x008 (R/W) Binary Point Register */
+ __IM uint32_t C_IAR; /*!< \brief +0x00C (R/ ) Interrupt Acknowledge Register */
+ __OM uint32_t C_EOIR; /*!< \brief +0x010 ( /W) End Of Interrupt Register */
+ __IM uint32_t C_RPR; /*!< \brief +0x014 (R/ ) Running Priority Register */
+ __IM uint32_t C_HPPIR; /*!< \brief +0x018 (R/ ) Highest Priority Pending Interrupt Register */
+ __IOM uint32_t C_ABPR; /*!< \brief +0x01C (R/W) Aliased Binary Point Register */
+ __IM uint32_t C_AIAR; /*!< \brief +0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+ __OM uint32_t C_AEOIR; /*!< \brief +0x024 ( /W) Aliased End Of Interrupt Register */
+ __IM uint32_t C_AHPPIR; /*!< \brief +0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+ uint32_t RESERVED15[41];
+ __IOM uint32_t C_APR0; /*!< \brief +0x0D0 (R/W) Active Priority Register */
+ uint32_t RESERVED16[3];
+ __IOM uint32_t C_NSAPR0; /*!< \brief +0x0E0 (R/W) Non-secure Active Priority Register */
+ uint32_t RESERVED17[6];
+ __IM uint32_t C_IIDR; /*!< \brief +0x0FC (R/ ) CPU Interface Identification Register */
+ uint32_t RESERVED18[960];
+ __OM uint32_t C_DIR; /*!< \brief +0x000 ( /W) Deactivate Interrupt Register */
} GICInterface_Type;
#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
@@ -828,95 +906,78 @@
__STATIC_INLINE void GIC_EnableDistributor(void)
{
- GICDistributor->ICDDCR |= 1; //enable distributor
+ GICDistributor->D_CTLR |= 1; //enable distributor
}
__STATIC_INLINE void GIC_DisableDistributor(void)
{
- GICDistributor->ICDDCR &=~1; //disable distributor
+ GICDistributor->D_CTLR &=~1; //disable distributor
}
__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
{
- return (uint32_t)(GICDistributor->ICDICTR);
+ return (uint32_t)(GICDistributor->D_TYPER);
}
__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
{
- return (uint32_t)(GICDistributor->ICDIIDR);
+ return (uint32_t)(GICDistributor->D_IIDR);
}
__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
{
- char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
- field += IRQn % 4;
- *field = (char)cpu_target & 0xf;
-}
-
-__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
-{
- uint32_t i, num_irq;
-
- //Get the maximum number of interrupts that the GIC supports
- num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
- for (i = 0; i < (num_irq/16); i++)
- {
- GICDistributor->ICDISPR[i] = *ICDICFRn++;
- }
+ GICDistributor->D_ITARGETSR[((uint32_t)(int32_t)IRQn)] = (uint8_t)(cpu_target & 0x0f);
}
__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
{
- char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
- field += IRQn % 4;
- return ((uint32_t)*field & 0xf);
+ return ((uint32_t) GICDistributor->D_ITARGETSR[((uint32_t)(int32_t)IRQn)] & 0x0f);
}
__STATIC_INLINE void GIC_EnableInterface(void)
{
- GICInterface->ICCICR |= 1; //enable interface
+ GICInterface->C_CTLR |= 1; //enable interface
}
__STATIC_INLINE void GIC_DisableInterface(void)
{
- GICInterface->ICCICR &=~1; //disable distributor
+ GICInterface->C_CTLR &=~1; //disable distributor
}
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
{
- return (IRQn_Type)(GICInterface->ICCIAR);
+ return (IRQn_Type)(GICInterface->C_IAR);
}
__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
{
- GICInterface->ICCEOIR = IRQn;
+ GICInterface->C_EOIR = IRQn;
}
__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
{
- GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+ GICDistributor->D_ISENABLER[IRQn / 32] = 1 << (IRQn % 32);
}
__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
{
- GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+ GICDistributor->D_ICENABLER[IRQn / 32] = 1 << (IRQn % 32);
}
__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
{
- GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+ GICDistributor->D_ISPENDR[IRQn / 32] = 1 << (IRQn % 32);
}
__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+ GICDistributor->D_ICPENDR[IRQn / 32] = 1 << (IRQn % 32);
}
__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
{
// Word-size read/writes must be used to access this register
- volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
+ volatile uint32_t * field = &(GICDistributor->D_ICFGR[IRQn / 16]);
unsigned bit_shift = (IRQn % 16)<<1;
unsigned int save_word;
@@ -928,55 +989,67 @@
__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
- field += IRQn % 4;
- *field = (char)priority;
+ GICDistributor->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] = (uint8_t)(priority);
}
__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
{
- char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
- field += IRQn % 4;
- return (uint32_t)*field;
+ return((uint32_t)GICDistributor->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)]);
}
-__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
{
- GICInterface->ICCPMR = priority & 0xff; //set priority mask
+ GICInterface->C_PMR = priority & 0xff; //set priority mask
+}
+
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+ return (uint32_t)GICInterface->C_PMR;
}
__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
{
- GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+ GICInterface->C_BPR = binary_point & 0x07; //set binary point
}
-__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
{
- return (uint32_t)GICInterface->ICCBPR;
+ return (uint32_t)GICInterface->C_BPR;
}
__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
{
uint32_t pending, active;
- active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
- pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+ active = ((GICDistributor->D_ISACTIVER[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+ pending =((GICDistributor->D_ISPENDR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
return ((active<<1) | pending);
}
__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
{
- GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+ GICDistributor->D_SGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
}
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
+{
+ return GICInterface->C_HPPIR;
+}
+
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{
+ return GICInterface->C_IIDR;
+}
+
+
__STATIC_INLINE void GIC_DistInit(void)
{
IRQn_Type i;
uint32_t num_irq = 0;
uint32_t priority_field;
- //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //A reset sets all bits in the D_IGROUPRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
@@ -985,7 +1058,7 @@
num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
/* Priority level is implementation defined.
- To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ To determine the number of priority bits implemented write 0xFF to an D_IPRIORITYR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
@@ -1010,14 +1083,14 @@
IRQn_Type i;
uint32_t priority_field;
- //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //A reset sets all bits in the D_IGROUPRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
GIC_DisableInterface();
/* Priority level is implementation defined.
- To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ To determine the number of priority bits implemented write 0xFF to an D_IPRIORITYR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
@@ -1038,7 +1111,7 @@
//Set binary point to 0
GIC_SetBinaryPoint(0);
//Set priority mask
- GIC_InterfacePriorityMask(0xff);
+ GIC_SetInterfacePriorityMask(0xff);
}
__STATIC_INLINE void GIC_Enable(void)
diff --git a/CMSIS/DoxyGen/Core_A/src/Overview.txt b/CMSIS/DoxyGen/Core_A/src/Overview.txt
index 6b0dabc..bd46fbb 100644
--- a/CMSIS/DoxyGen/Core_A/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Overview.txt
@@ -50,6 +50,7 @@
The \ref templates_pg supplied by ARM have been tested and verified with the following toolchains:
- ARM: ARM Compiler V5.6
+ - ARM: ARM Compiler V6.6
<hr>
*/
diff --git a/CMSIS/DoxyGen/Core_A/src/Using.txt b/CMSIS/DoxyGen/Core_A/src/Using.txt
index 32a1d6a..ba281ff 100644
--- a/CMSIS/DoxyGen/Core_A/src/Using.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Using.txt
@@ -19,14 +19,14 @@
The default initialization sequence is
- set the vector base address register (\ref __set_VBAR),
- set stacks for each exception mode (\ref __set_mode, \ref __set_SP),
- - call \ref MMU_CreateTranslationTable, and
- call \ref SystemInit.
After the system initialization control is transferred to the C/C++ run-time
library which performs initialization and calls the \b main function in the user code. In addition the \ref startup_c_pg contains a weak default handler
implementation for every exception. It may also contain stack and heap configurations for the user application.
-The \ref system_c_pg performs the setup for the processor clock. The variable \ref SystemCoreClock indicates the CPU clock speed.
+The \ref system_c_pg performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface
+and floating point unit. The variable \ref SystemCoreClock indicates the CPU clock speed.
\ref system_init_gr describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration.
The \ref device_h_pg is the central include file that the application programmer is using in the C/C++ source code. It provides the following features:
diff --git a/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt b/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
index 07bf54b..9f44463 100644
--- a/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
+++ b/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
@@ -138,24 +138,6 @@
*/
/**
-\def __UNALIGNED_UINT32(x)
-\brief Pointer for unaligned access of a uint32_t variable.
-\details
-Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
-processor core and compiler settings.
-
-<b> Code Example:</b>
-\code
-uint32_t val32;
-
-void test (uint8_t *ptr) {
- __UNALIGNED_UINT32(ptr) = val32;
-}
-\endcode
-*/
-
-/**
\def __ALIGNED(x)
\brief Minimum alignment for a variable.
\details
@@ -211,14 +193,10 @@
\details
This function assigns the given value to the current stack pointer.
-\fn __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
+\fn __STATIC_ASM void __set_SP_usr(uint32_t topOfProcStack)
\details
This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-\fn __STATIC_ASM void __set_CPS_USR(void)
-\details
- This function changes the processor state to User Mode
-
\fn __STATIC_INLINE uint32_t __get_FPEXC(void)
\details
This function returns the current value of the Floating Point Exception Control register.
diff --git a/CMSIS/DoxyGen/Core_A/src/core_ca.txt b/CMSIS/DoxyGen/Core_A/src/core_ca.txt
index d78dfd0..e07e2cd 100644
--- a/CMSIS/DoxyGen/Core_A/src/core_ca.txt
+++ b/CMSIS/DoxyGen/Core_A/src/core_ca.txt
@@ -450,7 +450,6 @@
\fn __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
\fn __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
\fn __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
-\fn __STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
\fn __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
\fn __STATIC_INLINE void GIC_EnableInterface(void)
\fn __STATIC_INLINE void GIC_DisableInterface(void)
@@ -463,11 +462,14 @@
\fn __STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
\fn __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\fn __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
-\fn __STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
+\fn __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+\fn __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
\fn __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
-\fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+\fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
\fn __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
\fn __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+\fn __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
+\fn __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
\fn __STATIC_INLINE void GIC_DistInit(void)
\fn __STATIC_INLINE void GIC_CPUInterfaceInit(void)
\fn __STATIC_INLINE void GIC_Enable(void)
diff --git a/Device/ARM/ARMCA5/Include/system_ARMCA5.h b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
index 691e6be..7c1dffa 100644
--- a/Device/ARM/ARMCA5/Include/system_ARMCA5.h
+++ b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
@@ -32,13 +32,47 @@
extern "C" {
#endif
-typedef void(*IRQHandler)();
-uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
-uint32_t InterruptHandlerUnregister(IRQn_Type);
-void SystemCoreClockUpdate (void);
-extern uint32_t SystemCoreClock;
-void SystemInit (void);
-void MMU_CreateTranslationTable(void);
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Interrupt Handler Register.
+
+ Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+ \brief Interrupt Handler Unregister.
+
+ Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
diff --git a/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct b/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct
new file mode 100644
index 0000000..7eba725
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
new file mode 100644
index 0000000..5fd4168
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
+void Reset_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exceptional mode
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __main
+ IMPORT __main
+ BL __main
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct b/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct
new file mode 100644
index 0000000..41e562c
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
new file mode 100644
index 0000000..54da7d1
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =FreeRTOS_SWI_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =FreeRTOS_IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct b/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct
deleted file mode 100644
index a807d93..0000000
--- a/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct
+++ /dev/null
@@ -1,77 +0,0 @@
-#! armcc -E
-;**************************************************
-; Copyright (c) 2017 ARM Ltd. All rights reserved.
-;**************************************************
-
-; Scatter-file for RTX Example on Versatile Express
-
-; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
-
-; This platform has 2GB SDRAM starting at 0x80000000.
-
-#include "mem_ARMCA5.h"
-
-SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
-{
- VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
- {
- * (RESET, +FIRST) ; Vector table and other startup code
- * (InRoot$$Sections) ; All (library) code that must be in a root region
- * (+RO-CODE) ; Application RO code (.text)
- * (+RO-DATA) ; Application RO data (.constdata)
- }
-
- RW_DATA __RAM_BASE __RW_DATA_SIZE
- { * (+RW) } ; Application RW data (.data)
-
- ZI_DATA (__RAM_BASE+
- __RW_DATA_SIZE) __ZI_DATA_SIZE
- { * (+ZI) } ; Application ZI data (.bss)
-
- ARM_LIB_HEAP (__RAM_BASE
- +__RW_DATA_SIZE
- +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
- { }
-
- UND_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE
- -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
- { }
-
- ABT_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
- { }
-
- SVC_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
- { }
-
- IRQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
- { }
-
- FIQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
- { }
-
- ARM_LIB_STACK (__RAM_BASE
- +__RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
- { }
-
- TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
- { }
-}
diff --git a/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c
deleted file mode 100644
index 3e3175c..0000000
--- a/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
- * @file startup_ARMCA5.c
- * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
- * @version V1.00
- * @date 16 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <ARMCA5.h>
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t Image$$FIQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$IRQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$SVC_STACK$$ZI$$Limit;
-extern uint32_t Image$$ABT_STACK$$ZI$$Limit;
-extern uint32_t Image$$UND_STACK$$ZI$$Limit;
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-void Vectors(void) __attribute__ ((section("RESET")));
-__ASM void Vectors(void) {
- IMPORT Reset_Handler
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-uint32_t reg;
-
- // Put any cores other than 0 to sleep
- if ((__get_MPIDR()&3U)!=0) __WFI();
-
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 0); // Clear M bit 0 to disable MMU
- reg &= ~(0x1 << 11); // Clear Z bit 11 to disable branch prediction
- reg &= ~(0x1 << 13); // Clear V bit 13 to disable hivecs
- __set_SCTLR(reg); // Write value back to CP15 System Control register
- __ISB();
-
- reg = __get_ACTRL(); // Read CP15 Auxiliary Control Register
- reg |= (0x1 << 1); // Enable L2 prefetch hint (UNK/WI since r4p1)
- __set_ACTRL(reg); // Write CP15 Auxiliary Control Register
-
- __set_VBAR((uint32_t)((uint32_t*)&Vectors));
-
- // Setup Stack for each exceptional mode
- __set_mode(FIQ_MODE);
- __set_SP((uint32_t)&Image$$FIQ_STACK$$ZI$$Limit);
- __set_mode(IRQ_MODE);
- __set_SP((uint32_t)&Image$$IRQ_STACK$$ZI$$Limit);
- __set_mode(SVC_MODE);
- __set_SP((uint32_t)&Image$$SVC_STACK$$ZI$$Limit);
- __set_mode(ABT_MODE);
- __set_SP((uint32_t)&Image$$ABT_STACK$$ZI$$Limit);
- __set_mode(UND_MODE);
- __set_SP((uint32_t)&Image$$UND_STACK$$ZI$$Limit);
- __set_mode(SYS_MODE);
- __set_SP((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
-
- // Create Translation Table
- MMU_CreateTranslationTable();
-
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
-
- // Invalidate data cache
- __L1C_CleanInvalidateCache(0);
-
- // Enable MMU, but leave caches disabled (they will be enabled later)
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
- reg &= ~(0x1 << 28); // Clear TRE bit 28 to disable TEX remap
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 1); // Clear A bit 1 to disable strict alignment fault checking
- reg |= (0x1 << 0); // Set M bit 0 to enable MMU
- __set_SCTLR(reg); // Write CP15 System Control register
-
- SystemInit();
-
- extern void __main(void);
- __main();
-}
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
diff --git a/Device/ARM/ARMCA5/Source/system_ARMCA5.c b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
index cab0a98..94e08f5 100644
--- a/Device/ARM/ARMCA5/Source/system_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
@@ -78,8 +78,45 @@
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
- GIC_Enable();
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if (__GIC_PRESENT == 1)
+ // Enable GIC
+ GIC_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
__FPU_Enable();
+#endif
}
diff --git a/Device/ARM/ARMCA7/Include/system_ARMCA7.h b/Device/ARM/ARMCA7/Include/system_ARMCA7.h
index fe57009..1dc618a 100644
--- a/Device/ARM/ARMCA7/Include/system_ARMCA7.h
+++ b/Device/ARM/ARMCA7/Include/system_ARMCA7.h
@@ -32,13 +32,47 @@
extern "C" {
#endif
-typedef void(*IRQHandler)();
-uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
-uint32_t InterruptHandlerUnregister(IRQn_Type);
-void SystemCoreClockUpdate (void);
-extern uint32_t SystemCoreClock;
-void SystemInit (void);
-void MMU_CreateTranslationTable(void);
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Interrupt Handler Register.
+
+ Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+ \brief Interrupt Handler Unregister.
+
+ Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
diff --git a/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct b/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct
new file mode 100644
index 0000000..b5677de
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA7.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
new file mode 100644
index 0000000..7b1554e
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file startup_ARMCA7.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
+void Reset_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exceptional mode
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __main
+ IMPORT __main
+ BL __main
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct b/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct
new file mode 100644
index 0000000..d8f3716
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA7.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
new file mode 100644
index 0000000..9f2241c
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file startup_ARMCA7.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =FreeRTOS_SWI_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =FreeRTOS_IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA7/Source/ARM/ARMCA7.sct b/Device/ARM/ARMCA7/Source/ARM/ARMCA7.sct
deleted file mode 100644
index c5612de..0000000
--- a/Device/ARM/ARMCA7/Source/ARM/ARMCA7.sct
+++ /dev/null
@@ -1,77 +0,0 @@
-#! armcc -E
-;**************************************************
-; Copyright (c) 2017 ARM Ltd. All rights reserved.
-;**************************************************
-
-; Scatter-file for RTX Example on Versatile Express
-
-; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
-
-; This platform has 2GB SDRAM starting at 0x80000000.
-
-#include "mem_ARMCA7.h"
-
-SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
-{
- VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
- {
- * (RESET, +FIRST) ; Vector table and other startup code
- * (InRoot$$Sections) ; All (library) code that must be in a root region
- * (+RO-CODE) ; Application RO code (.text)
- * (+RO-DATA) ; Application RO data (.constdata)
- }
-
- RW_DATA __RAM_BASE __RW_DATA_SIZE
- { * (+RW) } ; Application RW data (.data)
-
- ZI_DATA (__RAM_BASE+
- __RW_DATA_SIZE) __ZI_DATA_SIZE
- { * (+ZI) } ; Application ZI data (.bss)
-
- ARM_LIB_HEAP (__RAM_BASE
- +__RW_DATA_SIZE
- +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
- { }
-
- UND_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE
- -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
- { }
-
- ABT_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
- { }
-
- SVC_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
- { }
-
- IRQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
- { }
-
- FIQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
- { }
-
- ARM_LIB_STACK (__RAM_BASE
- +__RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
- { }
-
- TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
- { }
-}
diff --git a/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c
deleted file mode 100644
index 112632d..0000000
--- a/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
- * @file startup_ARMCA7.c
- * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
- * @version V1.00
- * @date 22 Feb 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <ARMCA7.h>
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t Image$$FIQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$IRQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$SVC_STACK$$ZI$$Limit;
-extern uint32_t Image$$ABT_STACK$$ZI$$Limit;
-extern uint32_t Image$$UND_STACK$$ZI$$Limit;
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-void Vectors(void) __attribute__ ((section("RESET")));
-__ASM void Vectors(void) {
- IMPORT Reset_Handler
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-uint32_t reg;
-
- // Put any cores other than 0 to sleep
- if ((__get_MPIDR()&3U)!=0) __WFI();
-
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 0); // Clear M bit 0 to disable MMU
- reg &= ~(0x1 << 11); // Clear Z bit 11 to disable branch prediction
- reg &= ~(0x1 << 13); // Clear V bit 13 to disable hivecs
- __set_SCTLR(reg); // Write value back to CP15 System Control register
- __ISB();
-
- reg = __get_ACTRL(); // Read CP15 Auxiliary Control Register
- reg |= (0x1 << 1); // Enable L2 prefetch hint (UNK/WI since r4p1)
- __set_ACTRL(reg); // Write CP15 Auxiliary Control Register
-
- __set_VBAR((uint32_t)((uint32_t*)&Vectors));
-
- // Setup Stack for each exceptional mode
- __set_mode(FIQ_MODE);
- __set_SP((uint32_t)&Image$$FIQ_STACK$$ZI$$Limit);
- __set_mode(IRQ_MODE);
- __set_SP((uint32_t)&Image$$IRQ_STACK$$ZI$$Limit);
- __set_mode(SVC_MODE);
- __set_SP((uint32_t)&Image$$SVC_STACK$$ZI$$Limit);
- __set_mode(ABT_MODE);
- __set_SP((uint32_t)&Image$$ABT_STACK$$ZI$$Limit);
- __set_mode(UND_MODE);
- __set_SP((uint32_t)&Image$$UND_STACK$$ZI$$Limit);
- __set_mode(SYS_MODE);
- __set_SP((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
-
- // Create Translation Table
- MMU_CreateTranslationTable();
-
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
-
- // Invalidate data cache
- __L1C_CleanInvalidateCache(0);
-
- // Enable MMU, but leave caches disabled (they will be enabled later)
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
- reg &= ~(0x1 << 28); // Clear TRE bit 28 to disable TEX remap
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 1); // Clear A bit 1 to disable strict alignment fault checking
- reg |= (0x1 << 0); // Set M bit 0 to enable MMU
- __set_SCTLR(reg); // Write CP15 System Control register
-
- SystemInit();
-
- extern void __main(void);
- __main();
-}
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
diff --git a/Device/ARM/ARMCA7/Source/system_ARMCA7.c b/Device/ARM/ARMCA7/Source/system_ARMCA7.c
index 4b7050d..8b230a3 100644
--- a/Device/ARM/ARMCA7/Source/system_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/system_ARMCA7.c
@@ -78,8 +78,45 @@
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
- GIC_Enable();
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if (__GIC_PRESENT == 1)
+ // Enable GIC
+ GIC_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
__FPU_Enable();
+#endif
}
diff --git a/Device/ARM/ARMCA9/Include/system_ARMCA9.h b/Device/ARM/ARMCA9/Include/system_ARMCA9.h
index d1652fd..4ebd072 100644
--- a/Device/ARM/ARMCA9/Include/system_ARMCA9.h
+++ b/Device/ARM/ARMCA9/Include/system_ARMCA9.h
@@ -32,13 +32,47 @@
extern "C" {
#endif
-typedef void(*IRQHandler)();
-uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
-uint32_t InterruptHandlerUnregister(IRQn_Type);
-void SystemCoreClockUpdate (void);
-extern uint32_t SystemCoreClock;
-void SystemInit (void);
-void MMU_CreateTranslationTable(void);
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Interrupt Handler Register.
+
+ Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+ \brief Interrupt Handler Unregister.
+
+ Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
diff --git a/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct b/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct
new file mode 100644
index 0000000..4bf3816
--- /dev/null
+++ b/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA9.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
new file mode 100644
index 0000000..df1a8c1
--- /dev/null
+++ b/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file startup_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA9.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exceptional mode
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __main
+ IMPORT __main
+ BL __main
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct b/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct
new file mode 100644
index 0000000..3316f93
--- /dev/null
+++ b/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA9.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
new file mode 100644
index 0000000..3687c56
--- /dev/null
+++ b/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file startup_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA9.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =FreeRTOS_SWI_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =FreeRTOS_IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA9/Source/ARM/ARMCA9.sct b/Device/ARM/ARMCA9/Source/ARM/ARMCA9.sct
deleted file mode 100644
index a4402b0..0000000
--- a/Device/ARM/ARMCA9/Source/ARM/ARMCA9.sct
+++ /dev/null
@@ -1,77 +0,0 @@
-#! armcc -E
-;**************************************************
-; Copyright (c) 2017 ARM Ltd. All rights reserved.
-;**************************************************
-
-; Scatter-file for RTX Example on Versatile Express
-
-; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
-
-; This platform has 2GB SDRAM starting at 0x80000000.
-
-#include "mem_ARMCA9.h"
-
-SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
-{
- VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
- {
- * (RESET, +FIRST) ; Vector table and other startup code
- * (InRoot$$Sections) ; All (library) code that must be in a root region
- * (+RO-CODE) ; Application RO code (.text)
- * (+RO-DATA) ; Application RO data (.constdata)
- }
-
- RW_DATA __RAM_BASE __RW_DATA_SIZE
- { * (+RW) } ; Application RW data (.data)
-
- ZI_DATA (__RAM_BASE+
- __RW_DATA_SIZE) __ZI_DATA_SIZE
- { * (+ZI) } ; Application ZI data (.bss)
-
- ARM_LIB_HEAP (__RAM_BASE
- +__RW_DATA_SIZE
- +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
- { }
-
- UND_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE
- -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
- { }
-
- ABT_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE
- -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
- { }
-
- SVC_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE
- -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
- { }
-
- IRQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE
- -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
- { }
-
- FIQ_STACK (__RAM_BASE
- +__RAM_SIZE
- -__STACK_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
- { }
-
- ARM_LIB_STACK (__RAM_BASE
- +__RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
- { }
-
- TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
- { }
-}
diff --git a/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c
deleted file mode 100644
index a8af5c0..0000000
--- a/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
- * @file startup_ARMCA9.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
- * @version V1.00
- * @date 22 Feb 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <ARMCA9.h>
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t Image$$FIQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$IRQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$SVC_STACK$$ZI$$Limit;
-extern uint32_t Image$$ABT_STACK$$ZI$$Limit;
-extern uint32_t Image$$UND_STACK$$ZI$$Limit;
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-void Vectors(void) __attribute__ ((section("RESET")));
-__ASM void Vectors(void) {
- IMPORT Reset_Handler
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-uint32_t reg;
-
- // Put any cores other than 0 to sleep
- if ((__get_MPIDR()&3U)!=0) __WFI();
-
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 0); // Clear M bit 0 to disable MMU
- reg &= ~(0x1 << 11); // Clear Z bit 11 to disable branch prediction
- reg &= ~(0x1 << 13); // Clear V bit 13 to disable hivecs
- __set_SCTLR(reg); // Write value back to CP15 System Control register
- __ISB();
-
- reg = __get_ACTRL(); // Read CP15 Auxiliary Control Register
- reg |= (0x1 << 1); // Enable L2 prefetch hint (UNK/WI since r4p1)
- __set_ACTRL(reg); // Write CP15 Auxiliary Control Register
-
- __set_VBAR((uint32_t)((uint32_t*)&Vectors));
-
- // Setup Stack for each exceptional mode
- __set_mode(FIQ_MODE);
- __set_SP((uint32_t)&Image$$FIQ_STACK$$ZI$$Limit);
- __set_mode(IRQ_MODE);
- __set_SP((uint32_t)&Image$$IRQ_STACK$$ZI$$Limit);
- __set_mode(SVC_MODE);
- __set_SP((uint32_t)&Image$$SVC_STACK$$ZI$$Limit);
- __set_mode(ABT_MODE);
- __set_SP((uint32_t)&Image$$ABT_STACK$$ZI$$Limit);
- __set_mode(UND_MODE);
- __set_SP((uint32_t)&Image$$UND_STACK$$ZI$$Limit);
- __set_mode(SYS_MODE);
- __set_SP((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
-
- // Create Translation Table
- MMU_CreateTranslationTable();
-
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
-
- // Invalidate data cache
- __L1C_CleanInvalidateCache(0);
-
- // Enable MMU, but leave caches disabled (they will be enabled later)
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
- reg &= ~(0x1 << 28); // Clear TRE bit 28 to disable TEX remap
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 1); // Clear A bit 1 to disable strict alignment fault checking
- reg |= (0x1 << 0); // Set M bit 0 to enable MMU
- __set_SCTLR(reg); // Write CP15 System Control register
-
- SystemInit();
-
- extern void __main(void);
- __main();
-}
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
diff --git a/Device/ARM/ARMCA9/Source/system_ARMCA9.c b/Device/ARM/ARMCA9/Source/system_ARMCA9.c
index 30e9f3b..e2f435e 100644
--- a/Device/ARM/ARMCA9/Source/system_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/system_ARMCA9.c
@@ -78,8 +78,45 @@
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
- GIC_Enable();
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if (__GIC_PRESENT == 1)
+ // Enable GIC
+ GIC_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
__FPU_Enable();
+#endif
}
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c b/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
index 6ddfc8f..dd3e25f 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
@@ -36,18 +36,9 @@
#define SYS_MODE 0x1F // System mode
/*----------------------------------------------------------------------------
- Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t Image$$FIQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$IRQ_STACK$$ZI$$Limit;
-extern uint32_t Image$$SVC_STACK$$ZI$$Limit;
-extern uint32_t Image$$ABT_STACK$$ZI$$Limit;
-extern uint32_t Image$$UND_STACK$$ZI$$Limit;
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-
-/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
void Reset_Handler(void);
/*----------------------------------------------------------------------------
@@ -63,9 +54,7 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
-void Vectors(void) __attribute__ ((section("RESET")));
__ASM void Vectors(void) {
- IMPORT Reset_Handler
IMPORT Undef_Handler
IMPORT SVC_Handler
IMPORT PAbt_Handler
@@ -85,72 +74,67 @@
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-uint32_t reg;
+__ASM void Reset_Handler(void) {
+
+ // Mask interrupts
+ CPSID if
// Put any cores other than 0 to sleep
- if ((__get_MPIDR()&3U)!=0) __WFI();
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 0); // Clear M bit 0 to disable MMU
- reg &= ~(0x1 << 11); // Clear Z bit 11 to disable branch prediction
- reg &= ~(0x1 << 13); // Clear V bit 13 to disable hivecs
- __set_SCTLR(reg); // Write value back to CP15 System Control register
- __ISB();
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
- reg = __get_ACTRL(); // Read CP15 Auxiliary Control Register
- reg |= (0x1 << 1); // Enable L2 prefetch hint (UNK/WI since r4p1)
- __set_ACTRL(reg); // Write CP15 Auxiliary Control Register
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
- __set_VBAR((uint32_t)((uint32_t*)&Vectors));
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exceptional mode
- __set_mode(FIQ_MODE);
- __set_SP((uint32_t)&Image$$FIQ_STACK$$ZI$$Limit);
- __set_mode(IRQ_MODE);
- __set_SP((uint32_t)&Image$$IRQ_STACK$$ZI$$Limit);
- __set_mode(SVC_MODE);
- __set_SP((uint32_t)&Image$$SVC_STACK$$ZI$$Limit);
- __set_mode(ABT_MODE);
- __set_SP((uint32_t)&Image$$ABT_STACK$$ZI$$Limit);
- __set_mode(UND_MODE);
- __set_SP((uint32_t)&Image$$UND_STACK$$ZI$$Limit);
- __set_mode(SYS_MODE);
- __set_SP((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
- // Create Translation Table
- MMU_CreateTranslationTable();
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
+ // Unmask interrupts
+ CPSIE if
- // Invalidate data cache
- __L1C_CleanInvalidateCache(0);
-
- // Enable MMU, but leave caches disabled (they will be enabled later)
- reg = __get_SCTLR(); // Read CP15 System Control register
- reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
- reg &= ~(0x1 << 28); // Clear TRE bit 28 to disable TEX remap
- reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
- reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
- reg &= ~(0x1 << 1); // Clear A bit 1 to disable strict alignment fault checking
- reg |= (0x1 << 0); // Set M bit 0 to enable MMU
- __set_SCTLR(reg); // Write CP15 System Control register
-
- SystemInit();
-
- extern void __main(void);
- __main();
+ // Call __main
+ IMPORT __main
+ BL __main
}
/*----------------------------------------------------------------------------
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c b/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
index b12465f..1a9bd99 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
@@ -98,14 +98,44 @@
reaching pre-main. RW section may be overwritten afterwards. */
SystemCoreClock = SYSTEM_CLOCK;
- /* Enable generic interrupt controller */
- GIC_Enable();
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
- /* Enable caches */
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
- L2C_Enable();
- /* Enable FPU */
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if (__GIC_PRESENT == 1)
+ // Enable GIC
+ GIC_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
__FPU_Enable();
+#endif
}