DSP: Removing deprecated library variant.
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 048ae8b..ef18053 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -16,7 +16,7 @@
<release version="5.7.1-dev1">
Active development ...
CMSIS-Core(M):
- - Added ARMv8-M Stack Sealing (to linker, startup) for toolcahin ARM, GCC
+ - Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC
- Changed C-Startup to default Startup.
</release>
<release version="5.7.1-dev0">
@@ -1137,14 +1137,6 @@
<accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
<accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
</condition>
- <condition id="CM7_SP">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
- <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
- </condition>
- <condition id="CM7_DP">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
- <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
- </condition>
<condition id="CM23">
<description>Cortex-M23 processor based device</description>
<require Dcore="Cortex-M23"/>
@@ -1179,40 +1171,6 @@
<accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
</condition>
- <condition id="CM33_NODSP_NOFPU">
- <description>CM33, no DSP, no FPU</description>
- <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM33_DSP_NOFPU">
- <description>CM33, DSP, no FPU</description>
- <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM33_NODSP_SP">
- <description>CM33, no DSP, SP FPU</description>
- <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
- </condition>
- <condition id="CM33_DSP_SP">
- <description>CM33, DSP, SP FPU</description>
- <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
- </condition>
-
- <condition id="CM35P_NODSP_NOFPU">
- <description>CM35P, no DSP, no FPU</description>
- <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU">
- <description>CM35P, DSP, no FPU</description>
- <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="CM35P_NODSP_SP">
- <description>CM35P, no DSP, SP FPU</description>
- <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
- </condition>
- <condition id="CM35P_DSP_SP">
- <description>CM35P, DSP, SP FPU</description>
- <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
- </condition>
-
<condition id="CM55_NOFPU_NOMVE">
<description>Cortex-M55, no FPU, no MVE</description>
<require Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="NO_MVE"/>
@@ -1228,23 +1186,6 @@
<accept Dcore="Cortex-M55" Dfpu="DP_FPU"/>
</condition>
- <condition id="ARMv8MML_NODSP_NOFPU">
- <description>Armv8-M Mainline, no DSP, no FPU</description>
- <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU">
- <description>Armv8-M Mainline, DSP, no FPU</description>
- <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP">
- <description>Armv8-M Mainline, no DSP, SP FPU</description>
- <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP">
- <description>Armv8-M Mainline, DSP, SP FPU</description>
- <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
- </condition>
-
<condition id="CA5_CA9">
<description>Cortex-A5 or Cortex-A9 processor based device</description>
<accept Dcore="Cortex-A5"/>
@@ -1380,38 +1321,6 @@
<require Dendian="Big-endian"/>
</condition>
- <condition id="CM7_SP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
- <require condition="CM7_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM7_SP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
- <require condition="CM7_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_SP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
- <require condition="CM7_SP_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_DP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
- <require condition="CM7_DP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM7_DP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
- <require condition="CM7_DP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_DP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
- <require condition="CM7_DP_ARMCC"/>
- <require Dendian="Big-endian"/>
- </condition>
-
<condition id="CM23_ARMCC">
<description>Cortex-M23 processor based device for the Arm Compiler</description>
<require condition="CM23"/>
@@ -1445,47 +1354,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM33_NODSP_NOFPU_ARMCC">
- <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
- <require condition="CM33_NODSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_ARMCC">
- <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
- <require condition="CM33_DSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_NODSP_SP_ARMCC">
- <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
- <require condition="CM33_NODSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_DSP_SP_ARMCC">
- <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
- <require condition="CM33_DSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
- <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
- <require condition="CM33_NODSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_LE_ARMCC">
- <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
- <require condition="CM33_DSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_NODSP_SP_LE_ARMCC">
- <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
- <require condition="CM33_NODSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_SP_LE_ARMCC">
- <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
- <require condition="CM33_DSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM35P_ARMCC">
<description>Cortex-M35P processor based device for the Arm Compiler</description>
<require condition="CM35P"/>
@@ -1508,47 +1376,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM35P_NODSP_NOFPU_ARMCC">
- <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
- <require condition="CM35P_NODSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_ARMCC">
- <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
- <require condition="CM35P_DSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_NODSP_SP_ARMCC">
- <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
- <require condition="CM35P_NODSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_DSP_SP_ARMCC">
- <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
- <require condition="CM35P_DSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
- <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
- <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
- <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
- <require condition="CM35P_DSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_NODSP_SP_LE_ARMCC">
- <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
- <require condition="CM35P_NODSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_SP_LE_ARMCC">
- <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
- <require condition="CM35P_DSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM55_NOFPU_NOMVE_ARMCC">
<description>Cortex-M55 processor, no FPU, no MVE, Arm Compiler</description>
<require condition="CM55_NOFPU_NOMVE"/>
@@ -1608,47 +1435,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
- <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
- <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_ARMCC">
- <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
- <require condition="ARMv8MML_NODSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_ARMCC">
- <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
- <require condition="ARMv8MML_DSP_SP"/>
- <require Tcompiler="ARMCC"/>
- </condition>
- <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
- <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
- <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
- <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
- <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
- <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
- <require condition="ARMv8MML_DSP_SP_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="TZ Secure ARMCC6">
<description>TrustZone (Secure), Arm Compiler</description>
<require condition="TZ Secure"/>
@@ -1784,28 +1570,6 @@
<require Dendian="Big-endian"/>
</condition>
- <condition id="CM7_SP_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
- <require condition="CM7_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM7_SP_LE_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
- <require condition="CM7_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM7_DP_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
- <require condition="CM7_DP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM7_DP_LE_GCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
- <require condition="CM7_DP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM23_GCC">
<description>Cortex-M23 processor based device for the GCC Compiler</description>
<require condition="CM23"/>
@@ -1839,47 +1603,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM33_NODSP_NOFPU_GCC">
- <description>CM33, no DSP, no FPU, GCC Compiler</description>
- <require condition="CM33_NODSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_GCC">
- <description>CM33, DSP, no FPU, GCC Compiler</description>
- <require condition="CM33_DSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_NODSP_SP_GCC">
- <description>CM33, no DSP, SP FPU, GCC Compiler</description>
- <require condition="CM33_NODSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_DSP_SP_GCC">
- <description>CM33, DSP, SP FPU, GCC Compiler</description>
- <require condition="CM33_DSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM33_NODSP_NOFPU_LE_GCC">
- <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
- <require condition="CM33_NODSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_LE_GCC">
- <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
- <require condition="CM33_DSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_NODSP_SP_LE_GCC">
- <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
- <require condition="CM33_NODSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_SP_LE_GCC">
- <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
- <require condition="CM33_DSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM35P_GCC">
<description>Cortex-M35P processor based device for the GCC Compiler</description>
<require condition="CM35P"/>
@@ -1902,47 +1625,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM35P_NODSP_NOFPU_GCC">
- <description>CM35P, no DSP, no FPU, GCC Compiler</description>
- <require condition="CM35P_NODSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_GCC">
- <description>CM35P, DSP, no FPU, GCC Compiler</description>
- <require condition="CM35P_DSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_NODSP_SP_GCC">
- <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
- <require condition="CM35P_NODSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_DSP_SP_GCC">
- <description>CM35P, DSP, SP FPU, GCC Compiler</description>
- <require condition="CM35P_DSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="CM35P_NODSP_NOFPU_LE_GCC">
- <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
- <require condition="CM35P_NODSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_LE_GCC">
- <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
- <require condition="CM35P_DSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_NODSP_SP_LE_GCC">
- <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
- <require condition="CM35P_NODSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_SP_LE_GCC">
- <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
- <require condition="CM35P_DSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM55_NOFPU_NOMVE_GCC">
<description>Cortex-M55 processor, no FPU, no MVE, GCC Compiler</description>
<require condition="CM55_NOFPU_NOMVE"/>
@@ -2002,47 +1684,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="ARMv8MML_NODSP_NOFPU_GCC">
- <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_GCC">
- <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_GCC">
- <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
- <require condition="ARMv8MML_NODSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_GCC">
- <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
- <require condition="ARMv8MML_DSP_SP"/>
- <require Tcompiler="GCC"/>
- </condition>
- <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
- <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
- <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_LE_GCC">
- <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
- <require condition="ARMv8MML_NODSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_LE_GCC">
- <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
- <require condition="ARMv8MML_DSP_SP_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<!-- IAR compiler -->
<condition id="CA_IAR">
<description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
@@ -2162,38 +1803,6 @@
<require Dendian="Big-endian"/>
</condition>
- <condition id="CM7_SP_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
- <require condition="CM7_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM7_SP_LE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
- <require condition="CM7_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_SP_BE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
- <require condition="CM7_SP_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
- <condition id="CM7_DP_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
- <require condition="CM7_DP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM7_DP_LE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
- <require condition="CM7_DP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM7_DP_BE_IAR">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
- <require condition="CM7_DP_IAR"/>
- <require Dendian="Big-endian"/>
- </condition>
-
<condition id="CM23_IAR">
<description>Cortex-M23 processor based device for the IAR Compiler</description>
<require condition="CM23"/>
@@ -2227,47 +1836,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM33_NODSP_NOFPU_IAR">
- <description>CM33, no DSP, no FPU, IAR Compiler</description>
- <require condition="CM33_NODSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_IAR">
- <description>CM33, DSP, no FPU, IAR Compiler</description>
- <require condition="CM33_DSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_NODSP_SP_IAR">
- <description>CM33, no DSP, SP FPU, IAR Compiler</description>
- <require condition="CM33_NODSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_DSP_SP_IAR">
- <description>CM33, DSP, SP FPU, IAR Compiler</description>
- <require condition="CM33_DSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM33_NODSP_NOFPU_LE_IAR">
- <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
- <require condition="CM33_NODSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_NOFPU_LE_IAR">
- <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
- <require condition="CM33_DSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_NODSP_SP_LE_IAR">
- <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
- <require condition="CM33_NODSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM33_DSP_SP_LE_IAR">
- <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
- <require condition="CM33_DSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM35P_IAR">
<description>Cortex-M35P processor based device for the IAR Compiler</description>
<require condition="CM35P"/>
@@ -2290,47 +1858,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM35P_NODSP_NOFPU_IAR">
- <description>CM35P, no DSP, no FPU, IAR Compiler</description>
- <require condition="CM35P_NODSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_IAR">
- <description>CM35P, DSP, no FPU, IAR Compiler</description>
- <require condition="CM35P_DSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_NODSP_SP_IAR">
- <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
- <require condition="CM35P_NODSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_DSP_SP_IAR">
- <description>CM35P, DSP, SP FPU, IAR Compiler</description>
- <require condition="CM35P_DSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="CM35P_NODSP_NOFPU_LE_IAR">
- <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
- <require condition="CM35P_NODSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_NOFPU_LE_IAR">
- <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
- <require condition="CM35P_DSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_NODSP_SP_LE_IAR">
- <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
- <require condition="CM35P_NODSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="CM35P_DSP_SP_LE_IAR">
- <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
- <require condition="CM35P_DSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<condition id="CM55_NOFPU_NOMVE_IAR">
<description>Cortex-M55 processor, no FPU, no MVE, IAR Compiler</description>
<require condition="CM55_NOFPU_NOMVE"/>
@@ -2390,47 +1917,6 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="ARMv8MML_NODSP_NOFPU_IAR">
- <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_IAR">
- <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_IAR">
- <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
- <require condition="ARMv8MML_NODSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_IAR">
- <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
- <require condition="ARMv8MML_DSP_SP"/>
- <require Tcompiler="IAR"/>
- </condition>
- <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
- <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
- <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
- <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
- <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_NODSP_SP_LE_IAR">
- <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
- <require condition="ARMv8MML_NODSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
- <condition id="ARMv8MML_DSP_SP_LE_IAR">
- <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
- <require condition="ARMv8MML_DSP_SP_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
<!-- conditions selecting single devices and CMSIS Core -->
<condition id="ARMCM0 CMSIS">
<description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
@@ -3170,113 +2656,6 @@
</component>
<!-- CMSIS-DSP component -->
- <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Library" Cversion="1.8.0" condition="CMSIS DSP">
- <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
- <files>
- <!-- CPU independent -->
- <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
- <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
-
- <!-- CPU and Compiler dependent -->
- <!-- ARMCC -->
- <file category="library" condition="CM0_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM0_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM1_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM1_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM3_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM3l_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM3_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM3b_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4l_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM4_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4b_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4lf_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4bf_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7l_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7b_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7lfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_SP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7bfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_DP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7lfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM7_DP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7bfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
-
- <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM33_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM33_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="CM35P_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
- <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
- <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
-
- <!-- GCC -->
- <file category="library" condition="CM0_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM0l_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM1_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM0l_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM3_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM3l_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM4_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM4l_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM4lf_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM7_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM7l_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM7_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM7lfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM7_DP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM7lfdp_math.a" src="CMSIS/DSP/Source/GCC"/>
-
- <file category="library" condition="CM23_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM33_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM33_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM33_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM35P_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="CM35P_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
- <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
- <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
-
- <!-- IAR -->
- <file category="library" condition="CM0_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM0_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM1_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM1_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM3_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM3l_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM3_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM3b_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM4_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4l_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM4_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4b_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4lf_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM4_FP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4bf_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7l_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7b_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_DP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7lf_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_DP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7bf_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7ls_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM7_SP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7bs_math.a" src="CMSIS/DSP/Source/IAR"/>
-
- <file category="library" condition="CM23_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM33_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM35P_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="CM35P_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
- <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
- <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
-
- </files>
- </component>
<component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cversion="1.9.0-dev" isDefaultVariant="true" condition="CMSIS DSP">
<description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
<files>