RTX5: Fix potential register R1 corruption when calling OS functions from threads multiple times with same arguments (when using high level compiler optimizations) - #1382
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 6d58fea..8f88f40 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -15,6 +15,8 @@
- Support for int16 convolution and fully connected for reference implementation
- Support for DSP extension optimization for int16 convolution and fully connected
- Support for dilation for int8 convolution
+ CMSIS-RTOS2:
+ - RTX 5.5.4 (see revision history for details)
</release>
<release version="5.8.0" date="2021-06-24">
CMSIS-Core(M): 5.5.0 (see revision history for details)
@@ -3001,7 +3003,7 @@
</component>
<!-- CMSIS-RTOS Keil RTX5 component -->
- <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.5.3" Capiversion="1.0.0" condition="RTOS RTX5">
+ <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.5.4" Capiversion="1.0.0" condition="RTOS RTX5">
<description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
@@ -3017,7 +3019,7 @@
</component>
<!-- CMSIS-RTOS2 Keil RTX5 component -->
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5">
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5">
<description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
@@ -3107,7 +3109,7 @@
<file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
<description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
@@ -3177,7 +3179,7 @@
<file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5">
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5">
<description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
@@ -3291,7 +3293,7 @@
<file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
</files>
</component>
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
<description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
@@ -3348,7 +3350,7 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s" condition="CA_IAR"/>
</files>
</component>
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.4" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
<description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
diff --git a/CMSIS/DoxyGen/RTOS2/src/history.txt b/CMSIS/DoxyGen/RTOS2/src/history.txt
index 556892f..84f6cca 100644
--- a/CMSIS/DoxyGen/RTOS2/src/history.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/history.txt
@@ -99,6 +99,12 @@
<th>Description</th>
</tr>
<tr>
+ <td>V5.5.4</td>
+ <td>
+ - Fixed potential register R1 corruption when calling OS functions from threads multiple times with same arguments (when using high level compiler optimizations).
+ </td>
+ </tr>
+ <tr>
<td>V5.5.3</td>
<td>
- CVE-2021-27431 vulnerability mitigation.
diff --git a/CMSIS/RTOS2/RTX/Include/rtx_os.h b/CMSIS/RTOS2/RTX/Include/rtx_os.h
index 65e4227..80e2622 100644
--- a/CMSIS/RTOS2/RTX/Include/rtx_os.h
+++ b/CMSIS/RTOS2/RTX/Include/rtx_os.h
@@ -39,8 +39,8 @@
/// Kernel Information
#define osRtxVersionAPI 20010003 ///< API version (2.1.3)
-#define osRtxVersionKernel 50050003 ///< Kernel version (5.5.3)
-#define osRtxKernelId "RTX V5.5.3" ///< Kernel identification string
+#define osRtxVersionKernel 50050004 ///< Kernel version (5.5.4)
+#define osRtxKernelId "RTX V5.5.4" ///< Kernel identification string
// ==== Common definitions ====
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
index 602a818..7900d8d 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
@@ -72,7 +72,7 @@
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
- STMIA R2!,{R0-R1} ; Store function return values
+ STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
index daf5fe8..2ff43f8 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
@@ -240,7 +240,7 @@
CMP R12, #0 ; Compare SVC number
BNE SVC_User ; Branch if User SVC
- PUSH {R0-R3}
+ PUSH {R0-R3} ; Push arguments to stack
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
@@ -254,20 +254,13 @@
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Disable ; Disable OS Tick interrupt
SVC_FuncCall
- POP {R0-R3}
-
- LDR R12, [SP] ; Reload R12 from stack
+ LDM SP, {R0-R3, R12} ; Reload R0-R3 and R12 from stack
CPSIE i ; Re-enable interrupts
BLX R12 ; Branch to SVC function
CPSID i ; Disable interrupts
- SUB SP, SP, #4
- STM SP, {SP}^ ; Store SP_usr onto stack
- POP {R12} ; Pop SP_usr into R12
- SUB R12, R12, #16 ; Adjust pointer to SP_usr
- LDMDB R12, {R2,R3} ; Load return values from SVC function
- PUSH {R0-R3} ; Push return values to stack
+ STR R0, [SP] ; Store function return value
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
index 639cad6..c47e2d5 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
@@ -79,7 +79,7 @@
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
+ STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s
index d7bfd99..55d29d3 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s
@@ -83,7 +83,7 @@
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
- STMIA R2!,{R0-R1} ; Store function return values
+ STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
index 984dd2d..318fa4a 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
@@ -89,7 +89,7 @@
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
+ STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
index 8cdc84a..ef4fa75 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
@@ -68,7 +68,7 @@
ldmia r0,{r0-r3} // Load function parameters from stack
blx r7 // Call service function
pop {r2,r3} // Restore SP and EXC_RETURN
- stmia r2!,{r0-r1} // Store function return values
+ str r0,[r2] // Store function return value
mov lr,r3 // Set EXC_RETURN
SVC_Context:
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
index 9d5f44a..aa59c94 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
@@ -244,7 +244,7 @@
cmp r12, #0 // Compare SVC number
bne SVC_User // Branch if User SVC
- push {r0-r3}
+ push {r0-r3} // Push arguments to stack
ldr r0, =IRQ_NestLevel
ldr r1, [r0]
@@ -258,20 +258,13 @@
ldr r0, [r0, #I_TICK_IRQN_OFS] // Load OS Tick irqn
blx IRQ_Disable // Disable OS Tick interrupt
SVC_FuncCall:
- pop {r0-r3}
-
- ldr r12, [sp] // Reload R12 from stack
+ ldm sp, {r0-r3, r12} // Reload R0-R3 and R12 from stack
cpsie i // Re-enable interrupts
blx r12 // Branch to SVC function
cpsid i // Disable interrupts
- sub sp, sp, #4
- stm sp, {sp}^ // Store SP_usr onto stack
- pop {r12} // Pop SP_usr into R12
- sub r12, r12, #16 // Adjust pointer to SP_usr
- ldmdb r12, {r2,r3} // Load return values from SVC function
- push {r0-r3} // Push return values to stack
+ str r0, [sp] // Store function return value
ldr r0, =osRtxInfo
ldr r1, [r0, #I_K_STATE_OFS] // Load RTX5 kernel state
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
index ae2a87b..daf9871 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
@@ -75,7 +75,7 @@
ldm r0,{r0-r3,r12} // Load function parameters and address from stack
blx r12 // Call service function
pop {r12,lr} // Restore SP and EXC_RETURN
- stm r12,{r0-r1} // Store function return values
+ str r0,[r12] // Store function return value
SVC_Context:
ldr r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
index 4a6a33c..74591a6 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
@@ -75,7 +75,7 @@
ldmia r0,{r0-r3} // Load function parameters from stack
blx r7 // Call service function
pop {r2,r3} // Restore SP and EXC_RETURN
- stmia r2!,{r0-r1} // Store function return values
+ str r0,[r2] // Store function return value
mov lr,r3 // Set EXC_RETURN
SVC_Context:
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
index 0883c6b..f2d6fea 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
@@ -87,7 +87,7 @@
ldm r0,{r0-r3,r12} // Load function parameters and address from stack
blx r12 // Call service function
pop {r12,lr} // Restore SP and EXC_RETURN
- stm r12,{r0-r1} // Store function return values
+ str r0,[r12] // Store function return value
SVC_Context:
ldr r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
index 29b8bb0..a85322d 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
@@ -73,7 +73,7 @@
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
- STMIA R2!,{R0-R1} ; Store function return values
+ STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
index 9e27930..cd19875 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
@@ -229,7 +229,7 @@
CMP R12, #0 ; Compare SVC number
BNE SVC_User ; Branch if User SVC
- PUSH {R0-R3}
+ PUSH {R0-R3} ; Push arguments to stack
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
@@ -243,20 +243,13 @@
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Disable ; Disable OS Tick interrupt
SVC_FuncCall
- POP {R0-R3}
-
- LDR R12, [SP] ; Reload R12 from stack
+ LDM SP, {R0-R3, R12} ; Reload R0-R3 and R12 from stack
CPSIE i ; Re-enable interrupts
BLX R12 ; Branch to SVC function
CPSID i ; Disable interrupts
- SUB SP, SP, #4
- STM SP, {SP}^ ; Store SP_usr onto stack
- POP {R12} ; Pop SP_usr into R12
- SUB R12, R12, #16 ; Adjust pointer to SP_usr
- LDMDB R12, {R2,R3} ; Load return values from SVC function
- PUSH {R0-R3} ; Push return values to stack
+ STR R0, [SP] ; Store function return value
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
index 3b6f9cf..7903d10 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
@@ -80,7 +80,7 @@
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
+ STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s
index 9f0bf8e..5ee2e8b 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s
@@ -84,7 +84,7 @@
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
- STMIA R2!,{R0-R1} ; Store function return values
+ STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s
index 00a8422..57733f3 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s
@@ -96,7 +96,7 @@
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
+ STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
index a599516..0dec69b 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
@@ -343,8 +343,7 @@
#define SVC_Out1 "=r"(__r0)
#define SVC_CL0
-#define SVC_CL1 "r1"
-#define SVC_CL2 "r0","r1"
+#define SVC_CL1 "r0"
#define SVC_Call0(in, out, cl) \
__ASM volatile ("svc 0" : out : in : cl)
@@ -353,7 +352,7 @@
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \
+ SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1); \
}
#define SVC0_0(f,t) \
@@ -361,7 +360,7 @@
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgN(0); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \
+ SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0); \
return (t) __r0; \
}
@@ -370,7 +369,7 @@
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \
+ SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
}
#define SVC0_1(f,t,t1) \
@@ -378,7 +377,7 @@
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \
+ SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
return (t) __r0; \
}
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
index 086b1e0..5b84038 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
@@ -374,8 +374,7 @@
#define SVC_Out1 "=r"(__r0)
#define SVC_CL0
-#define SVC_CL1 "r1"
-#define SVC_CL2 "r0","r1"
+#define SVC_CL1 "r0"
#define SVC_Call0(in, out, cl) \
__ASM volatile ("svc 0" : out : in : cl)
@@ -384,7 +383,7 @@
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \
+ SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1); \
}
#define SVC0_0(f,t) \
@@ -392,7 +391,7 @@
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgN(0); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \
+ SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0); \
return (t) __r0; \
}
@@ -401,7 +400,7 @@
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \
+ SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
}
#define SVC0_1(f,t,t1) \
@@ -409,7 +408,7 @@
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(svcRtx##f); \
- SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \
+ SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
return (t) __r0; \
}