CoreValidation: Initial contribution of a test suite for validating CMSIS-Core.
diff --git a/CMSIS/CoreValidation/ARM.CMSIS-Core_Validation.pdsc b/CMSIS/CoreValidation/ARM.CMSIS-Core_Validation.pdsc
new file mode 100644
index 0000000..6a6fbcc
--- /dev/null
+++ b/CMSIS/CoreValidation/ARM.CMSIS-Core_Validation.pdsc
@@ -0,0 +1,245 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
+ <vendor>ARM</vendor>
+ <name>CMSIS-Core_Validation</name>
+ <description>CMSIS-Core Validation</description>
+ <url>http://www.keil.com/pack</url>
+ <supportContact>http://silver.arm.com/support</supportContact>
+
+ <releases>
+ <release version="1.0.0-dev1">
+ Initial release of the CMSIS-Core Validation Suite
+ </release>
+ </releases>
+
+ <keywords>
+ <keyword>ARM</keyword>
+ <keyword>CMSIS-CORE</keyword>
+ <keyword>Core Validation</keyword>
+ </keywords>
+
+ <taxonomy>
+ <description Cclass="CMSIS-Core Validation">CMSIS-Core Validation Suite</description>
+ </taxonomy>
+
+ <examples>
+ <example name="CMSIS-Core Validation MDK-FVP" doc="Abstract.txt" folder="Examples/MDK-FVP">
+ <description>CMSIS-Core Validation Example for MDK Fixed Virtual Platform</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="uv" load="CMSIS_CV.uvprojx"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ <component Cclass="Compiler" Cgroup="EventRecorder"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation DS-MDK (Cortex-A5)" doc="Abstract.txt" folder="Examples/DS-MDK/Cortex-A5">
+ <description>CMSIS-Core Validation Example for DS-MDK Fixed Virtual Platform</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="ds5" load=".project"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation DS-MDK (Cortex-A7)" doc="Abstract.txt" folder="Examples/DS-MDK/Cortex-A7">
+ <description>CMSIS-Core Validation Example for DS-MDK Fixed Virtual Platform</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="ds5" load=".project"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation DS-MDK (Cortex-A9)" doc="Abstract.txt" folder="Examples/DS-MDK/Cortex-A9">
+ <description>CMSIS-Core Validation Example for DS-MDK Fixed Virtual Platform</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="ds5" load=".project"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation DS-MDK GCC (Cortex-A9)" doc="Abstract.txt" folder="Examples/DS-MDK/Cortex-A9_GCC">
+ <description>CMSIS-Core Validation Example for DS-MDK Fixed Virtual Platform</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="ds5" load=".project"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation IAR EWARM 8 (Cortex-M0)" doc="Abstract.txt" folder="Examples/IAR-EWARM8/Cortex-M0">
+ <description>CMSIS-Core Validation Example for IAR Embedded Workbench 8</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="iar" load="CMSIS_CV.eww"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ <example name="CMSIS-Core Validation IAR EWARM 8 (Cortex-A9)" doc="Abstract.txt" folder="Examples/IAR-EWARM8/Cortex-A9">
+ <description>CMSIS-Core Validation Example for IAR Embedded Workbench 8</description>
+ <board name="Fixed Virtual Platform" vendor="ARM"/>
+ <project>
+ <environment name="iar" load="CMSIS_CV.eww"/>
+ </project>
+ <attributes>
+ <component Cclass="CMSIS" Cgroup="CORE"/>
+ <component Cclass="Device" Cgroup="Startup"/>
+ </attributes>
+ </example>
+
+ </examples>
+
+ <conditions>
+
+ <!-- ARM architecture -->
+ <condition id="ARMv6-M Device">
+ <description>ARMv6-M architecture based device</description>
+ <accept Dcore="Cortex-M0"/>
+ <accept Dcore="Cortex-M0+"/>
+ <accept Dcore="SC000"/>
+ </condition>
+ <condition id="ARMv7-M Device">
+ <description>ARMv7-M architecture based device</description>
+ <accept Dcore="Cortex-M3"/>
+ <accept Dcore="Cortex-M4"/>
+ <accept Dcore="Cortex-M7"/>
+ <accept Dcore="SC300"/>
+ </condition>
+ <condition id="ARMv8-M Device">
+ <description>ARMv8-M architecture based device</description>
+ <accept Dcore="ARMV8MBL"/>
+ <accept Dcore="ARMV8MML"/>
+ <accept Dcore="Cortex-M23"/>
+ <accept Dcore="Cortex-M33"/>
+ </condition>
+ <condition id="ARMv8-M TZ Device">
+ <description>ARMv8-M architecture based device with TrustZone</description>
+ <require condition="ARMv8-M Device"/>
+ <require Dtz="TZ"/>
+ </condition>
+ <condition id="ARMv6_7-M Device">
+ <description>ARMv6_7-M architecture based device</description>
+ <accept condition="ARMv6-M Device"/>
+ <accept condition="ARMv7-M Device"/>
+ </condition>
+ <condition id="ARMv6_7_8-M Device">
+ <description>ARMv6_7_8-M architecture based device</description>
+ <accept condition="ARMv6-M Device"/>
+ <accept condition="ARMv7-M Device"/>
+ <accept condition="ARMv8-M Device"/>
+ </condition>
+ <condition id="ARMv7-A Device">
+ <description>ARMv7-A architecture based device</description>
+ <accept Dcore="Cortex-A5"/>
+ <accept Dcore="Cortex-A7"/>
+ <accept Dcore="Cortex-A9"/>
+ </condition>
+
+ <condition id="CMSIS-Core">
+ <description>CMSIS-Core for Cortex-M and Cortex-A</description>
+ <accept condition="ARMv6_7_8-M Device"/>
+ <accept condition="ARMv7-A Device"/>
+ <require Cclass="CMSIS" Cgroup="CORE"/>
+ </condition>
+
+ <condition id="CMSIS-Core Validation Framework">
+ <description>CMSIS-Core Validation Framework</description>
+ <require condition="CMSIS-Core"/>
+ <require Cclass="CMSIS-Core Validation" Cgroup="Framework"/>
+ </condition>
+
+ <condition id="MPU Tests">
+ <description>Cortex-M MPU Tests</description>
+ <require condition="CMSIS-Core Validation Framework"/>
+ <require condition="ARMv6_7_8-M Device"/>
+ </condition>
+
+ <condition id="Generic Timer Tests">
+ <description>Cortex-A Generic Timer Tests</description>
+ <require condition="CMSIS-Core Validation Framework"/>
+ <require Dcore="Cortex-A7"/>
+ </condition>
+
+ </conditions>
+
+ <components>
+
+ <component Cgroup="Framework" Cclass="CMSIS-Core Validation" Cversion="1.0.0" condition="CMSIS-Core">
+ <description>Test framework</description>
+ <files>
+ <!-- file category="doc" name="Documents/CV/html/index.html"/ -->
+ <file category="include" name="Include/"/>
+ <file category="header" name="Include/cmsis_cv.h"/>
+ <file category="header" name="Source/Config/CV_Config.h" attr="config" version = "1.0.0" condition="ARMv6_7_8-M Device"/>
+ <file category="header" name="Source/ConfigA/CV_Config.h" attr="config" version = "1.0.0" condition="ARMv7-A Device"/>
+ <file category="source" name="Source/cmsis_cv.c"/>
+ <file category="source" name="Source/CV_Framework.c"/>
+ <file category="source" name="Source/CV_Report.c"/>
+ </files>
+ </component>
+
+ <component Cgroup="CoreInstr" Cclass="CMSIS-Core Validation" Cversion="1.0.0" condition="CMSIS-Core Validation Framework">
+ <description>Core Instructions</description>
+ <RTE_Components_h>
+ #define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+ </RTE_Components_h>
+ <files>
+ <file category="source" name="Source/CV_CoreInstr.c"/>
+ </files>
+ </component>
+
+ <component Cgroup="CoreFunc" Cclass="CMSIS-Core Validation" Cversion="1.0.0" condition="CMSIS-Core Validation Framework">
+ <description>Core Functions</description>
+ <RTE_Components_h>
+ #define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+ </RTE_Components_h>
+ <files>
+ <file category="source" name="Source/CV_CoreFunc.c" condition="ARMv6_7_8-M Device"/>
+ <file category="source" name="Source/CV_CoreAFunc.c" condition="ARMv7-A Device"/>
+ </files>
+ </component>
+
+ <component Cgroup="MPUFunc" Cclass="CMSIS-Core Validation" Cversion="1.0.0" condition="MPU Tests">
+ <description>MPU Functions</description>
+ <RTE_Components_h>
+ #define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+ </RTE_Components_h>
+ <files>
+ <file category="source" name="Source/CV_MPU_ARMv7.c" condition="ARMv6_7-M Device"/>
+ <file category="source" name="Source/CV_MPU_ARMv8.c" condition="ARMv8-M Device"/>
+ </files>
+ </component>
+
+ <component Cgroup="GenTimer" Cclass="CMSIS-Core Validation" Cversion="1.0.0" condition="Generic Timer Tests">
+ <description>Generic Timer</description>
+ <RTE_Components_h>
+ #define RTE_CV_GENTIMER /* CORE Validation - Generic Timer tests enabled */
+ </RTE_Components_h>
+ <files>
+ <file category="source" name="Source/CV_GenTimer.c"/>
+ </files>
+ </component>
+ </components> <!-- end of components sections -->
+</package>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.cproject b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.cproject
new file mode 100644
index 0000000..c02f706
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.cproject
@@ -0,0 +1,245 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+ <extensions>
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+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.project b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.project
new file mode 100644
index 0000000..a33ede9
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.project
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>CMSIS_CV</name>
+ <comment></comment>
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+ </projects>
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+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
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+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>com.arm.cmsis.pack.project.RteNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/Device/ARMCA5/irq_ctrl_gic.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+ </link>
+ </linkedResources>
+ <variableList>
+ <variable>
+ <name>cmsis_pack_root</name>
+ <value>file:/C:/tools/Keil_v5/ARM/PACK</value>
+ </variable>
+ </variableList>
+</projectDescription>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/language.settings.xml b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/language.settings.xml
new file mode 100644
index 0000000..e2f040f
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
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+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A5 (AC6)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="299109064629967612" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..edee6e3
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/Abstract.txt b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/CMSIS_CV.rteconfig b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/CMSIS_CV.rteconfig
new file mode 100644
index 0000000..05dd037
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/CMSIS_CV.rteconfig
@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="ARMCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA5/Include/"/>
+<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca5</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/CMSIS_CORE_Validation/CV_Config.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/CMSIS_CORE_Validation/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/CMSIS_CORE_Validation/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/ARMCA5.sct b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/ARMCA5.sct
new file mode 100644
index 0000000..7eba725
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/ARMCA5.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mem_ARMCA5.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mem_ARMCA5.h
new file mode 100644
index 0000000..10efc94
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mem_ARMCA5.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA5.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mmu_ARMCA5.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mmu_ARMCA5.c
new file mode 100644
index 0000000..1633bd7
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/mmu_ARMCA5.c
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA5.c
+ * @brief MMU Configuration for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/startup_ARMCA5.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/startup_ARMCA5.c
new file mode 100644
index 0000000..6cf9cb3
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/startup_ARMCA5.c
@@ -0,0 +1,151 @@
+/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+ PRESERVE8
+
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+ PRESERVE8
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exceptional mode
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __main
+ IMPORT __main
+ BL __main
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.c
new file mode 100644
index 0000000..a8a272c
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.h
new file mode 100644
index 0000000..7d48ceb
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/Device/ARMCA5/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/RTE_Components.h
new file mode 100644
index 0000000..2589e4a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/RTE_Components.h
@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV
+ * RTE configuration: CMSIS_CV.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA5.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/main.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.cproject b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.cproject
new file mode 100644
index 0000000..8ae1a76
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.cproject
@@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A7 (AC5)">
+ <externalSettings/>
+ <extensions>
+ <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+ <option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="vfpv4" valueType="string"/>
+ <option id="com.arm.tool.assembler.v6.base.option.floatabi.1026121137" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.option.inst.1080491485" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.useMicroLib.505841516" name="Use microlib (--pd "__MICROLIB SETA 1")" superClass="com.arm.tool.assembler.v6.base.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.assembler.v6.base.option.warnall.1061553577" name="All Warnings (-Wall)" superClass="com.arm.tool.assembler.v6.base.option.warnall" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.assembler.v6.base.option.endian.1099452024" name="Byte order" superClass="com.arm.tool.assembler.v6.base.option.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.option.implicit.defmac.1870542989" name="Implicit Define macros" superClass="com.arm.tool.assembler.v6.base.option.implicit.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA7"/>
+ </option>
+ <option id="com.arm.tool.assembler.v6.base.option.implicit.incpath.1158607348" name="Implicit Include paths" superClass="com.arm.tool.assembler.v6.base.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7""/>
+ </option>
+ <inputType id="com.arm.tool.assembler.v6.base.input.1152692029" superClass="com.arm.tool.assembler.v6.base.input"/>
+ </tool>
+ <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1430743479" name="ARM Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
+ <option id="com.arm.tool.linker.v6.option.useMicroLib.2004205067" name="Use microlib" superClass="com.arm.tool.linker.v6.option.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.c.linker.option.entry.2110377742" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
+ <option id="com.arm.tool.c.linker.option.scatter.907632347" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7/ARMCA7.sct" valueType="string"/>
+ </tool>
+ <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.177548875" name="ARM Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+ </toolChain>
+ </folderInfo>
+ <sourceEntries>
+ <entry excluding="RTE/Device/ARMCA9/system_ARMCA9.h|RTE/Device/ARMCA9/system_ARMCA9.c|RTE/Device/ARMCA9/startup_ARMCA9.c|RTE/Device/ARMCA9/mmu_ARMCA9.c|RTE/Device/ARMCA9/mem_ARMCA9.h|RTE/Device/ARMCA9/ARMCA9.sct" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="com.arm.cmsis.project">
+ <rteConfig name="CMSIS_CV.rteconfig"/>
+ <toolChainAdapter id="com.arm.cmsis.pack.build.armcc5.Armcc5ToolChainAdapter" name="Adapter for ARM C/C++ 5.x and 6.x toolchains"/>
+ <device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="DP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname=""/>
+ <files>
+ <file name="RTE/Device/ARMCA9/ARMCA9.sct" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/ARMCA7.sct" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/ARMCA5.sct" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
+ <file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/mmu_ARMCA5.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/system_ARMCA7.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/system_ARMCA5.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/system_ARMCA5.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/mem_ARMCA5.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/mem_ARMCA7.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/system_ARMCA7.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA5/startup_ARMCA5.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/startup_ARMCA7.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
+ </files>
+ </storageModule>
+ <storageModule moduleId="com.arm.projectSettings" version="5.25"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Debug">
+ <resource resourceType="PROJECT" workspacePath="/CMSIS_CV"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.project b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.project
new file mode 100644
index 0000000..5c2e3fc
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.project
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>CMSIS_CV</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>com.arm.cmsis.pack.project.RteNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/Device/ARMCA7/irq_ctrl_gic.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+ </link>
+ </linkedResources>
+ <variableList>
+ <variable>
+ <name>cmsis_pack_root</name>
+ <value>file:/C:/tools/Keil_v5/ARM/PACK</value>
+ </variable>
+ </variableList>
+</projectDescription>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/language.settings.xml b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/language.settings.xml
new file mode 100644
index 0000000..85eefc4
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A7 (AC5)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A7 (AC6)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="413551431901398524" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..edee6e3
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/Abstract.txt b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/CMSIS_CV.rteconfig b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/CMSIS_CV.rteconfig
new file mode 100644
index 0000000..9ad2dc6
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/CMSIS_CV.rteconfig
@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="ARMCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA7/Include/"/>
+<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/system_ARMCA7.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="DP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca7</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/CMSIS_CORE_Validation/CV_Config.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/CMSIS_CORE_Validation/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/CMSIS_CORE_Validation/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/ARMCA7.sct b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/ARMCA7.sct
new file mode 100644
index 0000000..b5677de
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/ARMCA7.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA7.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mem_ARMCA7.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mem_ARMCA7.h
new file mode 100644
index 0000000..70e402e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mem_ARMCA7.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA7.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA7_H
+#define __MEM_ARMCA7_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA7_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mmu_ARMCA7.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mmu_ARMCA7.c
new file mode 100644
index 0000000..d65df5e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/mmu_ARMCA7.c
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA7.c
+ * @brief MMU Configuration for ARM Cortex-A7 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA7.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A7_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/startup_ARMCA7.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/startup_ARMCA7.c
new file mode 100644
index 0000000..47ef974
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/startup_ARMCA7.c
@@ -0,0 +1,151 @@
+/******************************************************************************
+ * @file startup_ARMCA7.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+ PRESERVE8
+
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+ PRESERVE8
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exceptional mode
+ IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+ IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+ IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+ IMPORT |Image$$UND_STACK$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ CPS #0x11
+ LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+ CPS #0x12
+ LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+ CPS #0x13
+ LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
+ CPS #0x17
+ LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
+ CPS #0x1B
+ LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
+ CPS #0x1F
+ LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ // Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __main
+ IMPORT __main
+ BL __main
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.c
new file mode 100644
index 0000000..77a9780
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA7.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.h
new file mode 100644
index 0000000..7012680
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/Device/ARMCA7/system_ARMCA7.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA7.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/RTE_Components.h
new file mode 100644
index 0000000..c33455d
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/RTE_Components.h
@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV
+ * RTE configuration: CMSIS_CV.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA7.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/main.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.cproject b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.cproject
new file mode 100644
index 0000000..7ea94e8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.cproject
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A9 (AC5)">
+ <externalSettings/>
+ <extensions>
+ <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A9 (AC5)" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+ <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
+ <toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
+ <option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A9.VFPv3_FP16.Neon" valueType="string"/>
+ <option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+ <option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+ <option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+ <targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
+ <builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+ <tool id="com.arm.tool.c.compiler.base.var.arm_compiler_5-5.1006008870" name="ARM C Compiler 5" superClass="com.arm.tool.c.compiler.base.var.arm_compiler_5-5">
+ <option id="com.arm.tool.c.compiler.option.incpath.2039211042" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ <option id="com.arm.tool.c.compiler.option.defmac.1773701319" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.882659687" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
+ <option id="com.arm.tool.c.compiler.option.targetcpu.1426497902" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A9" valueType="string"/>
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+ <option id="com.arm.tool.c.compiler.option.useMicroLib.829868509" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.option.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.c.compiler.option.implicit.defmac.768550198" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <option id="com.arm.tool.c.compiler.option.implicit.incpath.2077192262" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ <option id="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings.393339148" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings" value="false" valueType="boolean"/>
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+ <tool id="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5.1697853860" name="ARM C++ Compiler 5" superClass="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5">
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+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
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+ <option id="com.arm.tool.c.compiler.option.implicit.incpath.1172356175" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
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+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
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+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ </tool>
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+ <listOptionValue builtIn="false" value="_RTE_ SETA 1"/>
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+ <option id="com.arm.tool.assembler.option.implicit.incpath.840007947" name="Implicit Include paths" superClass="com.arm.tool.assembler.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
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+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
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+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
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+ <file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
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+ </storageModule>
+ <storageModule moduleId="com.arm.projectSettings" version="5.25"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Debug">
+ <resource resourceType="PROJECT" workspacePath="/CMSIS_CV"/>
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+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
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diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.project b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.project
new file mode 100644
index 0000000..d21819e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.project
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>CMSIS_CV</name>
+ <comment></comment>
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+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>com.arm.cmsis.pack.project.RteNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/Device/ARMCA9/irq_ctrl_gic.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/language.settings.xml b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/language.settings.xml
new file mode 100644
index 0000000..9b9be7b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A9 (AC5)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A9 (AC6)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="308886176073646716" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..edee6e3
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/Abstract.txt b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/CMSIS_CV.rteconfig b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/CMSIS_CV.rteconfig
new file mode 100644
index 0000000..1838886
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/CMSIS_CV.rteconfig
@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="ARMCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA9/Include/"/>
+<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/system_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA9/Include/system_ARMCA9.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A9" DcoreVersion="r4p1" Dendian="Little-endian" Dfamily="ARM Cortex A9" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA9" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca9</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/CMSIS_CORE_Validation/CV_Config.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/CMSIS_CORE_Validation/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/CMSIS_CORE_Validation/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/ARMCA9.sct b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/ARMCA9.sct
new file mode 100644
index 0000000..3316f93
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/ARMCA9.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA9.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE
+ -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mem_ARMCA9.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mem_ARMCA9.h
new file mode 100644
index 0000000..4bebfdf
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mem_ARMCA9.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA9.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA9_H
+#define __MEM_ARMCA9_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mmu_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mmu_ARMCA9.c
new file mode 100644
index 0000000..960808e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/mmu_ARMCA9.c
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA9.c
+ * @brief MMU Configuration for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA9.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A9_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/startup_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/startup_ARMCA9.c
new file mode 100644
index 0000000..e0a6ed7
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/startup_ARMCA9.c
@@ -0,0 +1,144 @@
+/******************************************************************************
+ * @file startup_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA9.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+
+/** \brief Exception and Interrupt Handler Jumptable.
+*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+
+/** \brief Reset Handler
+*/
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.c
new file mode 100644
index 0000000..aa26f1b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.h
new file mode 100644
index 0000000..97e3d39
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/Device/ARMCA9/system_ARMCA9.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA9.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA9_H
+#define __SYSTEM_ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/RTE_Components.h
new file mode 100644
index 0000000..007390a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/RTE/RTE_Components.h
@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV
+ * RTE configuration: CMSIS_CV.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA9.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/main.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.cproject b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.cproject
new file mode 100644
index 0000000..a92c843
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.cproject
@@ -0,0 +1,413 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
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+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
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+ <option id="com.arm.tool.c.compiler.v6.base.option.implicit.defmac.157256109" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.v6.base.option.implicit.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <option id="com.arm.tool.c.compiler.v6.base.option.implicit.incpath.2073821818" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.v6.base.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ <option id="com.arm.tool.c.compiler.v6.base.option.defmac.348012293" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <option id="com.arm.tool.c.compiler.v6.base.option.incpath.824110781" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ </tool>
+ <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.475165834" name="ARM Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
+ <option id="com.arm.tool.assembler.v6.base.option.incpath.512319760" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ <option defaultValue="com.arm.tool.assembler.v6.base.options.debug.level.std" id="com.arm.tool.assembler.v6.base.options.debug.level.1754017057" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.option.cpu.1440642309" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" value="cortex-a9" valueType="string"/>
+ <option id="com.arm.tool.assembler.v6.base.option.target.2099316555" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" value="arm-arm-none-eabi" valueType="string"/>
+ <option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="neon-fp16" valueType="string"/>
+ <option id="com.arm.tool.assembler.v6.base.option.floatabi.1026121137" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.option.inst.1080491485" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.useMicroLib.505841516" name="Use microlib (--pd "__MICROLIB SETA 1")" superClass="com.arm.tool.assembler.v6.base.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.assembler.v6.base.option.warnall.1061553577" name="All Warnings (-Wall)" superClass="com.arm.tool.assembler.v6.base.option.warnall" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.assembler.v6.base.option.endian.1099452024" name="Byte order" superClass="com.arm.tool.assembler.v6.base.option.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+ <option id="com.arm.tool.assembler.v6.base.option.implicit.defmac.1870542989" name="Implicit Define macros" superClass="com.arm.tool.assembler.v6.base.option.implicit.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <option id="com.arm.tool.assembler.v6.base.option.implicit.incpath.1158607348" name="Implicit Include paths" superClass="com.arm.tool.assembler.v6.base.option.implicit.incpath" valueType="includePath">
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include""/>
+ <listOptionValue builtIn="false" value=""${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9""/>
+ </option>
+ <option id="com.arm.tool.assembler.v6.base.option.defmac.2103727520" name="Define macro (-D)" superClass="com.arm.tool.assembler.v6.base.option.defmac" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="_RTE_"/>
+ <listOptionValue builtIn="false" value="ARMCA9"/>
+ </option>
+ <inputType id="com.arm.tool.assembler.v6.base.input.1152692029" superClass="com.arm.tool.assembler.v6.base.input"/>
+ </tool>
+ <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1430743479" name="ARM Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
+ <option id="com.arm.tool.linker.v6.option.useMicroLib.2004205067" name="Use microlib" superClass="com.arm.tool.linker.v6.option.useMicroLib" value="true" valueType="boolean"/>
+ <option id="com.arm.tool.c.linker.option.entry.2110377742" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
+ <option id="com.arm.tool.c.linker.option.scatter.907632347" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9/ARMCA9.sct" valueType="string"/>
+ </tool>
+ <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.177548875" name="ARM Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.2036454939;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1738674007">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="com.arm.cmsis.project">
+ <rteConfig name="CMSIS_CV.rteconfig"/>
+ <toolChainAdapter id="com.arm.cmsis.pack.build.gnuarmeclipse.toolChainAdapter" name="Cross ARM GCC Toolchain Adapter"/>
+ <device Dcore="Cortex-A9" DcoreVersion="r4p1" Dendian="Little-endian" Dfamily="ARM Cortex A9" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA9" Dvendor="ARM:82" Pname=""/>
+ <files>
+ <file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
+ <file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/system_ARMCA7.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/mem_ARMCA7.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA7/system_ARMCA7.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/ARMCA9.ld" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+ <file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
+ </files>
+ </storageModule>
+</cproject>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.project b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.project
new file mode 100644
index 0000000..d21819e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.project
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>CMSIS_CV</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>com.arm.cmsis.pack.project.RteNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+ </link>
+ <link>
+ <name>RTE/Device/ARMCA9/irq_ctrl_gic.c</name>
+ <type>1</type>
+ <locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/language.settings.xml b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/language.settings.xml
new file mode 100644
index 0000000..b2f6a4b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/language.settings.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704" name="Cortex-A9">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="270393908449436693" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A9 (AC5)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler5LanguageSettingsProvider" console="false" env-hash="778805395380471734" id="com.arm.eclipse.builder.armcc.v5.langprovider" keep-relative-paths="false" name="ARM Compiler 5 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} --list-macros "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="com.arm.eclipse.builder.armcc.lang.c"/>
+ <language-scope id="com.arm.eclipse.builder.armcc.lang.cpp"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A9 (AC6)">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="308886176073646716" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..ad47c49
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/CPATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/CPATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/append=true
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/appendContributed=true
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/append=true
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/appendContributed=true
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/Abstract.txt b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/CMSIS_CV.rteconfig b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/CMSIS_CV.rteconfig
new file mode 100644
index 0000000..d12bb16
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/CMSIS_CV.rteconfig
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="GCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA9/Include/"/>
+<file attr="config" category="sourceC" condition="GCC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="other" condition="GCC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/system_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA9/Include/system_ARMCA9.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A9" DcoreVersion="r4p1" Dendian="Little-endian" Dfamily="ARM Cortex A9" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA9" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca9</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/CMSIS_CORE_Validation/CV_Config.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/CMSIS_CORE_Validation/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/CMSIS_CORE_Validation/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/ARMCA9.ld b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/ARMCA9.ld
new file mode 100644
index 0000000..ee3d836
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/ARMCA9.ld
@@ -0,0 +1,181 @@
+#include "mem_ARMCA9.h"
+
+MEMORY
+{
+ ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
+ RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+
+ Image$$VECTORS$$Base = .;
+ * (RESET)
+ KEEP(*(.isr_vector))
+ Image$$VECTORS$$Limit = .;
+
+ *(SVC_TABLE)
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ Image$$RO_DATA$$Base = .;
+ *(.rodata*)
+ Image$$RO_DATA$$Limit = .;
+
+ KEEP(*(.eh_frame*))
+ } > ROM
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > ROM
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ROM
+ __exidx_end = .;
+
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ __copy_table_end__ = .;
+ } > ROM
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > ROM
+
+ __etext = .;
+
+ .ttb :
+ {
+ Image$$TTB$$ZI$$Base = .;
+ . += __TTB_SIZE;
+ Image$$TTB$$ZI$$Limit = .;
+ } > L_TTB
+
+ .data : AT (__etext)
+ {
+ Image$$RW_DATA$$Base = .;
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ Image$$RW_DATA$$Limit = .;
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss ALIGN(0x400):
+ {
+ Image$$ZI_DATA$$Base = .;
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$ZI_DATA$$Limit = .;
+ __end__ = .;
+ end = __end__;
+ } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ Image$$HEAP$$ZI$$Base = .;
+ . += __HEAP_SIZE;
+ Image$$HEAP$$ZI$$Limit = .;
+ __HeapLimit = .;
+ } > RAM
+#endif
+
+ .stack (NOLOAD):
+ {
+ . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+ . = ALIGN(8);
+
+ __StackTop = .;
+ Image$$SYS_STACK$$ZI$$Base = .;
+ . += __STACK_SIZE;
+ Image$$SYS_STACK$$ZI$$Limit = .;
+ __stack = .;
+
+ Image$$FIQ_STACK$$ZI$$Base = .;
+ . += __FIQ_STACK_SIZE;
+ Image$$FIQ_STACK$$ZI$$Limit = .;
+
+ Image$$IRQ_STACK$$ZI$$Base = .;
+ . += __IRQ_STACK_SIZE;
+ Image$$IRQ_STACK$$ZI$$Limit = .;
+
+ Image$$SVC_STACK$$ZI$$Base = .;
+ . += __SVC_STACK_SIZE;
+ Image$$SVC_STACK$$ZI$$Limit = .;
+
+ Image$$ABT_STACK$$ZI$$Base = .;
+ . += __ABT_STACK_SIZE;
+ Image$$ABT_STACK$$ZI$$Limit = .;
+
+ Image$$UND_STACK$$ZI$$Base = .;
+ . += __UND_STACK_SIZE;
+ Image$$UND_STACK$$ZI$$Limit = .;
+
+ } > RAM
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mem_ARMCA9.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mem_ARMCA9.h
new file mode 100644
index 0000000..4bebfdf
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mem_ARMCA9.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA9.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA9_H
+#define __MEM_ARMCA9_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mmu_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mmu_ARMCA9.c
new file mode 100644
index 0000000..179500f
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/mmu_ARMCA9.c
@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA9.c
+ * @brief MMU Configuration for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA9.h"
+#include "mem_ARMCA9.h"
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, __TTB_BASE, 1, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A9_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/startup_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/startup_ARMCA9.c
new file mode 100644
index 0000000..8374fdb
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/startup_ARMCA9.c
@@ -0,0 +1,144 @@
+/******************************************************************************
+ * @file startup_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA9.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+
+/** \brief Exception and Interrupt Handler Jumptable.
+*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+
+/** \brief Reset Handler
+*/
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL _start \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.c
new file mode 100644
index 0000000..aa26f1b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.h
new file mode 100644
index 0000000..97e3d39
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/Device/ARMCA9/system_ARMCA9.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA9.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA9_H
+#define __SYSTEM_ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/RTE_Components.h
new file mode 100644
index 0000000..007390a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/RTE_Components.h
@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV
+ * RTE configuration: CMSIS_CV.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA9.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/main.c b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.ewp
new file mode 100644
index 0000000..f75833a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mem_ARMCA9.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mem_ARMCA9.h
new file mode 100644
index 0000000..4bebfdf
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mem_ARMCA9.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA9.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA9_H
+#define __MEM_ARMCA9_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mmu_ARMCA9.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mmu_ARMCA9.c
new file mode 100644
index 0000000..960808e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/mmu_ARMCA9.c
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA9.c
+ * @brief MMU Configuration for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA9.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A9_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.c
new file mode 100644
index 0000000..aa26f1b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA9.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.h
new file mode 100644
index 0000000..97e3d39
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/CMSIS/ARM/system_ARMCA9.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA9.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA9_H
+#define __SYSTEM_ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/RTE_Components.h
new file mode 100644
index 0000000..a73629c
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/RTE/RTE_Components.h
@@ -0,0 +1,17 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCA9' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCA9.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-A9/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.ewp
new file mode 100644
index 0000000..59cda26
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/startup_ARMCM0.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..34caef0
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/startup_ARMCM0.s
@@ -0,0 +1,270 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/system_ARMCM0.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/system_ARMCM0.c
new file mode 100644
index 0000000..bb0d5eb
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/CMSIS/ARM/system_ARMCM0.c
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/RTE_Components.h
new file mode 100644
index 0000000..b8bb1c6
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM0' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM0.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M0/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.ewp
new file mode 100644
index 0000000..3f3e357
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.ewp
@@ -0,0 +1,1145 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>29</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Debug\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Debug\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Debug\List</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>8.11.2.13604</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>8.11.2.13604</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>25</version>
+ <state>57</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
+ </option>
+ <option>
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+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.1.1-dev1}$\CMSIS\Documentation\Core\html\index.html</name>
+ </file>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.1.1-dev1}$\CMSIS\Include\tz_context.h</name>
+ </file>
+ </group>
+ <group>
+ <name>CMSIS CORE Validation CoreFunc</name>
+ <tag>CMSISPack.Component</tag>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\CV_CoreFunc.c</name>
+ </file>
+ </group>
+ <group>
+ <name>CMSIS CORE Validation CoreInstr</name>
+ <tag>CMSISPack.Component</tag>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\CV_CoreInstr.c</name>
+ </file>
+ </group>
+ <group>
+ <name>CMSIS CORE Validation Framework</name>
+ <tag>CMSISPack.Component</tag>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\cmsis_cv.c</name>
+ </file>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Include\cmsis_cv.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\RTE\CMSIS-CORE_Validation\ARM\CV_Config.h</name>
+ </file>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\CV_Framework.c</name>
+ </file>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\CV_Report.c</name>
+ </file>
+ </group>
+ <group>
+ <name>CMSIS CORE Validation MPUFunc</name>
+ <tag>CMSISPack.Component</tag>
+ <file>
+ <name>${CMSIS_PACK_PATH_ARM#CMSIS-CORE_Validation#1.0.0-dev1}$\Source\CV_MPU_ARMv8.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Device Startup</name>
+ <tag>CMSISPack.Component</tag>
+ <file>
+ <name>$PROJ_DIR$\RTE\CMSIS\ARM\partition_ARMCM23.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\RTE\CMSIS\ARM\startup_ARMCM23.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\RTE\CMSIS\ARM\system_ARMCM23.c</name>
+ </file>
+ </group>
+ </group>
+ <cmsisPackSettings>
+ <rte><?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="IAR" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core/html/index.html"/>
+<file category="include" name="CMSIS/Include/"/>
+<file category="header" condition="ARMv8-M TZ Device" name="CMSIS/Include/tz_context.h"/>
+<file attr="template" category="sourceC" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c" select="Secure mode 'main' module for ARMv8-M" version="1.1.0"/>
+<file attr="template" category="sourceC" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" select="RTOS Context Management (TrustZone for ARMv8-M)" version="1.1.0"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-Core_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv6_7_8-M Device" name="Source/CV_CoreFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-Core_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-Core_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv6_7_8-M Device" name="Source/Config/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="MPUFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-Core_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv8-M Device" name="Source/CV_MPU_ARMv8.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCM23/Include/"/>
+<file attr="config" category="header" condition="ARMv8-M TZ Device" deviceDependent="1" name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0"/>
+</component>
+</components>
+<apis/>
+<device Dclock="10000000" Dcore="Cortex-M23" DcoreVersion="r0p0" Dendian="Little-endian" Dfamily="ARM Cortex M23" Dfpu="NO_FPU" Dmpu="MPU" Dname="ARMCM23_TZ" Dtz="TZ" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armcm23_tz</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>
+</rte>
+ </cmsisPackSettings>
+</project>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/partition_ARMCM23.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/partition_ARMCM23.h
new file mode 100644
index 0000000..f2354ee
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/partition_ARMCM23.h
@@ -0,0 +1,1232 @@
+/**************************************************************************//**
+ * @file partition_ARMCM23.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
+ * @version V5.00
+ * @date 28. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM23_H
+#define PARTITION_ARMCM23_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+
+/*
+// <e>Setup behaviour of single SysTick
+*/
+#define SCB_ICSR_INIT 0
+
+/*
+// <o> in a single SysTick implementation, SysTick is
+// <0=>Secure
+// <1=>Non-Secure
+// <i> Value for SCB->ICSR register bit STTNS
+// <i> only for single SysTick implementation
+*/
+#define SCB_ICSR_STTNS_VAL 0
+
+/*
+// </e>
+*/
+
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x0000122B
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
+ SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
+ ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
+ #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM23_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/startup_ARMCM23.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/startup_ARMCM23.s
new file mode 100644
index 0000000..40fd786
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/startup_ARMCM23.s
@@ -0,0 +1,272 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM23.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM23 Device Series
+; * @version V5.00
+; * @date 21. October 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/system_ARMCM23.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/system_ARMCM23.c
new file mode 100644
index 0000000..0bfd52b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/CMSIS/ARM/system_ARMCM23.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+ * @file system_ARMCM23.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM23 Device Series
+ * @version V5.00
+ * @date 21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM23.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/RTE_Components.h
new file mode 100644
index 0000000..7365f89
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM23_TZ' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM23_TZ.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M23/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.ewp
new file mode 100644
index 0000000..9c3cc53
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/startup_ARMCM3.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..81f28ce
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/startup_ARMCM3.s
@@ -0,0 +1,292 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/system_ARMCM3.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/system_ARMCM3.c
new file mode 100644
index 0000000..658d154
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/CMSIS/ARM/system_ARMCM3.c
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/RTE_Components.h
new file mode 100644
index 0000000..0c01ce4
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM3' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM3.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M3/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.ewp
new file mode 100644
index 0000000..5053a82
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/partition_ARMCM33.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/partition_ARMCM33.h
new file mode 100644
index 0000000..f0a4f1b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/partition_ARMCM33.h
@@ -0,0 +1,1260 @@
+/**************************************************************************//**
+ * @file partition_ARMCM33.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
+ * @version V5.0.1
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM33_H
+#define PARTITION_ARMCM33_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// <o>Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x0000122B
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM33_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/startup_ARMCM33.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/startup_ARMCM33.s
new file mode 100644
index 0000000..505632c
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/startup_ARMCM33.s
@@ -0,0 +1,297 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM33.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM33 Device Series
+; * @version V5.00
+; * @date 21. October 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD SecureFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SecureFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SecureFault_Handler
+ B SecureFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/system_ARMCM33.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/system_ARMCM33.c
new file mode 100644
index 0000000..9ad7594
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/CMSIS/ARM/system_ARMCM33.c
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file system_ARMCM33.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM33 Device Series
+ * @version V5.00
+ * @date 02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/RTE_Components.h
new file mode 100644
index 0000000..6c6752d
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM33_DSP_FP_TZ' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M33/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.ewp
new file mode 100644
index 0000000..c3a3121
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/startup_ARMCM4.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..689e85d
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/startup_ARMCM4.s
@@ -0,0 +1,292 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/system_ARMCM4.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/system_ARMCM4.c
new file mode 100644
index 0000000..af23005
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/CMSIS/ARM/system_ARMCM4.c
@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file system_ARMCM4.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/RTE_Components.h
new file mode 100644
index 0000000..ff7f6e2
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM4_FP' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM4_FP.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M4/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/Abstract.txt b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.ewp b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.ewp
new file mode 100644
index 0000000..c838e8e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.ewp
Binary files differ
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.eww b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.eww
new file mode 100644
index 0000000..eda1d20
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/CMSIS_CV.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+ <project>
+ <path>$WS_DIR$\CMSIS_CV.ewp</path>
+ </project>
+ <batchBuild />
+</workspace>
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS-CORE_Validation/ARM/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/startup_ARMCM7.s b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/startup_ARMCM7.s
new file mode 100644
index 0000000..002c438
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/startup_ARMCM7.s
@@ -0,0 +1,292 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM7.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM7 Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/system_ARMCM7.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/system_ARMCM7.c
new file mode 100644
index 0000000..22edd9c
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/CMSIS/ARM/system_ARMCM7.c
@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file system_ARMCM7.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM7 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/RTE_Components.h b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/RTE_Components.h
new file mode 100644
index 0000000..9c4b3d9
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/RTE/RTE_Components.h
@@ -0,0 +1,18 @@
+
+/*
+ * This is an auto generated Run-Time-Environment Component Configuration File
+ * DO NOT MODIFY!
+ *
+ * Project: 'CMSIS_CV'
+ * Device: 'ARMCM7_DP' Pack: 'ARM::CMSIS.5.1.1-dev1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header "ARMCM7_DP.h"
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/main.c b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/main.c
new file mode 100644
index 0000000..a37e002
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/IAR-EWARM8/Cortex-M7/main.c
@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void) {
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM23_TZ_config.txt b/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM23_TZ_config.txt
new file mode 100644
index 0000000..b0fa258
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM23_TZ_config.txt
@@ -0,0 +1,159 @@
+# Parameters:
+# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
+cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
+fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
+fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
+fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
+fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
+fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
+fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
+fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
+fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
+fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:48:c5" # (string, init-time) default = '00:02:f7:ef:48:c5' : Host/model MAC address
+fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
+fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
+fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
+fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
+fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
+fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
+fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
+fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
+fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
+fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
+#----------------------------------------------------------------------------------------------
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM33_DSP_FP_TZ_config.txt b/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM33_DSP_FP_TZ_config.txt
new file mode 100644
index 0000000..dd1bf62
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/ARMCM33_DSP_FP_TZ_config.txt
@@ -0,0 +1,177 @@
+# Parameters:
+# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
+cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
+cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
+cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
+cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
+cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
+cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
+cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
+cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
+cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
+cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
+idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
+cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
+cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
+cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
+cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
+cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
+fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
+fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
+fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
+fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
+fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
+fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
+fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
+fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
+fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
+fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
+fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
+fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
+fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
+fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
+fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
+fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
+fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
+fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
+fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
+fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
+fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
+fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
+fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
+fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
+fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
+fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
+fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
+fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
+fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
+fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
+fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
+#----------------------------------------------------------------------------------------------
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/Abstract.txt b/CMSIS/CoreValidation/Examples/MDK-FVP/Abstract.txt
new file mode 100644
index 0000000..07eb452
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/Abstract.txt
@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvoptx b/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvoptx
new file mode 100644
index 0000000..5f40ae7
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvoptx
@@ -0,0 +1,3567 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj; *.o</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Cortex-M0 (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <bEvRecOn>1</bEvRecOn>
+ <nTsel>4</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\DbgFM.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DbgFM</Key>
+ <Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMRTXEVENTFLAGS</Key>
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1431,137,-1244,412,0)(1008=-1446,121,-1070,357,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint>
+ <Bp>
+ <Number>0</Number>
+ <Type>0</Type>
+ <LineNumber>144</LineNumber>
+ <EnabledFlag>1</EnabledFlag>
+ <Address>222</Address>
+ <ByteObject>0</ByteObject>
+ <HtxType>0</HtxType>
+ <ManyObjects>0</ManyObjects>
+ <SizeOfObject>0</SizeOfObject>
+ <BreakByAccess>0</BreakByAccess>
+ <BreakIfRCount>1</BreakIfRCount>
+ <Filename>RTE\Device\ARMCM0\startup_ARMCM0.s</Filename>
+ <ExecCommand></ExecCommand>
+ <Expression>\\CMSIS_CV\RTE/Device/ARMCM0/startup_ARMCM0.s\144</Expression>
+ </Bp>
+ <Bp>
+ <Number>1</Number>
+ <Type>0</Type>
+ <LineNumber>75</LineNumber>
+ <EnabledFlag>1</EnabledFlag>
+ <Address>11940</Address>
+ <ByteObject>0</ByteObject>
+ <HtxType>0</HtxType>
+ <ManyObjects>0</ManyObjects>
+ <SizeOfObject>0</SizeOfObject>
+ <BreakByAccess>0</BreakByAccess>
+ <BreakIfRCount>1</BreakIfRCount>
+ <Filename>C:\tools\Keil_v5\ARM\PACK\ARM\CMSIS-CORE_Validation\1.0.0-dev1\Source\CV_Framework.c</Filename>
+ <ExecCommand></ExecCommand>
+ <Expression>\\CMSIS_CV\CV_Framework.c\75</Expression>
+ </Bp>
+ <Bp>
+ <Number>2</Number>
+ <Type>0</Type>
+ <LineNumber>330</LineNumber>
+ <EnabledFlag>1</EnabledFlag>
+ <Address>10578</Address>
+ <ByteObject>0</ByteObject>
+ <HtxType>0</HtxType>
+ <ManyObjects>0</ManyObjects>
+ <SizeOfObject>0</SizeOfObject>
+ <BreakByAccess>0</BreakByAccess>
+ <BreakIfRCount>1</BreakIfRCount>
+ <Filename>C:\tools\Keil_v5\ARM\PACK\ARM\CMSIS-CORE_Validation\1.0.0-dev1\Source\CV_Report.c</Filename>
+ <ExecCommand></ExecCommand>
+ <Expression>\\CMSIS_CV\CV_Report.c\330</Expression>
+ </Bp>
+ </Breakpoint>
+ <WatchWindow1>
+ <Ww>
+ <count>0</count>
+ <WinNumber>1</WinNumber>
+ <ItemText>test_report</ItemText>
+ </Ww>
+ </WatchWindow1>
+ <ScvdPack>
+ <Filename>C:\tools\Keil_v5\ARM\PACK\Keil\ARM_Compiler\1.3.1\EventRecorder.scvd</Filename>
+ <Type>Keil.ARM_Compiler.1.3.1</Type>
+ <SubType>1</SubType>
+ </ScvdPack>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
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+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>1</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable>C:\tools\lint\lint-nt.exe</LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <bAutoGenD>0</bAutoGenD>
+ <LntExFlags>59</LntExFlags>
+ <pMisraName>.\Lint\MISRA_C_2012_Config.lnt</pMisraName>
+ <pszMrule>MISRA_C_2012_Config</pszMrule>
+ <pSingCmds></pSingCmds>
+ <pMultCmds></pMultCmds>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>Cortex-M3 (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
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+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
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+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <bEvRecOn>1</bEvRecOn>
+ <nTsel>4</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\DbgFM.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DbgFM</Key>
+ <Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMRTXEVENTFLAGS</Key>
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
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+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint>
+ <Bp>
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+ <Filename>C:\tools\Keil_v5\ARM\PACK\ARM\CMSIS-CORE_Validation\1.0.0-dev1\Source\CV_Framework.c</Filename>
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+ <Filename>C:\tools\Keil_v5\ARM\PACK\ARM\CMSIS-CORE_Validation\1.0.0-dev1\Source\CV_Report.c</Filename>
+ <ExecCommand></ExecCommand>
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+ </Bp>
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+ <BreakByAccess>0</BreakByAccess>
+ <BreakIfRCount>0</BreakIfRCount>
+ <Filename>RTE\Device\ARMCM0\startup_ARMCM0.s</Filename>
+ <ExecCommand></ExecCommand>
+ <Expression></Expression>
+ </Bp>
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+ <pszMrule>MISRA_C_2012_Config</pszMrule>
+ <pSingCmds></pSingCmds>
+ <pMultCmds></pMultCmds>
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+ </Target>
+
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+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvprojx b/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvprojx
new file mode 100644
index 0000000..ca5083f
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/CMSIS_CV.uvprojx
@@ -0,0 +1,5972 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
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+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
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+ <Vendor>ARM</Vendor>
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+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-Wno-covered-switch-default</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M4f (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-Wno-covered-switch-default</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M7 (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM7_DP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M7"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>3</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-Wno-covered-switch-default</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M23 (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM23_TZ</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM23_TZ$Device\ARM\SVD\ARMCM23.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName></SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll></SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMV8M.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4097</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2V8M.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M23"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>1</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>4</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x200000</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20200000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-Wno-covered-switch-default</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M33 (AC6, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM33_DSP_FP_TZ</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName></SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll></SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMV8M.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2V8M.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M33"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>1</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>4</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x200000</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20200000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-Wno-covered-switch-default</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M0 (AC5, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+ <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> </SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>1</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M3 (AC5, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+ <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M4f (AC5, FVP)</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+ <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>3</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>3</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M0 (GCC, FVP)</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> </SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M0"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>1</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>1</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>1</Optim>
+ <wLevel>3</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>1</interw>
+ <VariousControls>
+ <MiscControls>-Wall -Wstrict-prototypes -Wshadow -pedantic</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>1</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile>.\RTE\Device\ARMCM0\gcc_arm.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M3 (GCC, FVP)</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>1</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>1</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>3</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>1</interw>
+ <VariousControls>
+ <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow -pedantic</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>1</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile>.\RTE\Device\ARMCM3\gcc_arm.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M4f (GCC, FVP)</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
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+ </CommonProperty>
+ <GroupArm>
+ <Carm>
+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
+ <reentr>2</reentr>
+ <interw>2</interw>
+ <bigend>2</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </GroupArm>
+ </GroupOption>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ <GroupOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <GroupArm>
+ <Carm>
+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
+ <reentr>2</reentr>
+ <interw>2</interw>
+ <bigend>2</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </GroupArm>
+ </GroupOption>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M23 (GCC, FVP)</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM23_TZ</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM23_TZ$Device\ARM\SVD\ARMCM23.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName></SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll></SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMV8M.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2V8M.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M23"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x20200000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>1</Type>
+ <StartAddress>0x200000</StartAddress>
+ <Size>0x200000</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>1</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>1</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>1</Optim>
+ <wLevel>3</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>1</interw>
+ <VariousControls>
+ <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow -Wedantic</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>1</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile>.\RTE\Device\ARMCM0\gcc_arm.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>Cortex-M33 (GCC, FVP)</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM33_DSP_FP_TZ</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.1.1-dev1</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>CMSIS_CV</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName></SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll></SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMV8M.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2V8M.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M33"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x20200000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>1</Type>
+ <StartAddress>0x200000</StartAddress>
+ <Size>0x200000</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>1</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>1</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>1</Optim>
+ <wLevel>3</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mfloat-abi=hard -mfpu=fpv5-sp-d16 -Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>1</interw>
+ <VariousControls>
+ <MiscControls>-mfloat-abi=hard -mfpu=fpv5-sp-d16 -Wall -Wextra -Wstrict-prototypes -Wshadow -pedantic</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>1</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-mfloat-abi=hard -mfpu=fpv5-sp-d16</Misc>
+ <ScatterFile>.\RTE\Device\ARMCM0\gcc_arm.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>main</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS CORE Validation</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Compiler</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0" condition="CMSIS CORE Validation Framework">
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+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0" condition="CMSIS CORE Validation Framework">
+ <package name="CMSIS-CORE_Validation" schemaVersion="1.3" supportContact="http://silver.arm.com/support" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
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+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M0 (GCC, FVP)"/>
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+ <targetInfo name="Cortex-M23 (GCC, FVP)"/>
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+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0" condition="CMSIS CORE">
+ <package name="CMSIS-CORE_Validation" schemaVersion="1.3" supportContact="http://silver.arm.com/support" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
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+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M0 (GCC, FVP)"/>
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+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
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+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="CMSIS CORE Validation" Cgroup="MPUFunc" Cvendor="ARM" Cversion="1.0.0" condition="MPU Tests">
+ <package name="CMSIS-CORE_Validation" schemaVersion="1.3" supportContact="http://silver.arm.com/support" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M23 (GCC, FVP)"/>
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+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
+ <targetInfo name="Cortex-M33 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M33 (GCC, FVP)"/>
+ <targetInfo name="Cortex-M4f (AC5, FVP)"/>
+ <targetInfo name="Cortex-M4f (AC6, FVP)"/>
+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M0 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
+ <targetInfo name="Cortex-M0 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M23 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM23 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M23 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (AC5, FVP)"/>
+ <targetInfo name="Cortex-M3 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
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+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M33 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (AC5, FVP)"/>
+ <targetInfo name="Cortex-M4f (AC6, FVP)"/>
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+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
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+ <targetInfos>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.1.0" condition="Cortex-M Device">
+ <package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </component>
+ <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0" condition="ARMCC Cortex-M with EVR">
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+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files>
+ <file attr="config" category="header" condition="ARMv6_7_8-M Device" name="Source\Config\CV_Config.h" version="1.0.0">
+ <instance index="0">RTE\CMSIS_CORE_Validation\CV_Config.h</instance>
+ <component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0" condition="CMSIS CORE"/>
+ <package name="CMSIS-CORE_Validation" schemaVersion="1.3" supportContact="http://silver.arm.com/support" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
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+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.0.0">
+ <instance index="0">RTE\Compiler\EventRecorderConf.h</instance>
+ <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.1.0" condition="Cortex-M Device"/>
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+ </file>
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+ <targetInfos>
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+ <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM0\startup_ARMCM0.c</instance>
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+ <targetInfos>
+ <targetInfo name="Cortex-M0 (GCC, FVP)"/>
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+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
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+ <targetInfos>
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+ </file>
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+ <instance index="0">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC"/>
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+ <targetInfos>
+ <targetInfo name="Cortex-M0 (AC5, FVP)"/>
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+ </file>
+ <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM23\Source\GCC\gcc_arm.ld" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM23_TZ\gcc_arm.ld</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC"/>
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+ <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM23\Include\Template\partition_ARMCM23.h" version="0.0.0">
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+ <targetInfos>
+ <targetInfo name="Cortex-M33 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M33 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM33\Source\GCC\startup_ARMCM33.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M33 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="0.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M33 (AC6, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="0.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M33 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M33 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (AC5, FVP)"/>
+ <targetInfo name="Cortex-M3 (AC6, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M3 (AC5, FVP)"/>
+ <targetInfo name="Cortex-M3 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M3 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM4_FP\gcc_arm.ld</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (AC5, FVP)"/>
+ <targetInfo name="Cortex-M4f (AC6, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M4f (AC5, FVP)"/>
+ <targetInfo name="Cortex-M4f (AC6, FVP)"/>
+ <targetInfo name="Cortex-M4f (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\gcc_arm.ld" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM7_DP\gcc_arm.ld</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM7_DP\startup_ARMCM7.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM7_DP\startup_ARMCM7.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM7_DP\system_ARMCM7.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+ <targetInfos>
+ <targetInfo name="Cortex-M7 (AC6, FVP)"/>
+ <targetInfo name="Cortex-M7 (GCC, FVP)"/>
+ </targetInfos>
+ </file>
+ </files>
+ </RTE>
+
+</Project>
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/EventRecorderStub.scvd b/CMSIS/CoreValidation/Examples/MDK-FVP/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
+ <events>
+ </events>
+
+</component_viewer>
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/Lint/MISRA_C_2012_Config.lnt b/CMSIS/CoreValidation/Examples/MDK-FVP/Lint/MISRA_C_2012_Config.lnt
new file mode 100644
index 0000000..f7b8868
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/Lint/MISRA_C_2012_Config.lnt
@@ -0,0 +1,1495 @@
+/*----------------------------------------------------------------------------
+ MISRA_C_2012.lnt
+ MISRA C 2012 rule configuration file for PC-lint
+ *----------------------------------------------------------------------------*/
+
+// include MISRA C 2012 PC-lint file
+au-misra3.lnt
+
++rw(restrict)
+-rw_asgn(__restrict,restrict)
+-rw_asgn(__restrict__,restrict)
+-rw_asgn(__RESTRICT,restrict)
+
+-esym(534,__disable_irq)
+-esym(534,__disable_fiq)
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Checker for Misra C 2012 rules
+
+// <h> Directive 1
+/**** Dir 1.1 (Req) ************/
+// <n> Directive 1.1 (required): Any implementation-defined behaviour on which the output of the program depends shall be documented and understood
+// <i> *** NOT CHECKED *** not statically checkable
+// </h>
+
+// <h> Directive 2
+/**** Dir 2.1 (Req) ************/
+// <!c> Directive 2.1 (required): All source files shall compile without any compilation errors
+ //-e950 /* flag non-standard word or construct */
+ //-elib(950)
+// </c>
+// </h>
+
+// <h> Directive 3
+/**** Dir 3.1 (Req) ************/
+// <n> Directive 3.1 (required): All code shall be traceable to documented requirements
+// <i> *** NOT CHECKED *** not statically checkable
+// </h>
+
+// <h> Directive 4 Code design
+/**** Dir 4.1 (Req) ************/
+// <n> Directive 4.1 (required): Run-time failures shall be minimized
+// <i> *** NOT CHECKED *** not statically checkable
+
+/**** Dir 4.2 (Adv) ************/
+// <n> Directive 4.2 (advisory): (required): All usage of assembly language should be documented
+// <i> *** NOT CHECKED *** not statically checkable
+
+/**** Dir 4.3 (Req) ************/
+// <!c> Directive 4.3 (required): Assembly language shall be encapsulated and isolated
+ //-esym(586, asm)
+// </c>
+
+/**** Dir 4.4 (Adv) ************/
+// <!c> Directive 4.4 (advisory): Sections of code should not be "commented out"
+ //-e602 /* comment within comment */
+ //-elib(602)
+// </c>
+
+/**** Dir 4.5 (Adv) ************/
+// <!c> Directive 4.5 (advisory): Identifiers in the same name space with overlapping visibility should be typographically unambiguous
+ //-e9046 /* typographical ambiguity */
+ //-elib(9046)
+// </c>
+
+/**** Dir 4.6 (Adv) ************/
+// <!c> Directive 4.6 (advisory): typedefs that indicate size and signedness should be used in place of the basic numerical types
+ //-e970 /* flag modifiers used outside of typedefs */
+ //-elib(970)
+// </c>
+
+/**** Dir 4.7 (Req) ************/
+// <!c> Directive 4.7 (required): If a function returns error information, then that error information shall be tested
+ //-e534 /* ignoring return value of function */
+ //-elib(534)
+// </c>
+
+/**** Dir 4.8 (Adv) ************/
+// <!c> Directive 4.8 (advisory): If a pointer to a structure or union is never dereferenced within a translation unit, then the implementation of the object should be hidden
+ //-e9045 /* non-hidden definition of type */
+ //-elib(9045)
+// </c>
+
+/**** Dir 4.9 (Adv) ************/
+// <!c> Directive 4.9 (advisory): A function should be used in preference to a function-like macro where they are interchangeable
+ //-e9026 /* function-like macro defined */
+ //-elib(9026)
+// </c>
+
+/**** Dir 4.10 (Req) ************/
+// <!c> Directive 4.10 (required): Precautions shall be taken in order to prevent the contents of a header file being included more than once
+ //-e451 /* Header repeatedly included without guard */
+ //-elib(451)
+// </c>
+
+/**** Dir 4.11 (Req) ************/
+// <n> Directive 4.11 (required): The validity of values passed to library functions shall be checked
+// <i> The arguments to over 100 calls to standard library functions are monitored;
+// <i> users can specify additional constraints for other functions
+
+/**** Dir 4.12 (Req) ************/
+// <!c> Directive 4.12 (required): Dynamic memory allocation shall not be used
+ //-esym(586, calloc)
+ //-esym(586, malloc)
+ //-esym(586, realloc)
+ //-esym(586, free)
+// </c>
+
+/**** Dir 4.13 (Adv) ************/
+// <!c> Directive 4.13 (advisory): Functions which are designed to provide operations on a resource should be called in an appropriate sequence
+ //-e480
+ //-elib(480)
+ //-e481
+ //-elib(481)
+// </c>
+// </h>
+
+// <h> Rules 1.x: A standard C environment
+/**** Rule 1.1 (Req) ************/
+// <!c> Rule 1.1 (required): The program shall contain no violations of the standard C syntax and constraints, and shall not exceed the implementation's translation limits
+ //-e950 /* flag non-standard word or construct */
+ //-elib(950)
+// </c>
+
+/**** Rule 1.2 (Adv) ************/
+// <!c> Rule 1.2 (advisory): Language extensions should not be used
+ //-e950 /* flag non-ANSI word or construct */
+ //-elib(950)
+// </c>
+
+/**** Rule 1.3 (Req) ************/
+// <!c> Rule 1.3 (required): There shall be no occurrence of undefined or critical unspecified behaviour
+ //-e406 /* unclosed comment */
+ //-elib(406)
+ //-e27 /* illegal character */
+ //-elib(27)
+ //-e2 /* unclosed quote */
+ //-elib(2)
+ //-e31 /* symbol redefinition */
+ //-elib(31)
+ //-e40 /* undeclared identifier */
+ //-elib(40)
+ //-e401 /* symbol not previously declared static */
+ //-elib(401)
+ //-e31 /* symbol redefinition */
+ //-elib(31)
+ //-e604 /* returning address of auto variable */
+ //-elib(604)
+ //-e934 /* taking address of near auto variable */
+ //-elib(934)
+ //-e606 /* non-ANSI escape sequence */
+ //-elib(606)
+ //-e9020 /* header name with non-standard character */
+ //-elib(9020)
+ //-e86 /* structure has no data elements */
+ //-elib(86)
+ //-e64 /* type mismatch */
+ //-elib(64)
+ //-e67 /* cannot cast between types */
+ //-elib(67)
+ //-e144 /* non-existent return value */
+ //-elib(144)
+ //-e564 /* variable depends on order of evaluation */
+ //-elib(564)
+ //-e54 /* division by 0 */
+ //-elib(54)
+ //-e414 /* possible division by 0 */
+ //-elib(414)
+ //-e795 /* conceivable division by 0 */
+ //-elib(795)
+ //-e413 /* likely use of null pointer */
+ //-elib(413)
+ //-e415 /* out-of-bounds pointer */
+ //-elib(415)
+ //-e416 /* out-of-bounds pointer */
+ //-elib(416)
+ //-e428 /* negative subscript */
+ //-elib(428)
+ //-e740 /* unusual pointer cast */
+ //-elib(740)
+ //-e71 /* cannot cast */
+ //-elib(71)
+ //-e504 /* unusual shift */
+ //-elib(504)
+ //-e629 /* static class for function */
+ //-elib(629)
+ //-e158 /* assignment increases capability */
+ //-elib(158)
+ //-e158 /* assignment increases capability */
+ //-elib(158)
+ //-estring(10,"a numeric constant") /* expecting a numeric constant */
+ //-e136 /* illegal macro name */
+ //-elib(136)
+ //-e558 /* too few arguments */
+ //-elib(558)
+ //-e719 /* too many arguments */
+ //-elib(719)
+ //-e557 /* unrecognized format */
+ //-elib(557)
+ //-e437 /* passing struct to ellipsis */
+ //-elib(437)
+ //-e449 /* previously deallocated pointer */
+ //-elib(449)
+ //-esym(424,free) /* inappropriate deallocation */
+ //-e419 /* data overrun */
+ //-elib(419)
+ //-e564 /* variable depends on order of evaluation */
+ //-elib(564)
+ //-e931 /* both sides of an expression have side-effects */
+ //-elib(931)
+ //-e564 /* variable depends on order of evaluation */
+ //-elib(564)
+ //-e9023 /* multiple '#/##' operators in macro definition */
+ //-elib(9023)
+// </c>
+// </h>
+
+// <h> Rules 2.x: Unused code
+/**** Rule 2.1 (Req) ************/
+// <!c> Rule 2.1 (required): A project shall not contain unreachable code
+ //-e506 /* constant value boolean */
+ //-elib(506)
+ //-e527 /* unreachable */
+ //-elib(527)
+ //-e681 /* loop not entered */
+ //-elib(681)
+ //-e827 /* loop not reachable */
+ //-elib(827)
+// </c>
+
+/**** Rule 2.2 (Req) ************/
+// <!c> Rule 2.2 (required): There shall be no dead code
+ //-e438 /* value not used */
+ //-elib(438)
+ //-e505 /* redundant argument to comma */
+ //-elib(505)
+ //-e520 /* highest operator has no side effects */
+ //-elib(520)
+ //-e521 /* highest operator has no side effects */
+ //-elib(521)
+ //-e522 /* highest operator has no side effects */
+ //-elib(522)
+// </c>
+
+/**** Rule 2.3 (Adv) ************/
+// <!c> Rule 2.3 (advisory): A project should not contain unused type declarations
+ //-e751 /* local typedef not referenced */
+ //-elib(751)
+ //-e756 /* global not referenced */
+ //-elib(756)
+// </c>
+
+/**** Rule 2.4 (Adv) ************/
+// <!c> Rule 2.4 (advisory): A project should not contain unused tag declarations
+ //-e753 /* local tag not referenced */
+ //-elib(753)
+ //-e9058
+ //-elibsym(9058)
+// </c>
+
+/**** Rule 2.5 (Adv) ************/
+// <!c> Rule 2.5 (advisory): A project should not contain unused macro declarations
+ //-e750 /* local macro not referenced */
+ //-elib(750)
+ //-e755 /* global macro not referenced */
+ //-elib(755)
+// </c>
+
+/**** Rule 2.6 (Adv) ************/
+// <!c> Rule 2.6 (advisory): A function should not contain unused label declarations
+ //-e563 /* label not referenced */
+ //-elib(563)
+// </c>
+
+/**** Rule 2.7 (Adv) ************/
+// <!c> Rule 2.7 (advisory): There should be no unused parameters in functions
+ //-e715 /* not referenced */
+ //-elib(715)
+// </c>
+// </h>
+
+// <h> Rules 3.x: Comments
+/**** Rule 3.1 (Req) ************/
+// <!c> Rule 3.1 (required): The character sequences /* and // shall not be used within a comment
+ //-e602 /* comment within comment */
+ //-elib(602)
+ //-e9059
+ //-elib(9059)
+ //-e9066
+ //-elib(9066)
+// </c>
+
+/**** Rule 3.2 (Req) ************/
+// <!c> Rule 3.2 (required): Line-splicing shall not be used in // comments
+ //-e427 /* C++ comment ends in \\ */
+ //-elib(427)
+// </c>
+// </h>
+
+// <h> Rules 4.x: Character sets and lexical conventions
+/**** Rule 4.1 (Req) ************/
+// <!c> Rule 4.1 (required): Octal and hexadecimal escape sequences shall be terminated
+ //-e9039 /* prohibited escape sequence */
+ //-elib(9039)
+// </c>
+
+/**** Rule 4.2 (Adv) ************/
+// <!c> Rule 4.2 (advisory): Trigraphs should not be used
+ //-e584 /* activate trigraph detected message */
+ //-elib(584)
+ //-e739 /* activate trigraph in string message */
+ //-elib(739)
+ //-e9060 /* trigraph in comment */
+ //-elib(9060)
+// </c>
+// </h>
+
+// <h> Rules 5.x: Identifiers
+/**** Rule 5.1 (Req) ************/
+// <!c> Rule 5.1 (required): External identifiers shall be distinct
+ //-e621 /* Identifier clash - length set by -idlen */
+ //-elib(621)
+// </c>
+
+/**** Rule 5.2 (Req) ************/
+// <!c> Rule 5.2 (required): Identifiers declared in the same scope and name space shall be distinct
+ //-e621 /* Identifier clash - length set by -idlen */
+ //-elib(621)
+// </c>
+
+/**** Rule 5.3 (Req) ************/
+// <!c> Rule 5.3 (required): An identifier declared in an inner scope shall not hide an identifier declared in an outer scope
+ //-e578 /* enable reports of name hiding */
+ //-elib(578)
+// </c>
+
+/**** Rule 5.4 (Req) ************/
+// <!c> Rule 5.4 (required): Macro identifiers shall be distinct
+ //-e621 /* Identifier clash - length set by -idlen */
+ //-elib(621)
+// </c>
+
+/**** Rule 5.5 (Req) ************/
+// <!c> Rule 5.5 (required): Identifiers shall be distinct from macro names
+ //-e123 /* macro defined with arguments */
+ //-elib(123)
+ //-e621 /* Identifier clash - length set by -idlen */
+ //-elib(621)
+ //-e9061 /* non-distinct identifier */
+ //-elib(9061)
+// </c>
+
+/**** Rule 5.6 (Req) ************/
+// <!c> Rule 5.6 (required): A typedef name shall be a unique identifier
+ //-e578 /* enable reports of name hiding */
+ //-elib(578)
+ //-e623 /* redefining the storage class of symbol */
+ //-elib(623)
+ //-esym(9062,typedef) /* non-unique typedef */
+ //-elib(9062)
+// </c>
+
+/**** Rule 5.7 (Req) ************/
+// <!c> Rule 5.7 (required): A tag name shall be a unique identifier
+ //-e407 /* Inconsistent use of tag */
+ //-elib(407)
+ //-e578 /* Declaration of Symbol hides Symbol */
+ //-elib(578)
+ //-e14 /* Symbol previously defined */
+ //-elib(14)
+ //-e15 /* Symbol redeclared */
+ //-elib(15)
+ //-e631 /* Tag defined differently */
+ //-elib(631)
+ //-e9062 /* non-unique tag */
+ //-elib(9062)
+// </c>
+
+/**** Rule 5.8 (Req) ************/
+// <!c> Rule 5.8 (required): Identifiers that define objects or functions with external linkage shall be unique
+ //-e401 /* Symbol not previously declared static */
+ //-elib(401)
+ //-e578 /* Declaration of Symbol hides Symbol */
+ //-elib(578)
+ //-e580 /* enable reports of name hiding */
+ //-elib(580)
+// </c>
+
+/**** Rule 5.9 (Adv) ************/
+// <!c> Rule 5.9 (advisory): Identifiers that define objects \or functions with internal linkage should be unique
+ //-e578 /* enable reports of name hiding */
+ //-elib(578)
+ //-e580 /* enable reports of name hiding */
+ //-elib(580)
+// </c>
+// </h>
+
+// <h> Rules 6.x: Types
+/**** Rule 6.1 (Req) ************/
+// <!c> Rule 6.1 (required): Bit-fields shall only be declared with an appropriate type
+ //-e46 /* field type should be int */
+ //-elib(46)
+ //-e806 /* small bit field is signed rather than unsigned */
+ //-elib(806)
+// </c>
+
+/**** Rule 6.2 (Req) ************/
+// <!c> Rule 6.2 (required): Single-bit named bit fields shall not be of a signed type
+ //-e9088 /* named signed single-bit bit-field */
+ //-elib(9088)
+// </c>
+// </h>
+
+// <h> Rules 7.x: Literals and constants
+/**** Rule 7.1 (Req) ************/
+// <!c> Rule 7.1 (required): Octal constants shall not be used
+ //-e9001 /* Octal constant used */
+ //-elib(9001)
+// </c>
+
+/**** Rule 7.2 (Req) ************/
+// <!c> Rule 7.2 (required): A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type
+ //-e9048 /* unsigned literal without 'U' suffix */
+ //-elib(9048)
+// </c>
+
+/**** Rule 7.3 (Req) ************/
+// <!c> Rule 7.3 (required): The lowercase character "l" shall not be used in a literal suffix
+ //-e620 /* suspicious constant */
+ //-elib(620)
+ //-e9057 /* "l" after "u" in literal suffix */
+ //-elib(9057)
+// </c>
+
+/**** Rule 7.4 (Req) ************/
+// <!c> Rule 7.4 (required): A string literal shall not be assigned to an object unless the object's type is "pointer to const-qualified char"
+ //-e489 /* attempting to modify a string literal */
+ //-elib(489)
+ //-e1776 /* string literal not const safe */
+ //-elib(1776)
+ //-e1778 /* assignment of string literal not const safe */
+ //-elib(1778)
+// </c>
+// </h>
+
+// <h> Rules 8.x: Declarations and definitions
+/**** Rule 8.1 (Req) ************/
+// <!c> Rule 8.1 (required): Types shall be explicitly specified
+ //-e601 /* no explicit type */
+ //-elib(601)
+ //-e745 /* function has no explicit type */
+ //-elib(745)
+ //-e808 /* no explicit type */
+ //-elib(808)
+ //-e832 /* parameter has no explicit type */
+ //-elib(832)
+ //-e939 /* return type defaults to int */
+ //-elib(939)
+// </c>
+
+/**** Rule 8.2 (Req) ************/
+// <!c> Rule 8.2 (required): Function types shall be in prototype form with named parameters
+ //-e937 /* old-style function declaration */
+ //-elib(937)
+ //-e745 /* function has no explicit type */
+ //-elib(745)
+ //-e939 /* return type defaults to int */
+ //-elib(939)
+ //-e18 /* symbol redeclared */
+ //-elib(18)
+ //-e936 /* old-style function definition */
+ //-elib(936)
+ //-e955 /* param name missing from prototype */
+ //-elib(955)
+// </c>
+
+/**** Rule 8.3 (Req) ************/
+// <!c> Rule 8.3 (required): All declarations of an object or function shall use the same names and type qualifiers
+ //-e18 /* symbol redeclared */
+ //-elib(18)
+ //-e516 /* argument type conflict */
+ //-elib(516)
+ //-e532 /* return mode of symbol inconsistent */
+ //-elib(532)
+ //-e9072 /* parameter list differs */
+ //-elib(9072)
+// </c>
+
+/**** Rule 8.4 (Req) ************/
+// <!c> Rule 8.4 (required): A compatible declaration shall be visible when an object or function with external linkage is defined
+ //-e15 /* symbol redeclared */
+ //-elib(15)
+ //-e64 /* flag type mismatch */
+ //-elib(64)
+ //-e516 /* argument type mismatch */
+ //-elib(516)
+ //-e9075 /* extern defined without prior declaration */
+ //-elib(9075)
+// </c>
+
+/**** Rule 8.5 (Req) ************/
+// <!c> Rule 8.5 (required): An external object or function shall be declared once in one and only one file
+ //-e9004 /* object/function previously declared */
+ //-elib(9004)
+// </c>
+
+/**** Rule 8.6 (Req) ************/
+// <!c> Rule 8.6 (required): An identifier with external linkage shall have exactly one external definition
+ //-e14 /* Symbol previously defined */
+ //-elib(14)
+// </c>
+
+/**** Rule 8.7 (Adv) ************/
+// <!c> Rule 8.7 (advisory): Functions and objects should not be defined with external linkage if they are referenced in only one translation unit
+ //-e765 /* could be made static */
+ //-elib(765)
+// </c>
+
+/**** Rule 8.8 (Req) ************/
+// <!c> Rule 8.8 (required): The static storage class specifier shall be used in all declarations of objects and functions that have internal linkage
+ //-e839 /* storage class assumed static */
+ //-elib(839)
+// </c>
+
+/**** Rule 8.9 (Adv) ************/
+// <!c> Rule 8.9 (advisory): An object should be defined at block scope if its identifier only appears in a single function
+ //-e9003 /* could define variable at block scope */
+ //-elib(9003)
+// </c>
+
+/**** Rule 8.10 (Req) ************/
+// <!c> Rule 8.10 (required): An inline function shall be declared with the static storage class
+ //-e695 /* inline function without storage-class specifier */
+ //-elib(695)
+ //-esym(9056,extern) /* inline function defined with extern */
+// </c>
+
+/**** Rule 8.11 (Adv) ************/
+// <!c> Rule 8.11 (advisory): When an array with external linkage is declared, its size should be explicitly specified
+ //-e9067 /* array has no dimension or initializer */
+ //-elib(9067)
+// </c>
+
+/**** Rule 8.12 (Req) ************/
+// <!c> Rule 8.12 (required): Within an enumerator list, the value of an implicitly-specified enumeration constant shall be unique
+ //-e488 /* duplicate enumerator values */
+ //-elib(488)
+// </c>
+
+/**** Rule 8.13 (Adv) ************/
+// <!c> Rule 8.13 (advisory): A pointer should point to a const-qualified type whenever possible
+ //-e818 /* pointer could be declared pointing to const */
+ //-elib(818)
+ //-e844 /* pointer could be declared pointing to const */
+ //-elib(844)
+ //-e954 /* pointer could be declared pointing to const */
+ //-elib(954)
+// </c>
+
+/**** Rule 8.14 (Req) ************/
+// <!c> Rule 8.14 (required): The restrict type qualifier shall not be used
+ //-esym(586, restrict)
+// </c>
+// </h>
+
+// <h> Rules 9.x: Initialization
+/**** Rule 9.1 (Mand) ************/
+// <!c> Rule 9.1 (mandatory): The value of an object with automatic storage duration shall not be read before it has been set
+ //-e644 /* Symbol may not have been initialized */
+ //-elib(644)
+ //-e771 /* Symbol conceivably not initialized */
+ //-elib(771)
+ //-e530 /* Symbol not initialized */
+ //-elib(530)
+// </c>
+
+/**** Rule 9.2 (Req) ************/
+// <!c> Rule 9.2 (required): The initializer for an aggregate or union shall be enclosed in braces
+ //-e9069 /* omitted braces within an initializer */
+ //-elib(9069)
+// </c>
+
+/**** Rule 9.3 (Req) ************/
+// <!c> Rule 9.3 (required): Arrays shall not be partially initialized
+ //-e9068 /* too few initializers */
+ //-elib(9068)
+// </c>
+
+/**** Rule 9.4 (Req) ************/
+// <!c> Rule 9.4 (required): An element of an object shall not be initialized more than once
+ //-e485 /* duplicate initialization */
+ //-elib(485)
+// </c>
+
+/**** Rule 9.5 (Req) ************/
+// <!c> Rule 9.5 (required): Where designated initializers are used to initialize an array object the size of the array shall be specified explicitly
+ //-e9054 /* designated initializer and dimensionless array */
+ //-elib(9054)
+// </c>
+// </h>
+
+// <h> Rules 10.x: The essential type model
+/**** Rule 10.1 (Req) ************/
+// <!c> Rule 10.1 (required): Operands shall not be of an inappropriate essential type
+ //-e48 /* bad type */
+ //-elib(48)
+ //-e9027 /* unpermitted operand */
+ //-elib(9027)
+// </c>
+
+/**** Rule 10.2 (Req) ************/
+// <!c> Rule 10.2 (required): Expressions of essentially character type shall not be used inappropriately in addition and subtraction operations
+ //-e9028 /* unpermitted arithmetic */
+ //-elib(9028)
+// </c>
+
+/**** Rule 10.3 (Req) ************/
+// <!c> Rule 10.3 (required): The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category
+ //-e9034 /* expression assigned to narrower or different essential type */
+ //-elib(9034)
+// </c>
+
+/**** Rule 10.4 (Req) ************/
+// <!c>Rule 10.4 (required): Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category
+ //-e9029 /* mismatched essential type */
+ //-elib(9029)
+// </c>
+
+/**** Rule 10.5 (Adv) ************/
+// <!c> Rule 10.5 (advisory): The value of an expression should not be cast to an inappropriate essential type
+ //-e9030 /* impermissible cast */
+ //-elib(9030)
+// </c>
+
+/**** Rule 10.6 (Req) ************/
+// <!c> Rule 10.6 (required): The value of a composite expression shall not be assigned to an object with wider essential type
+ //-e9031 /* composite expression assigned to wider essential type */
+ //-elib(9031)
+// </c>
+
+/**** Rule 10.7 (Req) ************/
+// <!c> Rule 10.7 (required): If a composite expression is used as one operand of an operator in which the usual arithmetic conversions are performed then the other operand shall not have wider essential type
+ //-e9032 /* composite expression with smaller essential type than other operand*/
+ //-elib(9032)
+// </c>
+
+/**** Rule 10.8 (Req) ************/
+// <!c> Rule 10.8 (required): The value of a composite expression shall not be cast to a different essential type category or a wider essential type
+ //-e9033 /* impermissible cast of composite expression */
+ //-elib(9033)
+// </c>
+// </h>
+
+// <h> Rules 11.x: Pointer type conversions
+/**** Rule 11.1 (Req) ************/
+// <!c> Rule 11.1 (required): Conversions shall not be performed between a pointer to a function and any other type
+ //-e9074 /* conversion between a pointer to function and another type */
+ //-elib(9074)
+// </c>
+
+/**** Rule 11.2 (Req) ************/
+// <!c> Rule 11.2 (required): Conversions shall not be performed between a pointer to an incomplete type and any other type
+ //-e9076 /* conversion between a pointer to incomplete type and another type */
+ //-elib(9076)
+// </c>
+
+/**** Rule 11.3 (Req) ************/
+// <!c> Rule 11.3 (required): A cast shall not be performed between a pointer to object type and a pointer to a different object type
+ //-e9087 /* cast from pointer to pointer */
+ //-elib(9087)
+// </c>
+
+/**** Rule 11.4 (Adv) ************/
+// <!c> Rule 11.4 (advisory): A conversion should not be performed between a pointer to object and an integer type
+ //-e9078 /* cast pointer/integer */
+ //-elib(9078)
+// </c>
+
+/**** Rule 11.5 (Adv) ************/
+// <!c> Rule 11.5 (advisory): A conversion should not be performed from pointer to void into pointer to object
+ //-e9079 /* cast from pointer to pointer */
+ //-elib(9079)
+// </c>
+
+/**** Rule 11.6 (Req) ************/
+// <!c> Rule 11.6 (required): A cast shall not be performed between pointer to void and an arithmetic type
+ //-e923 /* cast pointer/non-pointer */
+ //-elib(923)
+// </c>
+
+/**** Rule 11.7 (Req) ************/
+// <!c> Rule 11.7 (required): A cast shall not be performed between pointer to object and a non-integer arithmetic type
+ //-e68 /* cast pointer/float */
+ //-elib(68)
+ //-e70 /* cast pointer/float */
+ //-elib(70)
+// </c>
+
+/**** Rule 11.8 (Req) ************/
+// <!c> Rule 11.8 (required): A cast shall not remove any const or volatile qualification from the type pointed to by a pointer
+ //-e9005 /* attempt to cast away const/volatile from pointer or reference */
+ //-elib(9005)
+// </c>
+
+/**** Rule 11.9 (Req) ************/
+// <!c> Rule 11.9 (required): The macro NULL shall be the only permitted form of integer null pointer constant
+ //-e910 /* conversion from 0 to pointer */
+ //-elib(910)
+ //-e9080 /* integer null pointer constant */
+ //-elib(9080)
+// </c>
+// </h>
+
+// <h> Rules 12.x: Expressions
+/**** Rule 12.1 (Adv) ************/
+// <!c> Rule 12.1 (advisory): The precedence of operators within expressions should be made explicit
+ //-e9050 /* dependence placed on precedence */
+ //-elib(9050)
+// </c>
+
+/**** Rule 12.2 (Req) ************/
+// <!c> Rule 12.2 (required): The right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand
+ //-e598 /* excessive left shift */
+ //-elib(598)
+ //-e9053 /* shift value exceeds size of LHS */
+ //-elib(9053)
+// </c>
+
+/**** Rule 12.3 (Adv) ************/
+// <!c> Rule 12.3 (advisory): The comma operator should not be used
+ //-e9008 /* comma operator used */
+ //-elib(9008)
+// </c>
+
+/**** Rule 12.4 (Adv) ************/
+// <!c> Rule 12.4 (advisory): Evaluation of constant expressions should not lead to unsigned integer wrap-around
+ //-e648
+ //-elib(648) /* Overflow in computing constant */
+ //-estring(648,"unsigned addition")
+ //-estring(648,"unsigned multiplication")
+ //-estring(648,"unsigned sub.")
+ //-estring(648,"unsigned shift left")
+ //-estring(648,"unsigned shift right")
+// </c>
+// </h>
+
+// <h> Rules 13.x: Side effects
+/**** Rule 13.1 (Req) ************/
+// <!c> Rule 13.1 (required): Initializer lists shall not contain persistent side effects
+ //-e446 /* side effect in initializer */
+ //-elib(446)
+// </c>
+
+/**** Rule 13.2 (Req) ************/
+// <!c> Rule 13.2 (required): The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders
+ //-e564 /* variable depends on order of evaluation */
+ //-elib(564)
+ //-e864 /* variable possibly depends on order of evaluation */
+ //-elib(864)
+ //-e931 /* both sides have side effects */
+ //-elib(931)
+// </c>
+
+/**** Rule 13.3 (Adv) ************/
+// <!c> Rule 13.3 (advisory): A full expression containing an increment (++) or decrement (--) operator should have no other potential side effects other than that caused by the increment or decrement operator
+ //-e9049 /* increment/decrement combined with other operations */
+ //-elib(9049)
+// </c>
+
+/**** Rule 13.4 (Adv) ************/
+// <!c> Rule 13.4 (advisory): The result of an assignment operator should not be used
+ //-e720 /* Boolean test of assignment */
+ //-elib(720)
+ //-e820 /* Boolean test of parenthesized assignment */
+ //-elib(820)
+ //-e9084 /* assignment used inside larger expression */
+ //-elib(9084)
+// </c>
+
+/**** Rule 13.5 (Req) ************/
+// <!c> Rule 13.5 (required): The right hand operand of a logical && or || operator shall not contain persistent side effects
+ //-e9007 /* side effects on right hand side of logical operator */
+ //-elib(9007)
+// </c>
+
+/**** Rule 13.6 (Mand) ************/
+// <!c> Rule 13.6 (mandatory): The operand of the sizeof operator shall not contain any expression which has potential side effects
+ //-e9006 /* sizeof used with expression with side effect */
+ //-elib(9006)
+ //-e9089 /* potential side-effect in argument to sizeof */
+ //-elib(9089)
+// </c>
+// </h>
+
+// <h> Rules 14.x: Control statement expressions
+/**** Rule 14.1 (Req) ************/
+// <!c> Rule 14.1 (required): A loop counter shall not have essentially floating type
+ //-e9009 /* floating point variable used as loop counter */
+ //-elib(9009)
+// </c>
+
+/**** Rule 14.2 (Req) ************/
+// <!c> Rule 14.2 (required): A for loop shall be well-formed
+ //-e850 /* index variable modified in body of for loop */
+ //-elib(850)
+// </c>
+
+/**** Rule 14.3 (Req) ************/
+// <!c> Rule 14.3 (required): Controlling expressions shall not be invariant
+ //-e685 /* relational always evaluates to true/false */
+ //-elib(685)
+ //-e774 /* boolean always evaluates to true/false */
+ //-elib(774)
+ //-e650 /* constant out of range for operator */
+ //-elib(650)
+// </c>
+
+/**** Rule 14.4 (Req) ************/
+// <!c> Rule 14.4 (required): The controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type
+ //-e9036 /* condition should have essentially Boolean type */
+ //-elib(9036)
+// </c>
+// </h>
+
+// <h> Rules 15.x: Control flow
+/**** Rule 15.1 (Adv) ************/
+// <!c> Rule 15.1 (advisory): The goto statement should not be used
+ //-e801 /* use of 'goto' is deprecated */
+ //-elib(801)
+// </c>
+
+/**** Rule 15.2 (Req) ************/
+// <!c> Rule 15.2 (required): The goto statement shall jump to a label declared later in the same function
+ //-e9064 /* goto references earlier label */
+ //-elib(9064)
+// </c>
+
+/**** Rule 15.3 (Req) ************/
+// <!c> Rule 15.3 (required): Any label referenced by a goto statement shall be declared in the same block, or in any block enclosing the goto statement
+ //-e9041 /* goto not nested in the same block as label */
+ //-elib(9041)
+// </c>
+
+/**** Rule 15.4 (Adv) ************/
+// <!c> Rule 15.4 (advisory): There should be no more than one break or goto statement used to terminate any iteration statement
+ //-e9011 /* more than one 'break' terminates loop */
+ //-elib(9011)
+// </c>
+
+/**** Rule 15.5 (Adv) ************/
+// <!c> Rule 15.5 (advisory): A function should have a single point of exit at the end
+ //-e904 /* return before function end */
+ //-elib(904)
+// </c>
+
+/**** Rule 15.6 (Req) ************/
+// <!c> Rule 15.6 (required): The body of an iteration-statement or a selection-statement shall be acompound-statement
+ //-e9012 /* sub-statement should be a compound statement */
+ //-elib(9012)
+// </c>
+
+/**** Rule 15.7 (Req) ************/
+// <!c> Rule 15.7 (required): All if ... else if constructs shall be terminated with an else statement
+ //-e9013 /* no 'else' at end of 'if ... else if' chain */
+ //-elib(9013)
+ //-e9063 /* no comment or action in else-branch */
+ //-elib(9063)
+// </c>
+// </h>
+
+// <h> Rules 16.x: Switch statements
+/**** Rule 16.1 (Req) ************/
+// <!c> Rule 16.1 (required): All switch statements shall be well-formed
+ //-e616 /* control flows into case/default */
+ //-elib(616)
+ //-e744 /* switch statement has no default */
+ //-elib(744)
+ //-e764 /* switch does not have a case */
+ //-elib(764)
+ //-e825 /* control flows into case/default without -fallthrough comment */
+ //-elib(825)
+ //-e9014 /* default missing from switch */
+ //-elib(9014)
+ //-e9042 /* departure from MISRA switch syntax */
+ //-elib(9042)
+ //-e9077 /* missing unconditional break */
+ //-elib(9077)
+ //-e9081 /* too few independent cases for switch */
+ //-elib(9081)
+ //-e9082 /* switch statement should either begin or end with default label */
+ //-elib(9082)
+ //-e9085 /* statement or comment should appear in default case */
+ //-elib(9085)
+// </c>
+
+/**** Rule 16.2 (Req) ************/
+// <!c> Rule 16.2 (required): A switch label shall only be used when the most closely-enclosing compound statement is the body of a switch statement
+ //-e44 /* Need a switch */
+ //-elib(44)
+ //-e9055 /* enclosing statement is not a switch */
+ //-elib(9055)
+// </c>
+
+/**** Rule 16.3 (Req) ************/
+// <!c> Rule 16.3 (required): An unconditional break statement shall terminate every switch-clause
+ //-e616 /* control flows into case/default */
+ //-elib(616)
+ //-e825 /* control flows into case/default without -fallthrough comment */
+ //-elib(825)
+ //-e9077 /* missing unconditional break */
+ //-elib(9077)
+ //-e9090 /* missing unconditional break */
+ //-elib(9090)
+// </c>
+
+/**** Rule 16.4 (Req) ************/
+// <!c> Rule 16.4 (required): Every switch statement shall have a default label
+ //-e744 /* switch statement has no default */
+ //-elib(744)
+ //-e9014 /* switch statement has no default */
+ //-elib(9014)
+ //-e9085 /* default case has no statement nor comment */
+ //-elib(9085)
+// </c>
+
+/**** Rule 16.5 (Req) ************/
+// <!c> Rule 16.5 (required): A default label shall appear as either the first or the last switch label of a switch statement
+ //-e9082 /* default should be first or last */
+ //-elib(9082)
+// </c>
+
+/**** Rule 16.6 (Req) ************/
+// <!c> Rule 16.6 (required): Every switch statement shall have at least two switch-clauses
+ //-e764 /* switch does not have a case */
+ //-elib(764)
+ //-e9081 /* too few cases */
+ //-elib(9081)
+// </c>
+
+/**** Rule 16.7 (Req) ************/
+// <!c> Rule 16.7 (required): A switch-expression shall not have essentially Boolean type
+ //-e483 /* boolean value in switch expression */
+ //-elib(483)
+// </c>
+// </h>
+
+// <h> Rules 17.x: Functions
+/**** Rule 17.1 (Req) ************/
+// <!c> Rule 17.1 (required): The features of <stdarg.h> shall not be used
+ //-efile(829, stdarg.h)
+ //-esym(586, va_arg)
+ //-esym(586, va_start)
+ //-esym(586, va_end)
+ //-esym(586, va_copy)
+// </c>
+
+/**** Rule 17.2 (Req) ************/
+// <!c> Rule 17.2 (required): Functions shall not call themselves, either directly or indirectly
+ //-e9070
+// </c>
+
+/**** Rule 17.3 (Mand) ************/
+// <!c> Rule 17.3 (mandatory): A function shall not be declared implicitly
+ //-e718 /* symbol undeclared, assumed to return int */
+ //-elib(718)
+// </c>
+
+/**** Rule 17.4 (Mand) ************/
+// <!c> Rule 17.4 (mandatory): All exit paths from a function with non-void return type shall have an explicit return statement with an expression
+ //-e533 /* function should return a value */
+ //-elib(533)
+// </c>
+
+/**** Rule 17.5 (Adv) ************/
+// <n> Rule 17.5 (advisory): The function argument corresponding to a parameter declared to have an array type shall have an appropriate number of elements
+// <i> *** NOT CHECKED *** MISRA has declared this rule to be "undecidable"
+
+/**** Rule 17.6 (Mand) ************/
+// <!c> Rule 17.6 (mandatory): The declaration of an array parameter shall not contain the static keyword between the [ ]
+ //-e9043 /* static between brackets of array declaration */
+ //-elib(9043)
+// </c>
+
+/**** Rule 17.7 (Req) ************/
+// <!c> Rule 17.7 (required): The value returned by a function having non-void return type shall be used
+ //-e534 /* ignoring return value of function */
+ //-elib(534)
+// </c>
+
+/**** Rule 17.8 (Adv) ************/
+// <!c> Rule 17.8 (advisory): A function parameter should not be modified
+ //-e9044 /* function parameter modified */
+ //-elib(9044)
+// </c>
+// </h>
+
+// <h> Rules 18.x: Pointers and arrays
+/**** Rule 18.1 (Req) ************/
+// <!c> Rule 18.1 (required): A pointer resulting from arithmetic on a pointer operand shall address an element of the same array as that pointer operand
+ //-e415 /* out-of-bounds pointer */
+ //-elib(415)
+ //-e416 /* out-of-bounds pointer */
+ //-elib(416)
+ //-e428 /* out-of-bounds pointer */
+ //-elib(428)
+ //-e661 /* out-of-bounds pointer */
+ //-elib(661)
+ //-e662 /* out-of-bounds pointer */
+ //-elib(662)
+ //-e676 /* out-of-bounds pointer */
+ //-elib(676)
+ //-e796 /* out-of-bounds pointer */
+ //-elib(796)
+ //-e797 /* out-of-bounds pointer */
+ //-elib(797)
+ //-e817 /* out-of-bounds pointer */
+ //-elib(817)
+// </c>
+
+/**** Rule 18.2 (Req) ************/
+// <!c> Rule 18.2 (required): Subtraction between pointers shall only be applied to pointers that address elements of the same array
+ //-e946 /* relational or subtract operator applied to pointers */
+ //-elib(946)
+ //-e947 /* relational or subtract operator applied to pointers */
+ //-elib(947)
+// </c>
+
+/**** Rule 18.3 (Req) ************/
+// <!c> Rule 18.3 (required): The relational operators >, >=, < and <= shall not be applied to objects of pointer type except where they point into the same object
+ //-e946 /* relational or subtract operator applied to pointers */
+ //-elib(946)
+ //-e947 /* relational or subtract operator applied to pointers */
+ //-elib(947)
+// </c>
+
+/**** Rule 18.4 (Adv) ************/
+// <!c> Rule 18.4 (advisory): The +, -, += and -= operators should not be applied to an expression of pointer type
+ //-e9016 /* pointer arithmetic other than array indexing used */
+ //-elib(9016)
+// </c>
+
+/**** Rule 18.5 (Adv) ************/
+// <!c> Rule 18.5 (advisory): Declarations should contain no more than two levels of pointer nesting
+ //-e9025 /* more than two pointer indirection levels used */
+ //-elib(9025)
+// </c>
+
+/**** Rule 18.6 (Req) ************/
+// <!c> Rule 18.6 (required): The address of an object with automatic storage shall not be copied to another object that persists after the first object has ceased to exist
+ //-e733 /* assigning address of auto to outer scope symbol */
+ //-elib(733)
+ //-e789 /* assigning address of auto to static */
+ //-elib(789)
+ //-e604 /* returning address of auto variable */
+ //-elib(604)
+// </c>
+
+/**** Rule 18.7 (Req) ************/
+// <!c> Rule 18.7 (required): Flexible array members shall not be declared
+ //-e9038 /* flexible array member declared */
+ //-elib(9038)
+// </c>
+
+/**** Rule 18.8 (Req) ************/
+// <!c> Rule 18.8 (required): Variable-length array types shall not be used
+ //-e9035 /* variable length array declared */
+ //-elib(9035)
+// </c>
+// </h>
+
+// <h> Rules 19.x: Overlapping storage
+/**** Rule 19.1 (Mand) ************/
+// <n> Rule 19.1 (mandatory): An object shall not be assigned or copied to an overlapping object
+// <i> *** NOT CHECKED *** MISRA has declared this rule to be "undecidable"
+
+/**** Rule 19.2 (Adv) ************/
+// <!c> Rule 19.2 (advisory): The union keyword should not be used
+ //-e9018 /* union type/object declared */
+ //-elib(9018)
+// </c>
+// </h>
+
+// <h> Rules 20.x: Preprocessing directives
+/**** Rule 20.1 (Adv) ************/
+// <!c> Rule 20.1 (advisory): #include directives should only be preceded by preprocessor directives or comments
+ //-e9019 /* declaration before #include */
+ //-elib(9019)
+// </c>
+
+/**** Rule 20.2 (Req) ************/
+// <!c> Rule 20.2 (required): The ',' or characters and the /* or // character sequences shall not occur in a header file name
+ //-e9020 /* header file name with non-standard character */
+ //-elib(9020)
+// </c>
+
+/**** Rule 20.3 (Req) ************/
+// <!c> Rule 20.3 (required): The #include directive shall be followed by either a <filename> or "filename" sequence
+ //-e12 /* Need LT or " after #include */
+ //-elib(12)
+ //-e9086 /* multiple arguments after #include */
+ //-elib(9086)
+// </c>
+
+/**** Rule 20.4 (Req) ************/
+// <!c> Rule 20.4 (required): A macro shall not be defined with the same name as a keyword
+ //-e9051 /* macro with same name as a keyword */
+ //-elib(9051)
+// </c>
+
+/**** Rule 20.5 (Adv) ************/
+// <!c> Rule 20.5 (advisory): #undef should not be used
+ //-e9021 /* use of '#undef' is discouraged */
+ //-elib(9021)
+// </c>
+
+/**** Rule 20.6 (Req) ************/
+// <!c> Rule 20.6 (required): Tokens that look like a preprocessing directive shall not occur within a macro argument
+ //-e436 /* preprocessor directive in invocation of macro */
+ //-elib(436)
+// </c>
+
+/**** Rule 20.7 (Req) ************/
+// <!c> Rule 20.7 (required): Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses
+ //-e665 /* expression passed to unparenthesized macro */
+ //-elib(665)
+// </c>
+
+/**** Rule 20.8 (Req) ************/
+// <!c> Rule 20.8 (required): The controlling expression of a #if or #elif preprocessing directive shall evaluate to 0 or 1
+ //-e9037 /* conditional of #if/#elif does not evaluate to 0 or 1 */
+ //-elib(9037)
+// </c>
+
+/**** Rule 20.9 (Req) ************/
+// <!c> Rule 20.9 (required): All identifiers used in the controlling expression of #if or #elif preprocessing directives shall be #define'd before evaluation
+ //-e553 /* Undefined preprocessor variable, assumed 0 */
+ //-elib(553)
+// </c>
+
+/**** Rule 20.10 (Adv) ************/
+// <!c> Rule 20.10 (advisory): The # and ## preprocessor operators should not be used
+ //-e9024 /* '#/##' operators used */
+ //-elib(9024)
+// </c>
+
+/**** Rule 20.11 (Req) ************/
+// <!c> Rule 20.11 (required): A macro parameter immediately following a # operator shall not immediately be followed by a ## operator
+ //-e484 /* stringize operator followed by macro parameter followed by pasting operator */
+ //-elib(484)
+// </c>
+
+/**** Rule 20.12 (Req) ************/
+// <!c> Rule 20.12 (required): A macro parameter used as an operand to the # or ## operators, which is itself subject to further macro replacement, shall only be used as an operand to these operators
+ //-e9015 /* macro argument is used both with and without '#/##' and is subject to further replacement */
+ //-elib(9015)
+// </c>
+
+/**** Rule 20.13 (Req) ************/
+// <!c> Rule 20.13 (required): A line whose first token is # shall be a valid preprocessing directive
+ //-e544 /* endif or else not followed by EOL */
+ //-elib(544)
+ //-e16 /* # directive not followed by recognizable word */
+ //-elib(16)
+ ///* other parts of this rule such as a syntax check of the disabled portions of the code do not seem to be statically checkable */
+// </c>
+
+/**** Rule 20.14 (Req) ************/
+// <!c> Rule 20.14 (required): All #else, #elif and #endif preprocessor directives shall reside in the same file as the #if, #ifdef or #ifndef directive to which they are related
+ //-e405 /* #if/#ifdef/#ifndef not closed off */
+ //-elib(405)
+// </c>
+// </h>
+
+// <h> Rules 21.x: Standard libraries
+/**** Rule 21.1 (Req) ************/
+// <!c> Rule 21.1 (required): #define and #undef shall not be used on a reserved identifier or reserved macro name
+ //-e136 /* Illegal macro name */
+ //-elib(136)
+ ///* Undefining standard library macros is covered by rule 20.5. */
+ ///* Defining/redefining reserved/standard identifiers is covered by rules 20.4 and 21.2. */
+ //-e9071 /* defined macro reserved to the compiler */
+ //-elib(9071)
+ //-e9083 /* undefined macro reserved to the compiler */
+ //-elib(9083)
+// </c>
+
+/**** Rule 21.2 (Req) ************/
+// <!c> Rule 21.2 (required): A reserved identifier or macro name shall not be declared
+ //-e683 /* complain about #define standard functions */
+ //-elib(683)
+ ///* Undefining standard library macros is covered by rule 20.5. */
+ ///* Defining/redefining reserved/standard identifiers is covered by rule 20.4 and 21.2. */
+// </c>
+
+/**** Rule 21.3 (Req) ************/
+// <!c> Rule 21.3 (required): The memory allocation and deallocation functions of <stdlib.h> shall not be used
+ //-esym(586, calloc)
+ //-esym(586, malloc)
+ //-esym(586, realloc)
+ //-esym(586, free)
+// </c>
+
+/**** Rule 21.4 (Req) ************/
+// <!c> Rule 21.4 (required): The standard header file <setjmp.h> shall not be used
+ //-efile(829, setjmp.h)
+ //-esym(586, setjmp)
+ //-esym(586, longjmp)
+ //-esym(586, setjmp)
+ //-esym(586, longjmp)
+// </c>
+
+/**** Rule 21.5 (Req) ************/
+// <!c> Rule 21.5 (required): The standard header file <signal.h> shall not be used
+ //-efile(829, signal.h)
+ //-esym(586, signal)
+ //-esym(586, raise)
+ //-esym(586, SIGABRT)
+ //-esym(586, SIGFPE)
+ //-esym(586, SIGILL)
+ //-esym(586, SIGINT)
+ //-esym(586, SIGSEGV)
+ //-esym(586, SIGTERM)
+ //-esym(586, SIG_DFL)
+ //-esym(586, SIG_ERR)
+ //-esym(586, SIG_IGN)
+// </c>
+
+/**** Rule 21.6 (required): (Req) ************/
+// <!c> Rule 21.6 The Standard Library input/output functions shall not be used
+ //-esym(586, clearerr)
+ //-esym(586, fclose)
+ //-esym(586, feof)
+ //-esym(586, ferror)
+ //-esym(586, fflush)
+ //-esym(586, fgetc)
+ //-esym(586, fgetpos)
+ //-esym(586, fgets)
+ //-esym(586, fgetwc)
+ //-esym(586, fgetws)
+ //-esym(586, fopen)
+ //-esym(586, fprintf)
+ //-esym(586, fputc)
+ //-esym(586, fputs)
+ //-esym(586, fputwc)
+ //-esym(586, fputws)
+ //-esym(586, fread)
+ //-esym(586, fscanf)
+ //-esym(586, fseek)
+ //-esym(586, fsetpos)
+ //-esym(586, freopen)
+ //-esym(586, ftell)
+ //-esym(586, fwide)
+ //-esym(586, fwprintf)
+ //-esym(586, fwrite)
+ //-esym(586, fwscanf)
+ //-esym(586, getc)
+ //-esym(586, getchar)
+ //-esym(586, gets)
+ //-esym(586, getwc)
+ //-esym(586, getwchar)
+ //-esym(586, perror)
+ //-esym(586, printf)
+ //-esym(586, putc)
+ //-esym(586, putchar)
+ //-esym(586, puts)
+ //-esym(586, putwc)
+ //-esym(586, putwchar)
+ //-esym(586, remove)
+ //-esym(586, rename)
+ //-esym(586, rewind)
+ //-esym(586, scanf)
+ //-esym(586, setbuf)
+ //-esym(586, setvbuf)
+ //-esym(586, snprintf)
+ //-esym(586, sprintf)
+ //-esym(586, sscanf)
+ //-esym(586, swprintf)
+ //-esym(586, swscanf)
+ //-esym(586, tmpfile)
+ //-esym(586, tmpnam)
+ //-esym(586, ungetc)
+ //-esym(586, ungetwc)
+ //-esym(586, vfprintf)
+ //-esym(586, vfscanf)
+ //-esym(586, vfwprintf)
+ //-esym(586, vfwscanf)
+ //-esym(586, vprintf)
+ //-esym(586, vscanf)
+ //-esym(586, vsnprintf)
+ //-esym(586, vsprintf)
+ //-esym(586, vsscanf)
+ //-esym(586, vswprintf)
+ //-esym(586, vswscanf)
+ //-esym(586, vwprintf)
+ //-esym(586, vwscanf)
+ //-esym(586, wprintf)
+ //-esym(586, wscanf)
+ //-esym(586, clearerr)
+ //-esym(586, fclose)
+ //-esym(586, feof)
+ //-esym(586, ferror)
+ //-esym(586, fflush)
+ //-esym(586, fgetc)
+ //-esym(586, fgets)
+ //-esym(586, fgetpos)
+ //-esym(586, fgetwc)
+ //-esym(586, fgetws)
+ //-esym(586, fopen)
+ //-esym(586, fprintf)
+ //-esym(586, fputc)
+ //-esym(586, fputs)
+ //-esym(586, fputwc)
+ //-esym(586, fputws)
+ //-esym(586, fread)
+ //-esym(586, fscanf)
+ //-esym(586, fseek)
+ //-esym(586, fsetpos)
+ //-esym(586, freopen)
+ //-esym(586, ftell)
+ //-esym(586, fwide)
+ //-esym(586, fwprintf)
+ //-esym(586, fwrite)
+ //-esym(586, fwscanf)
+ //-esym(586, getc)
+ //-esym(586, getchar)
+ //-esym(586, gets)
+ //-esym(586, getwc)
+ //-esym(586, getwchar)
+ //-esym(586, perror)
+ //-esym(586, printf)
+ //-esym(586, putc)
+ //-esym(586, putchar)
+ //-esym(586, puts)
+ //-esym(586, putwc)
+ //-esym(586, putwchar)
+ //-esym(586, remove)
+ //-esym(586, rename)
+ //-esym(586, rewind)
+ //-esym(586, scanf)
+ //-esym(586, setbuf)
+ //-esym(586, setvbuf)
+ //-esym(586, snprintf)
+ //-esym(586, sprintf)
+ //-esym(586, sscanf)
+ //-esym(586, swprintf)
+ //-esym(586, swscanf)
+ //-esym(586, tmpfile)
+ //-esym(586, tmpnam)
+ //-esym(586, ungetc)
+ //-esym(586, ungetwc)
+ //-esym(586, vfprintf)
+ //-esym(586, vfscanf)
+ //-esym(586, vfwprintf)
+ //-esym(586, vfwscanf)
+ //-esym(586, vprintf)
+ //-esym(586, vscanf)
+ //-esym(586, vsnprintf)
+ //-esym(586, vsprintf)
+ //-esym(586, vsscanf)
+ //-esym(586, vswprintf)
+ //-esym(586, vswscanf)
+ //-esym(586, vwprintf)
+ //-esym(586, vwscanf)
+ //-esym(586, wprintf)
+ //-esym(586, wscanf)
+// </c>
+
+/**** Rule 21.7 (Req) ************/
+// <!c> Rule 21.7 (required): The atof, atoi, atol and atoll functions of <stdlib.h> shall not be used
+ //-esym(586, atof)
+ //-esym(586, atoi)
+ //-esym(586, atol)
+ //-esym(586, atoll)
+ //-esym(586, atof)
+ //-esym(586, atoi)
+ //-esym(586, atol)
+ //-esym(586, atoll)
+// </c>
+
+/**** Rule 21.8 (Req) ************/
+// <!c> Rule 21.8 (required): The library functions abort, exit, getenv and system of <stdlib.h> shall not be used
+ //-esym(586, abort)
+ //-esym(586, exit)
+ //-esym(586, getenv)
+ //-esym(586, system)
+ //-esym(586, abort)
+ //-esym(586, exit)
+ //-esym(586, getenv)
+ //-esym(586, system)
+// </c>
+
+/**** Rule 21.9 (Req) ************/
+// <!c> Rule 21.9 (required): The library functions bsearch and qsort of <stdlib.h> shall not be used
+ //-esym(586, bsearch)
+ //-esym(586, qsort)
+ //-esym(586, bsearch)
+ //-esym(586, qsort)
+// </c>
+
+/**** Rule 21.10 (Req) ************/
+// <!c> Rule 21.10 (required): The Standard Library time and date functions shall not be used
+ //-efile(829, time.h)
+ //-esym(586, wcsftime)
+ //-esym(586, wcsftime)
+ //-esym(586, clock)
+ //-esym(586, clock)
+ //-esym(586, difftime)
+ //-esym(586, difftime)
+ //-esym(586, mktime)
+ //-esym(586, mktime)
+ //-esym(586, time)
+ //-esym(586, time)
+ //-esym(586, asctime)
+ //-esym(586, asctime)
+ //-esym(586, ctime)
+ //-esym(586, ctime)
+ //-esym(586, gmtime)
+ //-esym(586, gmtime)
+ //-esym(586, localtime)
+ //-esym(586, localtime)
+ //-esym(586, strftime)
+ //-esym(586, strftime)
+ //-esym(586, CLOCKS_PER_SEC)
+// </c>
+
+/**** Rule 21.11 (Req) ************/
+// <!c> Rule 21.11 (required): The standard header file <tgmath.h> shall not be used
+ //-efile(829, tgmath.h)
+// </c>
+
+/**** Rule 21.12 (Adv) ************/
+// <!c> Rule 21.12 (advisory): The exception handling features of <fenv.h> should not be used
+ //-esym(586, feclearexcept)
+ //-esym(586, feclearexcept)
+ //-esym(586, fegetexceptflag)
+ //-esym(586, fegetexceptflag)
+ //-esym(586, feraiseexcept)
+ //-esym(586, feraiseexcept)
+ //-esym(586, fesetexceptflag)
+ //-esym(586, fesetexceptflag)
+ //-esym(586, fetestexcept)
+ //-esym(586, fetestexcept)
+ //-esym(586, FE_INEXACT)
+ //-esym(586, FE_DIVBYZERO)
+ //-esym(586, FE_UNDERFLOW)
+ //-esym(586, FE_OVERFLOW)
+ //-esym(586, FE_INVALID)
+ //-esym(586, FE_ALL_EXCEPT)
+// </c>
+// </h>
+
+// <h> Rules 22.x: Resources
+/**** Rule 22.1 (Req) ************/
+// <!c> Rule 22.1 (required): All resources obtained dynamically by means of Standard Library functions shall be explicitly released
+ //-e429 /* custodial pointer neither free'd nor returned */
+ //-elib(429)
+ //-e480 /* no balancing call */
+ //-elib(480)
+ //-e481 /* different balance call states */
+ //-elib(481)
+// </c>
+
+/**** Rule 22.2 (Mand) ************/
+// <!c> Rule 22.2 (mandatory): A block of memory shall only be freed if it was allocated by means of a Standard Library function
+ //-e424 /* inappropriate deallocation */
+ //-elib(424)
+ //-e449 /* pointer previously deallocated */
+ //-elib(449)
+// </c>
+
+/**** Rule 22.3 (required): (Req) ************/
+// <n> Rule 22.3 The same file shall not be open for read and write access at the same time on different streams
+// <i> *** NOT CHECKED *** MISRA has declared this rule to be "undecidable"
+
+/**** Rule 22.4 (Mand) ************/
+// <n> Rule 22.4 (mandatory): There shall be no attempt to write to a stream which has been opened as read-only
+// <i> *** NOT CHECKED *** MISRA has declared this rule to be "undecidable"
+
+/**** Rule 22.5 (Mand) ************/
+// <!c> Rule 22.5 (mandatory): A pointer to a FILE object shall not be dereferenced
+ //-e9047 /* FILE pointer dereferenced */
+ //-elib(9047)
+// </c>
+
+/**** Rule 22.6 (Mand) ************/
+// <!c> Rule 22.6 (mandatory): The value of a pointer to a FILE shall not be used after the associated stream has been closed
+ //-e449 /* previously deallocated pointer */
+ //-elib(449)
+// </c>
+// </h>
+
+// </h>
+
+// <<< end of configuration section >>>
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/CMSIS_CORE_Validation/CV_Config.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/CMSIS_CORE_Validation/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/CMSIS_CORE_Validation/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Compiler/EventRecorderConf.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Compiler/EventRecorderConf.h
new file mode 100644
index 0000000..b2086e0
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Compiler/EventRecorderConf.h
@@ -0,0 +1,44 @@
+/*------------------------------------------------------------------------------
+ * MDK - Component ::Event Recorder
+ * Copyright (c) 2016 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name: EventRecorderConf.h
+ * Purpose: Event Recorder Configuration
+ * Rev.: V1.0.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Event Recorder
+
+// <o>Number of Records
+// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
+// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
+// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288
+// <1048576=>1048576
+// <i>Configure size of Event Record Buffer (each record is 16 bytes)
+// <i>Must be 2^n (min=8, max=1048576)
+#define EVENT_RECORD_COUNT 64U
+
+// <o>Time Stamp Source
+// <0=> DWT Cycle Counter <1=> SysTick
+// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset)
+// <i>Selects source for 32-bit time stamp
+#define EVENT_TIMESTAMP_SOURCE 0
+
+// <h>SysTick Configuration
+// <i>Configure values when Time Stamp Source is set to SysTick
+
+// <o>SysTick Input Clock Frequency [Hz] <1-1000000000>
+// <i>Defines SysTick input clock (typical identical with processor clock)
+#define SYSTICK_CLOCK 100000000U
+
+// <o>SysTick Interrupt Period [us] <1-1000000000>
+// <i>Defines time period of the SysTick timer interrupt
+#define SYSTICK_PERIOD_US 1000U
+
+// </h>
+
+// </h>
+
+//------------- <<< end of configuration section >>> ---------------------------
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.c
new file mode 100644
index 0000000..35e8427
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.c
@@ -0,0 +1,291 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0 Device Series
+ * @version V5.00
+ * @date 26. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M0 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM0 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M0 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.s
new file mode 100644
index 0000000..9fc447d
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/startup_ARMCM0.s
@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device Series
+; * @version V5.00
+; * @date 02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/system_ARMCM0.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/system_ARMCM0.c
new file mode 100644
index 0000000..bb0d5eb
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM0/system_ARMCM0.c
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h
new file mode 100644
index 0000000..f2354ee
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h
@@ -0,0 +1,1232 @@
+/**************************************************************************//**
+ * @file partition_ARMCM23.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
+ * @version V5.00
+ * @date 28. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM23_H
+#define PARTITION_ARMCM23_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+
+/*
+// <e>Setup behaviour of single SysTick
+*/
+#define SCB_ICSR_INIT 0
+
+/*
+// <o> in a single SysTick implementation, SysTick is
+// <0=>Secure
+// <1=>Non-Secure
+// <i> Value for SCB->ICSR register bit STTNS
+// <i> only for single SysTick implementation
+*/
+#define SCB_ICSR_STTNS_VAL 0
+
+/*
+// </e>
+*/
+
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x0000122B
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
+ SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
+ ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
+ #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM23_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c
new file mode 100644
index 0000000..46569ce
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c
@@ -0,0 +1,291 @@
+/**************************************************************************//**
+ * @file startup_ARMCM23.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM23 Device Series
+ * @version V5.00
+ * @date 21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* ARMCM23 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM23 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* ARMCM23 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s
new file mode 100644
index 0000000..3f2eb00
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s
@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM23.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM23 Device Series
+; * @version V5.00
+; * @date 21. October 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/system_ARMCM23.c
new file mode 100644
index 0000000..0bfd52b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM23_TZ/system_ARMCM23.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+ * @file system_ARMCM23.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM23 Device Series
+ * @version V5.00
+ * @date 21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM23.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.c
new file mode 100644
index 0000000..9f7c76a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.c
@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file startup_ARMCM3.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM3 Device Series
+ * @version V5.00
+ * @date 26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M3 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM3 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M3 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.s
new file mode 100644
index 0000000..16e56b0
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/startup_ARMCM3.s
@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device Series
+; * @version V5.00
+; * @date 02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/system_ARMCM3.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/system_ARMCM3.c
new file mode 100644
index 0000000..658d154
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM3/system_ARMCM3.c
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
new file mode 100644
index 0000000..ff24424
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
@@ -0,0 +1,1260 @@
+/**************************************************************************//**
+ * @file partition_ARMCM33.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
+ * @version V5.0.1
+ * @date 07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM33_H
+#define PARTITION_ARMCM33_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// <o>Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM33_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
new file mode 100644
index 0000000..80702f4
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c
@@ -0,0 +1,296 @@
+/**************************************************************************//**
+ * @file startup_ARMCM33.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM33 Device Series
+ * @version V5.00
+ * @date 21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* ARMCM33 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM33 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* ARMCM33 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ SecureFault_Handler, /* Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
new file mode 100644
index 0000000..1e28f2e
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
@@ -0,0 +1,267 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM33.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM33 Device Series
+; * @version V5.00
+; * @date 21. October 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SecureFault_Handler\
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
new file mode 100644
index 0000000..9ad7594
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
@@ -0,0 +1,99 @@
+/**************************************************************************//**
+ * @file system_ARMCM33.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM33 Device Series
+ * @version V5.00
+ * @date 02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM33.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c
new file mode 100644
index 0000000..1afe878
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c
@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file startup_ARMCM4.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M4 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM4 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M4 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
new file mode 100644
index 0000000..dae6439
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device Series
+; * @version V5.00
+; * @date 02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/system_ARMCM4.c
new file mode 100644
index 0000000..af23005
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM4_FP/system_ARMCM4.c
@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file system_ARMCM4.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/gcc_arm.ld b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/gcc_arm.ld
new file mode 100644
index 0000000..b987fd1
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/gcc_arm.ld
@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c
new file mode 100644
index 0000000..26edb9f
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c
@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file startup_ARMCM7.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM7 Device Series
+ * @version V5.00
+ * @date 26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void); /* CMSIS System Initialization */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+ User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+ #define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+ #define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M7 Processor Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM7 Specific Interrupts */
+void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M7 Exceptions Handler */
+ (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External interrupts */
+ WDT_IRQHandler, /* 0: Watchdog Timer */
+ RTC_IRQHandler, /* 1: Real Time Clock */
+ TIM0_IRQHandler, /* 2: Timer0 / Timer1 */
+ TIM2_IRQHandler, /* 3: Timer2 / Timer3 */
+ MCIA_IRQHandler, /* 4: MCIa */
+ MCIB_IRQHandler, /* 5: MCIb */
+ UART0_IRQHandler, /* 6: UART0 - DUT FPGA */
+ UART1_IRQHandler, /* 7: UART1 - DUT FPGA */
+ UART2_IRQHandler, /* 8: UART2 - DUT FPGA */
+ UART4_IRQHandler, /* 9: UART4 - not connected */
+ AACI_IRQHandler, /* 10: AACI / AC97 */
+ CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */
+ ENET_IRQHandler, /* 12: Ethernet */
+ USBDC_IRQHandler, /* 13: USB Device */
+ USBHC_IRQHandler, /* 14: USB Host Controller */
+ CHLCD_IRQHandler, /* 15: Character LCD */
+ FLEXRAY_IRQHandler, /* 16: Flexray */
+ CAN_IRQHandler, /* 17: CAN */
+ LIN_IRQHandler, /* 18: LIN */
+ I2C_IRQHandler, /* 19: I2C ADC/DAC */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ 0, /* 26: Reserved */
+ 0, /* 27: Reserved */
+ CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */
+ 0, /* 29: Reserved - CPU FPGA */
+ UART3_IRQHandler, /* 30: UART3 - CPU FPGA */
+ SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t*)*(pTable + 0);
+ pDest = (uint32_t*)*(pTable + 1);
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for ( ; pDest < &__data_end__ ; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t*)*(pTable + 0);
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+ *pDest++ = 0;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for ( ; pDest < &__bss_end__ ; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.s b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.s
new file mode 100644
index 0000000..b69f038
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/startup_ARMCM7.s
@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM7.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM7 Device Series
+; * @version V5.00
+; * @date 02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/system_ARMCM7.c b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/system_ARMCM7.c
new file mode 100644
index 0000000..22edd9c
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/Device/ARMCM7_DP/system_ARMCM7.c
@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file system_ARMCM7.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM7 Device Series
+ * @version V5.00
+ * @date 07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC5__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC5__FVP_/RTE_Components.h
new file mode 100644
index 0000000..391eae3
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC5__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M0 (AC5, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..2cc5b00
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M0 (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..9a229bc
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M0__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M0 (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..bfd3788
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M23 (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM23_TZ.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..8a9f7cc
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M23__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M23 (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM23_TZ.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..ea47068
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M33 (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..3275e5b
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M33__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M33 (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC5__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC5__FVP_/RTE_Components.h
new file mode 100644
index 0000000..1d4d18d
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC5__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M3 (AC5, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..c5af8c9
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M3 (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..7358b34
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M3__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M3 (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC5__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC5__FVP_/RTE_Components.h
new file mode 100644
index 0000000..727dcb6
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC5__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M4f (AC5, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..eb1721a
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M4f (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..9ae12af
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M4f__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M4f (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__AC6__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__AC6__FVP_/RTE_Components.h
new file mode 100644
index 0000000..2b24653
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__AC6__FVP_/RTE_Components.h
@@ -0,0 +1,27 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M7 (AC6, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM7_DP.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__GCC__FVP_/RTE_Components.h b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__GCC__FVP_/RTE_Components.h
new file mode 100644
index 0000000..38e9e54
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/RTE/_Cortex-M7__GCC__FVP_/RTE_Components.h
@@ -0,0 +1,25 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV'
+ * Target: 'Cortex-M7 (GCC, FVP)'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM7_DP.h"
+
+#define RTE_CV_COREFUNC /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR /* CORE Validation - Core Instruction tests enabled */
+#define RTE_CV_MPUFUNC /* CORE Validation - MPU Function tests enabled */
+#define RTE_Compiler_EventRecorder
+ #define RTE_Compiler_EventRecorder_DAP
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/CoreValidation/Examples/MDK-FVP/main.c b/CMSIS/CoreValidation/Examples/MDK-FVP/main.c
new file mode 100644
index 0000000..67bca24
--- /dev/null
+++ b/CMSIS/CoreValidation/Examples/MDK-FVP/main.c
@@ -0,0 +1,42 @@
+/*----------------------------------------------------------------------------
+ * Name: main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+//lint -e970 allow using int for main
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main (void)
+{
+
+ // System Initialization
+ SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+ // Initialize and start Event Recorder
+ (void)EventRecorderInitialize(EventRecordError, 1U);
+ (void)EventRecorderEnable (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+ cmsis_cv();
+
+ for(;;) {}
+}
diff --git a/CMSIS/CoreValidation/Include/CV_Framework.h b/CMSIS/CoreValidation/Include/CV_Framework.h
new file mode 100644
index 0000000..241f615
--- /dev/null
+++ b/CMSIS/CoreValidation/Include/CV_Framework.h
@@ -0,0 +1,44 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Framework.h
+ * Purpose: Framework header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __FRAMEWORK_H__
+#define __FRAMEWORK_H__
+
+#include "CV_Typedefs.h"
+#include "CV_Report.h"
+
+/*-----------------------------------------------------------------------------
+ * Test framework global definitions
+ *----------------------------------------------------------------------------*/
+
+/* Test case definition macro */
+#define TCD(x, y) {x, #x, y}
+
+/* Test case description structure */
+typedef struct __TestCase {
+ void (*TestFunc)(void); /* Test function */
+ const char *TFName; /* Test function name string */
+ BOOL en; /* Test function enabled */
+} TEST_CASE;
+
+/* Test suite description structure */
+typedef struct __TestSuite {
+ const char *FileName; /* Test module file name */
+ const char *Date; /* Compilation date */
+ const char *Time; /* Compilation time */
+ const char *ReportTitle; /* Title or name of module under test */
+ void (*Init)(void); /* Init function callback */
+
+ uint32_t TCBaseNum; /* Base number for test case numbering */
+ TEST_CASE *TC; /* Array of test cases */
+ uint32_t NumOfTC; /* Number of test cases (sz of TC array)*/
+
+} TEST_SUITE;
+
+/* Defined in user test module */
+extern TEST_SUITE ts;
+
+#endif /* __FRAMEWORK_H__ */
diff --git a/CMSIS/CoreValidation/Include/CV_Report.h b/CMSIS/CoreValidation/Include/CV_Report.h
new file mode 100644
index 0000000..7c34466
--- /dev/null
+++ b/CMSIS/CoreValidation/Include/CV_Report.h
@@ -0,0 +1,89 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Report.h
+ * Purpose: Report statistics and layout header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __REPORT_H__
+#define __REPORT_H__
+
+#include "CV_Config.h"
+#include "CV_Typedefs.h"
+
+/*-----------------------------------------------------------------------------
+ * Test report global definitions
+ *----------------------------------------------------------------------------*/
+
+#define REP_TC_FAIL 0
+#define REP_TC_WARN 1
+#define REP_TC_PASS 2
+#define REP_TC_NOEX 3
+
+/* Test case result definition */
+typedef enum {
+ PASSED = 0,
+ WARNING,
+ FAILED,
+ NOT_EXECUTED
+} TC_RES;
+
+/* Assertion result info */
+typedef struct {
+ const char *module; /* Module name */
+ uint32_t line; /* Assertion line */
+} AS_INFO;
+
+/* Test case callback interface definition */
+typedef struct {
+ BOOL (* Result) (TC_RES res);
+ BOOL (* Dbgi) (TC_RES res, const char *fn, uint32_t ln, char *desc);
+} TC_ITF;
+
+/* Assert interface to the report */
+extern TC_ITF tcitf;
+
+/* Assertion result buffer */
+typedef struct {
+AS_INFO passed[BUFFER_ASSERTIONS];
+AS_INFO failed[BUFFER_ASSERTIONS];
+AS_INFO warnings[BUFFER_ASSERTIONS];
+} AS_T_INFO;
+
+/* Assertion statistics */
+typedef struct {
+ uint32_t passed; /* Total assertions passed */
+ uint32_t failed; /* Total assertions failed */
+ uint32_t warnings; /* Total assertions warnings */
+ AS_T_INFO info; /* Detailed assertion info */
+} AS_STAT;
+
+/* Test global statistics */
+typedef struct {
+ uint32_t tests; /* Total test cases count */
+ uint32_t executed; /* Total test cases executed */
+ uint32_t passed; /* Total test cases passed */
+ uint32_t failed; /* Total test cases failed */
+ uint32_t warnings; /* Total test cases warnings */
+ AS_STAT assertions; /* Total assertions statistics */
+} TEST_REPORT;
+
+/* Test report interface */
+typedef struct {
+ BOOL (* Init) (void);
+ BOOL (* Open) (const char *title, const char *date, const char *time, const char *fn);
+ BOOL (* Close) (void);
+ BOOL (* Open_TC) (uint32_t num, const char *fn);
+ BOOL (* Close_TC) (void);
+} REPORT_ITF;
+
+/* Test report statistics */
+extern TEST_REPORT test_report;
+
+/* Test report interface */
+extern REPORT_ITF ritf;
+
+/* Assertions and test results */
+extern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc);
+extern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond);
+
+#endif /* __REPORT_H__ */
diff --git a/CMSIS/CoreValidation/Include/CV_Typedefs.h b/CMSIS/CoreValidation/Include/CV_Typedefs.h
new file mode 100644
index 0000000..63f32c3
--- /dev/null
+++ b/CMSIS/CoreValidation/Include/CV_Typedefs.h
@@ -0,0 +1,54 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Typedefs.h
+ * Purpose: Test framework filetypes and structures description
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <string.h>
+#include <stdio.h>
+
+typedef unsigned int BOOL;
+
+#ifndef __TRUE
+ #define __TRUE 1
+#endif
+#ifndef __FALSE
+ #define __FALSE 0
+#endif
+
+#ifndef ENABLED
+ #define ENABLED 1
+#endif
+#ifndef DISABLED
+ #define DISABLED 0
+#endif
+
+#ifndef NULL
+ #ifdef __cplusplus // EC++
+ #define NULL 0
+ #else
+ #define NULL ((void *) 0)
+ #endif
+#endif
+
+#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))
+
+static const int BACKSLASH = '\\';
+
+//lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename
+//lint -emacro(613,__FILENAME__) null pointer is checked
+#define __FILENAME__ ((strrchr(__FILE__, BACKSLASH) != NULL) ? (strrchr(__FILE__, BACKSLASH) + 1) : __FILE__)
+
+/* Assertions and test results */
+#define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc));
+
+//lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter
+//lint -emacro(613,ASSERT_TRUE) null pointer is checked
+#define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U);
+
+#endif /* __TYPEDEFS_H__ */
diff --git a/CMSIS/CoreValidation/Include/cmsis_cv.h b/CMSIS/CoreValidation/Include/cmsis_cv.h
new file mode 100644
index 0000000..7bcceec
--- /dev/null
+++ b/CMSIS/CoreValidation/Include/cmsis_cv.h
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+ * Name: cmsis_cv.h
+ * Purpose: cmsis_cv header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CMSIS_CV_H
+#define __CMSIS_CV_H
+
+#include <stdint.h>
+#include "CV_Config.h"
+
+/* Expansion macro used to create CMSIS Driver references */
+#define EXPAND_SYMBOL(name, port) name##port
+#define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
+
+// Simulator counter
+#ifndef HW_PRESENT
+extern uint32_t SIM_CYCCNT;
+#endif
+
+// SVC interrupt callback
+extern void (*TST_IRQHandler)(void);
+
+// Test main function
+extern void cmsis_cv (void);
+
+// Test cases
+#ifdef RTE_CV_COREINSTR
+extern void TC_CoreInstr_NOP (void);
+extern void TC_CoreInstr_REV (void);
+extern void TC_CoreInstr_REV16 (void);
+extern void TC_CoreInstr_REVSH (void);
+extern void TC_CoreInstr_ROR (void);
+extern void TC_CoreInstr_RBIT (void);
+extern void TC_CoreInstr_CLZ (void);
+extern void TC_CoreInstr_SSAT (void);
+extern void TC_CoreInstr_USAT (void);
+#endif
+
+#ifdef RTE_CV_COREFUNC
+ #if defined(__CORTEX_M)
+ extern void TC_CoreFunc_EnDisIRQ (void);
+ extern void TC_CoreFunc_Control (void);
+ extern void TC_CoreFunc_IPSR (void);
+ extern void TC_CoreFunc_APSR (void);
+ extern void TC_CoreFunc_PSP (void);
+ extern void TC_CoreFunc_MSP (void);
+ extern void TC_CoreFunc_PRIMASK (void);
+
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+ extern void TC_CoreFunc_FAULTMASK (void);
+ extern void TC_CoreFunc_BASEPRI (void);
+
+ #endif
+
+ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+ extern void TC_CoreFunc_FPSCR (void);
+
+ #endif
+ #elif defined(__CORTEX_A)
+ extern void TC_CoreAFunc_IRQ (void);
+ extern void TC_CoreAFunc_FPSCR (void);
+ extern void TC_CoreAFunc_CPSR (void);
+ extern void TC_CoreAFunc_Mode (void);
+ extern void TC_CoreAFunc_SP (void);
+ extern void TC_CoreAFunc_SP_usr (void);
+ extern void TC_CoreAFunc_FPEXC (void);
+ extern void TC_CoreAFunc_ACTLR (void);
+ extern void TC_CoreAFunc_CPACR (void);
+ extern void TC_CoreAFunc_DFSR (void);
+ extern void TC_CoreAFunc_IFSR (void);
+ extern void TC_CoreAFunc_ISR (void);
+ extern void TC_CoreAFunc_CBAR (void);
+ extern void TC_CoreAFunc_TTBR0 (void);
+ extern void TC_CoreAFunc_DACR (void);
+ extern void TC_CoreAFunc_SCTLR (void);
+ extern void TC_CoreAFunc_ACTRL (void);
+ extern void TC_CoreAFunc_MPIDR (void);
+ extern void TC_CoreAFunc_VBAR (void);
+ #endif
+#endif
+
+#ifdef RTE_CV_MPUFUNC
+#if defined(__MPU_PRESENT) && __MPU_PRESENT
+extern void TC_MPU_SetClear (void);
+extern void TC_MPU_Load (void);
+#endif
+#endif
+
+#ifdef RTE_CV_GENTIMER
+extern void TC_GenTimer_CNTFRQ (void);
+extern void TC_GenTimer_CNTP_TVAL (void);
+extern void TC_GenTimer_CNTP_CTL (void);
+#endif
+
+#endif /* __CMSIS_CV_H */
diff --git a/CMSIS/CoreValidation/Source/CV_CoreAFunc.c b/CMSIS/CoreValidation/Source/CV_CoreAFunc.c
new file mode 100644
index 0000000..1f773f2
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_CoreAFunc.c
@@ -0,0 +1,219 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_CoreFunc.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_IRQ(void) {
+ __enable_irq();
+ __disable_irq();
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_FPSCR(void) {
+
+ volatile float f1 = 47.11f;
+ volatile float f2 = 8.15f;
+ volatile float f3 = f1 / f2;
+
+ uint32_t fpscr = __get_FPSCR();
+ __set_FPSCR(fpscr);
+
+ ASSERT_TRUE(fpscr == __get_FPSCR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+#if defined(__CC_ARM)
+#define __SUBS(Rd, Rm, Rn) __ASM("SUBS " # Rd ", " # Rm ", " # Rn)
+#define __ADDS(Rd, Rm, Rn) __ASM("ADDS " # Rd ", " # Rm ", " # Rn)
+#elif defined( __GNUC__ ) && defined(__thumb__)
+#define __SUBS(Rd, Rm, Rn) __ASM("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#else
+#define __SUBS(Rd, Rm, Rn) __ASM("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#endif
+
+void TC_CoreAFunc_CPSR(void) {
+ uint32_t result;
+
+ uint32_t cpsr = __get_CPSR();
+ __set_CPSR(cpsr & CPSR_M_Msk);
+
+ // Check negative flag
+ int32_t Rm = 5;
+ int32_t Rn = 7;
+ __SUBS(Rm, Rm, Rn);
+ result = __get_CPSR();
+ ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk);
+
+ // Check zero and compare flag
+ Rm = 5;
+ __SUBS(Rm, Rm, Rm);
+ result = __get_CPSR();
+ ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk);
+ ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk);
+
+ // Check overflow flag
+ Rm = 5;
+ Rn = INT32_MAX;
+ __ADDS(Rm, Rm, Rn);
+ result = __get_CPSR();
+ ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_Mode(void) {
+ uint32_t mode = __get_mode();
+ __set_mode(mode);
+
+ ASSERT_TRUE(mode == __get_mode());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+static uint32_t TC_CoreAFunc_SP_orig;
+static uint32_t TC_CoreAFunc_SP_sp;
+static uint32_t TC_CoreAFunc_SP_result;
+
+void TC_CoreAFunc_SP(void) {
+ TC_CoreAFunc_SP_orig = __get_SP();
+
+ TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U;
+ __set_SP(TC_CoreAFunc_SP_sp);
+ TC_CoreAFunc_SP_result = __get_SP();
+
+ __set_SP(TC_CoreAFunc_SP_orig);
+
+ ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+static uint32_t TC_CoreAFunc_SP_usr_orig;
+static uint32_t TC_CoreAFunc_SP_usr_sp;
+static uint32_t TC_CoreAFunc_SP_usr_result;
+
+void TC_CoreAFunc_SP_usr(void) {
+ TC_CoreAFunc_SP_usr_orig = __get_SP_usr();
+
+ TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U;
+ __set_SP(TC_CoreAFunc_SP_usr_sp);
+ TC_CoreAFunc_SP_usr_result = __get_SP_usr();
+
+ __set_SP(TC_CoreAFunc_SP_usr_orig);
+
+ ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_FPEXC(void) {
+ uint32_t fpexc = __get_FPEXC();
+ __set_FPEXC(fpexc);
+
+ ASSERT_TRUE(fpexc == __get_FPEXC());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_ACTLR(void) {
+ uint32_t actlr = __get_ACTLR();
+ __set_ACTLR(actlr);
+
+ ASSERT_TRUE(actlr == __get_ACTLR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_CPACR(void) {
+ uint32_t cpacr = __get_CPACR();
+ __set_CPACR(cpacr);
+
+ ASSERT_TRUE(cpacr == __get_CPACR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_DFSR(void) {
+ uint32_t dfsr = __get_DFSR();
+ __set_DFSR(dfsr);
+
+ ASSERT_TRUE(dfsr == __get_DFSR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_IFSR(void) {
+ uint32_t ifsr = __get_IFSR();
+ __set_IFSR(ifsr);
+
+ ASSERT_TRUE(ifsr == __get_IFSR());
+}
+
+/*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_ISR(void) {
+ uint32_t isr = __get_ISR();
+
+ ASSERT_TRUE(isr == __get_ISR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_CBAR(void) {
+ uint32_t cbar = __get_CBAR();
+
+ ASSERT_TRUE(cbar == __get_CBAR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_TTBR0(void) {
+ uint32_t ttbr0 = __get_TTBR0();
+ __set_TTBR0(ttbr0);
+
+ ASSERT_TRUE(ttbr0 == __get_TTBR0());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_DACR(void) {
+ uint32_t dacr = __get_DACR();
+ __set_DACR(dacr);
+
+ ASSERT_TRUE(dacr == __get_DACR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_SCTLR(void) {
+ uint32_t sctlr = __get_SCTLR();
+ __set_SCTLR(sctlr);
+
+ ASSERT_TRUE(sctlr == __get_SCTLR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_ACTRL(void) {
+ uint32_t actrl = __get_ACTRL();
+ __set_ACTRL(actrl);
+
+ ASSERT_TRUE(actrl == __get_ACTRL());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_MPIDR(void) {
+ uint32_t mpidr = __get_MPIDR();
+
+ ASSERT_TRUE(mpidr == __get_MPIDR());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_CoreAFunc_VBAR(void) {
+ uint32_t vbar = __get_VBAR();
+ __set_VBAR(vbar);
+
+ ASSERT_TRUE(vbar == __get_VBAR());
+}
diff --git a/CMSIS/CoreValidation/Source/CV_CoreFunc.c b/CMSIS/CoreValidation/Source/CV_CoreFunc.c
new file mode 100644
index 0000000..65819c3
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_CoreFunc.c
@@ -0,0 +1,377 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_CoreFunc.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+static volatile uint32_t irqTaken = 0U;
+
+static void TC_CoreFunc_EnDisIRQIRQHandler(void) {
+ ++irqTaken;
+}
+
+static volatile uint32_t irqIPSR = 0U;
+static volatile uint32_t irqXPSR = 0U;
+
+static void TC_CoreFunc_IPSR_IRQHandler(void) {
+ irqIPSR = __get_IPSR();
+ irqXPSR = __get_xPSR();
+}
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_EnDisIRQ
+\details
+- Check if __disable_irq() and __enable_irq() have expected behaviour.
+*/
+void TC_CoreFunc_EnDisIRQ (void)
+{
+ __disable_irq();
+
+ NVIC_EnableIRQ(WDT_IRQn);
+ NVIC_ClearPendingIRQ(WDT_IRQn);
+
+ TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
+ irqTaken = 0U;
+
+ NVIC_SetPendingIRQ(WDT_IRQn);
+ for(uint32_t i = 10U; i > 0U; --i) {}
+
+ // Interrupt is not taken
+ ASSERT_TRUE(irqTaken == 0U);
+
+ __enable_irq();
+
+ for(uint32_t i = 10U; i > 0U; --i) {}
+
+ // Interrupt was taken
+ ASSERT_TRUE(irqTaken == 1U);
+
+ __disable_irq();
+ NVIC_DisableIRQ(WDT_IRQn);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_GetCtrl
+\details
+- Check if __set_CONTROL and __get_CONTROL() sets/gets control register
+*/
+void TC_CoreFunc_Control (void) {
+ // don't use stack for this variables
+ static uint32_t orig;
+ static uint32_t ctrl;
+ static uint32_t result;
+
+ orig = __get_CONTROL();
+ ctrl = orig;
+ result = UINT32_MAX;
+
+#ifdef CONTROL_SPSEL_Msk
+ // toggle SPSEL
+ ctrl = (ctrl & ~CONTROL_SPSEL_Msk) | (~ctrl & CONTROL_SPSEL_Msk);
+#endif
+
+ __set_CONTROL(ctrl);
+ __ISB();
+
+ result = __get_CONTROL();
+
+ __set_CONTROL(orig);
+ __ISB();
+
+ ASSERT_TRUE(result == ctrl);
+ ASSERT_TRUE(__get_CONTROL() == orig);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_IPSR
+\details
+- Check if __get_IPSR instrinsic is available
+- Check if __get_xPSR instrinsic is available
+- Result differentiates between thread and exception modes
+*/
+void TC_CoreFunc_IPSR (void) {
+ uint32_t result = __get_IPSR();
+ ASSERT_TRUE(result == 0U); // Thread Mode
+
+ result = __get_xPSR();
+ ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode
+
+ TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler;
+ irqIPSR = 0U;
+ irqXPSR = 0U;
+
+ NVIC_ClearPendingIRQ(WDT_IRQn);
+ NVIC_EnableIRQ(WDT_IRQn);
+ __enable_irq();
+
+ NVIC_SetPendingIRQ(WDT_IRQn);
+ for(uint32_t i = 10U; i > 0U; --i) {}
+
+ __disable_irq();
+ NVIC_DisableIRQ(WDT_IRQn);
+
+ ASSERT_TRUE(irqIPSR != 0U); // Exception Mode
+ ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+
+#if defined(__CC_ARM)
+#define SUBS(Rd, Rm, Rn) __ASM("SUBS " # Rd ", " # Rm ", " # Rn)
+#define ADDS(Rd, Rm, Rn) __ASM("ADDS " # Rd ", " # Rm ", " # Rn)
+#elif defined( __GNUC__ )
+#define SUBS(Rd, Rm, Rn) __ASM("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define ADDS(Rd, Rm, Rn) __ASM("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#elif defined(_lint)
+//lint -save -e(9026) allow function-like macro
+#define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn))
+#define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn))
+//lint -restore
+#else
+#define SUBS(Rd, Rm, Rn) __ASM("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define ADDS(Rd, Rm, Rn) __ASM("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#endif
+
+/**
+\brief Test case: TC_CoreFunc_APSR
+\details
+- Check if __get_APSR instrinsic is available
+- Check if __get_xPSR instrinsic is available
+- Check negative, zero and overflow flags
+*/
+void TC_CoreFunc_APSR (void) {
+ uint32_t result;
+ //lint -esym(838, Rm) unused values
+ //lint -esym(438, Rm) unused values
+
+ // Check negative flag
+ int32_t Rm = 5;
+ int32_t Rn = 7;
+ SUBS(Rm, Rm, Rn);
+ result = __get_APSR();
+ ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk);
+
+ Rm = 5;
+ Rn = 7;
+ SUBS(Rm, Rm, Rn);
+ result = __get_xPSR();
+ ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk);
+
+ // Check zero and compare flag
+ Rm = 5;
+ SUBS(Rm, Rm, Rm);
+ result = __get_APSR();
+ ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk);
+ ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
+
+ Rm = 5;
+ SUBS(Rm, Rm, Rm);
+ result = __get_xPSR();
+ ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk);
+ ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
+
+ // Check overflow flag
+ Rm = 5;
+ Rn = INT32_MAX;
+ ADDS(Rm, Rm, Rn);
+ result = __get_APSR();
+ ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk);
+
+ Rm = 5;
+ Rn = INT32_MAX;
+ ADDS(Rm, Rm, Rn);
+ result = __get_xPSR();
+ ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_PSP
+\details
+- Check if __get_PSP and __set_PSP instrinsic can be used to manipulate process stack pointer.
+*/
+void TC_CoreFunc_PSP (void) {
+ // don't use stack for this variables
+ static uint32_t orig;
+ static uint32_t psp;
+ static uint32_t result;
+
+ orig = __get_PSP();
+
+ psp = orig + 0x12345678U;
+ __set_PSP(psp);
+
+ result = __get_PSP();
+
+ __set_PSP(orig);
+
+ ASSERT_TRUE(result == psp);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_MSP
+\details
+- Check if __get_MSP and __set_MSP instrinsic can be used to manipulate process stack pointer.
+*/
+void TC_CoreFunc_MSP (void) {
+ // don't use stack for this variables
+ static uint32_t orig;
+ static uint32_t msp;
+ static uint32_t result;
+ static uint32_t ctrl;
+
+ ctrl = __get_CONTROL();
+ __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP
+
+ orig = __get_MSP();
+
+ msp = orig + 0x12345678U;
+ __set_MSP(msp);
+
+ result = __get_MSP();
+
+ __set_MSP(orig);
+
+ __set_CONTROL(ctrl);
+
+ ASSERT_TRUE(result == msp);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_PRIMASK
+\details
+- Check if __get_PRIMASK and __set_PRIMASK instrinsic can be used to manipulate PRIMASK.
+- Check if __enable_irq and __disable_irq are reflected in PRIMASK.
+*/
+void TC_CoreFunc_PRIMASK (void) {
+ uint32_t orig = __get_PRIMASK();
+
+ // toggle primask
+ uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U);
+
+ __set_PRIMASK(primask);
+ uint32_t result = __get_PRIMASK();
+
+ ASSERT_TRUE(result == primask);
+
+ __disable_irq();
+ result = __get_PRIMASK();
+ ASSERT_TRUE((result & 0x01U) == 1U);
+
+ __enable_irq();
+ result = __get_PRIMASK();
+ ASSERT_TRUE((result & 0x01U) == 0U);
+
+ __disable_irq();
+ result = __get_PRIMASK();
+ ASSERT_TRUE((result & 0x01U) == 1U);
+
+ __set_PRIMASK(orig);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+\brief Test case: TC_CoreFunc_FAULTMASK
+\details
+- Check if __get_FAULTMASK and __set_FAULTMASK instrinsic can be used to manipulate FAULTMASK.
+- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK.
+*/
+void TC_CoreFunc_FAULTMASK (void) {
+ uint32_t orig = __get_FAULTMASK();
+
+ // toggle faultmask
+ uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U);
+
+ __set_FAULTMASK(faultmask);
+ uint32_t result = __get_FAULTMASK();
+
+ ASSERT_TRUE(result == faultmask);
+
+ __disable_fault_irq();
+ result = __get_FAULTMASK();
+ ASSERT_TRUE((result & 0x01U) == 1U);
+
+ __enable_fault_irq();
+ result = __get_FAULTMASK();
+ ASSERT_TRUE((result & 0x01U) == 0U);
+
+ __disable_fault_irq();
+ result = __get_FAULTMASK();
+ ASSERT_TRUE((result & 0x01U) == 1U);
+
+ __set_FAULTMASK(orig);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_BASEPRI
+\details
+- Check if __get_BASEPRI and __set_BASEPRI instrinsic can be used to manipulate BASEPRI.
+- Check if __set_BASEPRI_MAX instrinsic can be used to manipulate BASEPRI.
+*/
+void TC_CoreFunc_BASEPRI(void) {
+ uint32_t orig = __get_BASEPRI();
+
+ uint32_t basepri = ~orig & 0x80U;
+ __set_BASEPRI(basepri);
+ uint32_t result = __get_BASEPRI();
+
+ ASSERT_TRUE(result == basepri);
+
+ __set_BASEPRI(orig);
+
+ __set_BASEPRI_MAX(basepri);
+ result = __get_BASEPRI();
+
+ ASSERT_TRUE(result == basepri);
+}
+#endif
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+\brief Test case: TC_CoreFunc_BASEPRI
+\details
+- Check if __get_FPSCR and __set_FPSCR intrinsics can be used
+*/
+void TC_CoreFunc_FPSCR(void) {
+ uint32_t fpscr = __get_FPSCR();
+ __ISB();
+ __DSB();
+
+ __set_FPSCR(~fpscr);
+ __ISB();
+ __DSB();
+
+ uint32_t result = __get_FPSCR();
+
+ __set_FPSCR(fpscr);
+
+#if (defined (__FPU_USED ) && (__FPU_USED == 1U))
+ ASSERT_TRUE(result != fpscr);
+#endif
+}
+#endif
diff --git a/CMSIS/CoreValidation/Source/CV_CoreInstr.c b/CMSIS/CoreValidation/Source/CV_CoreInstr.c
new file mode 100644
index 0000000..87b0524
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_CoreInstr.c
@@ -0,0 +1,193 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_CoreInstr.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_NOP
+\details
+- Check if __NOP instrinsic is available
+- No real assertion is deployed, just a compile time check.
+*/
+void TC_CoreInstr_NOP (void) {
+ __NOP();
+ ASSERT_TRUE(1U == 1U);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_REV
+\details
+- Check if __REV instrinsic swaps all bytes in a word.
+*/
+void TC_CoreInstr_REV (void) {
+ uint32_t result = __REV(0x47110815U);
+ ASSERT_TRUE(result == 0x15081147U);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_REV16
+\details
+- Check if __REV16 instrinsic swaps the bytes in a halfword.
+*/
+void TC_CoreInstr_REV16(void) {
+ uint16_t result = __REV16(0x4711U);
+ ASSERT_TRUE(result == 0x1147U);
+
+ result = __REV16(0x4711U);
+ ASSERT_TRUE(result == 0x1147U);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_REVSH
+\details
+- Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign.
+*/
+void TC_CoreInstr_REVSH(void) {
+ int16_t result = __REVSH(0x4711);
+ ASSERT_TRUE(result == 0x1147);
+
+ result = __REVSH(-4711);
+ ASSERT_TRUE(result == -26131);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_ROT
+\details
+- Check if __ROR instrinsic moves all bits as expected.
+*/
+void TC_CoreInstr_ROR(void) {
+ uint32_t result = __ROR(0x01U, 1U);
+ ASSERT_TRUE(result == 0x80000000U);
+
+ result = __ROR(0x80000000U, 1U);
+ ASSERT_TRUE(result == 0x40000000U);
+
+ result = __ROR(0x40000000U, 30U);
+ ASSERT_TRUE(result == 0x00000001U);
+
+ result = __ROR(0x01U, 32U);
+ ASSERT_TRUE(result == 0x00000001U);
+
+ result = __ROR(0x08154711U, 8U);
+ ASSERT_TRUE(result == 0x11081547U);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_RBIT
+\details
+- Check if __RBIT instrinsic revserses the bit order of arbitrary words.
+*/
+void TC_CoreInstr_RBIT (void) {
+ uint32_t result = __RBIT(0xAAAAAAAAU);
+ ASSERT_TRUE(result == 0x55555555U);
+
+ result = __RBIT(0x55555555U);
+ ASSERT_TRUE(result == 0xAAAAAAAAU);
+
+ result = __RBIT(0x00000001U);
+ ASSERT_TRUE(result == 0x80000000U);
+
+ result = __RBIT(0x80000000U);
+ ASSERT_TRUE(result == 0x00000001U);
+
+ result = __RBIT(0xDEADBEEFU);
+ ASSERT_TRUE(result == 0xF77DB57BU);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_CLZ
+\details
+- Check if __CLZ instrinsic counts leading zeros.
+*/
+
+void TC_CoreInstr_CLZ (void) {
+ int32_t result = __CLZ(0x00U);
+ ASSERT_TRUE(result == 32);
+
+ result = __CLZ(0x00000001U);
+ ASSERT_TRUE(result == 31);
+
+ result = __CLZ(0x40000000U);
+ ASSERT_TRUE(result == 1);
+
+ result = __CLZ(0x80000000U);
+ ASSERT_TRUE(result == 0);
+
+ result = __CLZ(0xFFFFFFFFU);
+ ASSERT_TRUE(result == 0);
+
+ result = __CLZ(0x80000001U);
+ ASSERT_TRUE(result == 0);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_SSAT
+\details
+- Check if __SSAT instrinsic saturates signed integer values.
+*/
+void TC_CoreInstr_SSAT (void) {
+ int32_t result = __SSAT(INT32_MAX, 32U);
+ ASSERT_TRUE(result == INT32_MAX);
+
+ result = __SSAT(INT32_MAX, 16U);
+ ASSERT_TRUE(result == INT16_MAX);
+
+ result = __SSAT(INT32_MAX, 8U);
+ ASSERT_TRUE(result == INT8_MAX);
+
+ result = __SSAT(INT32_MAX, 1U);
+ ASSERT_TRUE(result == 0);
+
+ result = __SSAT(INT32_MIN, 32U);
+ ASSERT_TRUE(result == INT32_MIN);
+
+ result = __SSAT(INT32_MIN, 16U);
+ ASSERT_TRUE(result == INT16_MIN);
+
+ result = __SSAT(INT32_MIN, 8U);
+ ASSERT_TRUE(result == INT8_MIN);
+
+ result = __SSAT(INT32_MIN, 1U);
+ ASSERT_TRUE(result == -1);
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreInstr_USAT
+\details
+- Check if __USAT instrinsic saturates unsigned integer values.
+*/
+void TC_CoreInstr_USAT (void) {
+ uint32_t result = __USAT(UINT32_MAX, 31U);
+ ASSERT_TRUE(result == (UINT32_MAX>>1U));
+
+ result = __USAT(UINT32_MAX, 16U);
+ ASSERT_TRUE(result == UINT16_MAX);
+
+ result = __USAT(UINT32_MAX, 8U);
+ ASSERT_TRUE(result == UINT8_MAX);
+
+ result = __USAT(UINT32_MAX, 0U);
+ ASSERT_TRUE(result == 0U);
+}
diff --git a/CMSIS/CoreValidation/Source/CV_Framework.c b/CMSIS/CoreValidation/Source/CV_Framework.c
new file mode 100644
index 0000000..d49e812
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_Framework.c
@@ -0,0 +1,99 @@
+/*-----------------------------------------------------------------------------
+ * Name: cv_framework.c
+ * Purpose: Test framework entry point
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/* Prototypes */
+void ts_cmsis_cv(void);
+void closeDebug(void);
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\defgroup framework_funcs Framework Functions
+\brief Functions in the Framework software component
+\details
+
+@{
+*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Close the debug session.
+\details
+Debug session dead end - debug script should close session here.
+*/
+void closeDebug(void) {
+ __NOP();
+ // Test completed
+}
+
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+
+/**
+\brief This is CORE Validation test suite.
+\details
+Program flow:
+ -# Test report statistics is initialized
+ -# Test report headers are written to the standard output
+ -# All defined test cases are executed:
+ - Test case statistics is initialized
+ - Test case report header is written to the standard output
+ - Test case is executed
+ - Test case results are written to the standard output
+ - Test case report footer is written to the standard output
+ - Test case is closed
+ -# Test report footer is written to the standard output
+ -# Debug session ends in dead loop
+*/
+void ts_cmsis_cv () {
+ const char *fn;
+ uint32_t tc, no;
+
+ (void)ritf.Init (); /* Init test report */
+ (void)ritf.Open (ts.ReportTitle, /* Write test report title */
+ ts.Date, /* Write compilation date */
+ ts.Time, /* Write compilation time */
+ ts.FileName); /* Write module file name */
+
+ /* Execute all test cases */
+ for (tc = 0; tc < ts.NumOfTC; tc++) {
+ no = ts.TCBaseNum+tc; /* Test case number */
+ fn = ts.TC[tc].TFName; /* Test function name string */
+ (void)ritf.Open_TC (no, fn); /* Open test case #(Base + TC) */
+ if (ts.TC[tc].en != 0U) {
+ ts.TC[tc].TestFunc(); /* Execute test case if enabled */
+ }
+ (void)ritf.Close_TC (); /* Close test case */
+ }
+ (void)ritf.Close (); /* Close test report */
+
+ closeDebug(); /* Close debug session */
+}
+
+/**
+\brief This is the entry point of the test framework.
+\details
+Program flow:
+ -# Hardware is first initialized if Init callback function is provided
+ -# Main thread is initialized
+*/
+void cmsis_cv (void) {
+
+ /* Init test suite */
+ if (ts.Init != NULL) {
+ ts.Init(); /* Init hardware */
+ }
+
+ ts_cmsis_cv();
+}
+
+
+/**
+@}
+*/
+// end of group framework_funcs
diff --git a/CMSIS/CoreValidation/Source/CV_GenTimer.c b/CMSIS/CoreValidation/Source/CV_GenTimer.c
new file mode 100644
index 0000000..b62394a
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_GenTimer.c
@@ -0,0 +1,42 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_GenTimer.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_GenTimer_CNTFRQ(void) {
+ uint32_t cntfrq = __get_CNTFRQ();
+ __set_CNTFRQ(cntfrq);
+
+ ASSERT_TRUE(cntfrq == __get_CNTFRQ());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_GenTimer_CNTP_TVAL(void) {
+ uint32_t cntp_tval = __get_CNTP_TVAL();
+ __set_CNTP_TVAL(cntp_tval);
+
+ ASSERT_TRUE(cntp_tval >= __get_CNTP_TVAL());
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+void TC_GenTimer_CNTP_CTL(void) {
+ uint32_t cntp_ctl = __get_CNTP_CTL();
+ __set_CNTP_CTL(cntp_ctl);
+
+ ASSERT_TRUE(cntp_ctl == __get_CNTP_CTL());
+}
diff --git a/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c b/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c
new file mode 100644
index 0000000..2a66dfc
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c
@@ -0,0 +1,118 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_MPU_ARMv7.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT != 0)
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+static void ClearMpu(void) {
+ for(uint32_t i = 0U; i < 8U; ++i) {
+ MPU->RNR = i;
+ MPU->RBAR = 0U;
+ MPU->RASR = 0U;
+ }
+}
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_MPU_SetClear
+\details
+- Check if ARM_MPU_Load correctly loads MPU table to registers.
+*/
+void TC_MPU_SetClear(void)
+{
+ static const ARM_MPU_Region_t table[] = {
+ { .RBAR = 0U, .RASR = 0U },
+ { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
+ { .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }
+ };
+
+ #define ASSERT_MPU_REGION(rnr, region) \
+ MPU->RNR = rnr; \
+ ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \
+ ASSERT_TRUE(MPU->RASR == region.RASR)
+
+ ClearMpu();
+
+ ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR);
+
+ ASSERT_MPU_REGION(1U, table[0]);
+ ASSERT_MPU_REGION(2U, table[1]);
+ ASSERT_MPU_REGION(3U, table[0]);
+
+ ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR);
+
+ ASSERT_MPU_REGION(4U, table[0]);
+ ASSERT_MPU_REGION(5U, table[2]);
+ ASSERT_MPU_REGION(6U, table[0]);
+
+ ARM_MPU_ClrRegion(5U);
+
+ MPU->RNR = 5U;
+ ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U);
+
+ #undef ASSERT_MPU_REGION
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_MPU_Load
+\details
+- Check if ARM_MPU_Load correctly loads MPU table to registers.
+*/
+void TC_MPU_Load(void)
+{
+ static const ARM_MPU_Region_t table[] = {
+ { .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) },
+ { .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) },
+ { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
+ { .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) },
+ { .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) },
+ { .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB) },
+ { .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB) },
+ { .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB) }
+ };
+
+ #define ASSERT_MPU_REGION(rnr, table) \
+ MPU->RNR = rnr; \
+ ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \
+ ASSERT_TRUE(MPU->RASR == table[rnr].RASR)
+
+ ClearMpu();
+
+ ARM_MPU_Load(&(table[0]), 1U);
+
+ ASSERT_MPU_REGION(0U, table);
+
+ ARM_MPU_Load(&(table[1]), 5U);
+
+ ASSERT_MPU_REGION(0U, table);
+ ASSERT_MPU_REGION(1U, table);
+ ASSERT_MPU_REGION(2U, table);
+ ASSERT_MPU_REGION(3U, table);
+ ASSERT_MPU_REGION(4U, table);
+ ASSERT_MPU_REGION(5U, table);
+
+ ARM_MPU_Load(&(table[6]), 2U);
+
+ ASSERT_MPU_REGION(5U, table);
+ ASSERT_MPU_REGION(6U, table);
+ ASSERT_MPU_REGION(7U, table);
+
+ #undef ASSERT_MPU_REGION
+}
+
+#endif
diff --git a/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c b/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c
new file mode 100644
index 0000000..36f432d
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c
@@ -0,0 +1,107 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_MPU_ARMv7.c
+ * Purpose: CMSIS CORE validation tests implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "CV_Framework.h"
+#include "cmsis_cv.h"
+
+/*-----------------------------------------------------------------------------
+ * Test implementation
+ *----------------------------------------------------------------------------*/
+
+static void ClearMpu() {
+ for(uint32_t i = 0U; i < 8U; ++i) {
+ MPU->RNR = i;
+ MPU->RBAR = 0U;
+ MPU->RLAR = 0U;
+ }
+}
+
+/*-----------------------------------------------------------------------------
+ * Test cases
+ *----------------------------------------------------------------------------*/
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_MPU_SetClear
+\details
+- Check if ARM_MPU_Load correctly loads MPU table to registers.
+*/
+void TC_MPU_SetClear(void)
+{
+ static const ARM_MPU_Region_t table[] = {
+ { .RBAR = 0U, .RLAR = 0U },
+ { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) }
+ };
+
+ #define ASSERT_MPU_REGION(rnr, region) \
+ MPU->RNR = rnr; \
+ ASSERT_TRUE(MPU->RBAR == region.RBAR); \
+ ASSERT_TRUE(MPU->RLAR == region.RLAR)
+
+ ClearMpu();
+
+ ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR);
+
+ ASSERT_MPU_REGION(1U, table[0]);
+ ASSERT_MPU_REGION(2U, table[1]);
+ ASSERT_MPU_REGION(3U, table[0]);
+
+ ARM_MPU_ClrRegion(2U);
+
+ MPU->RNR = 2U;
+ ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U);
+
+ #undef ASSERT_MPU_REGION
+}
+
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_MPU_Load
+\details
+- Check if ARM_MPU_Load correctly loads MPU table to registers.
+*/
+void TC_MPU_Load(void)
+{
+ static const ARM_MPU_Region_t table[] = {
+ { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) },
+ { .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) }
+ };
+
+ #define ASSERT_MPU_REGION(rnr, table) \
+ MPU->RNR = rnr; \
+ ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \
+ ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR)
+
+ ClearMpu();
+
+ ARM_MPU_Load(0U, &(table[0]), 1U);
+
+ ASSERT_MPU_REGION(0U, table);
+
+ ARM_MPU_Load(1U, &(table[1]), 5U);
+
+ ASSERT_MPU_REGION(0U, table);
+ ASSERT_MPU_REGION(1U, table);
+ ASSERT_MPU_REGION(2U, table);
+ ASSERT_MPU_REGION(3U, table);
+ ASSERT_MPU_REGION(4U, table);
+ ASSERT_MPU_REGION(5U, table);
+
+ ARM_MPU_Load(6U, &(table[6]), 2U);
+
+ ASSERT_MPU_REGION(5U, table);
+ ASSERT_MPU_REGION(6U, table);
+ ASSERT_MPU_REGION(7U, table);
+
+ #undef ASSERT_MPU_REGION
+}
diff --git a/CMSIS/CoreValidation/Source/CV_Report.c b/CMSIS/CoreValidation/Source/CV_Report.c
new file mode 100644
index 0000000..907ec13
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/CV_Report.c
@@ -0,0 +1,393 @@
+/*-----------------------------------------------------------------------------
+ * Name: cv_report.c
+ * Purpose: Report statistics and layout implementation
+ *-----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#include "CV_Report.h"
+#include <stdio.h>
+#include <string.h>
+
+TEST_REPORT test_report;
+static AS_STAT current_assertions; /* Current test case assertions statistics */
+#define TAS (&test_report.assertions) /* Total assertions */
+#define CAS (¤t_assertions) /* Current assertions */
+
+#ifdef DISABLE_SEMIHOSTING
+#if defined (__CC_ARM)
+ #pragma import __use_no_semihosting
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ __ASM(".global __use_no_semihosting");
+#endif
+#define PRINT(x)
+#define FLUSH()
+void _sys_exit(int return_code) {}
+#else
+#define PRINT(x) MsgPrint x
+#define FLUSH() MsgFlush()
+#endif // DISABLE_SEMIHOSTING
+
+static uint8_t Passed[] = "PASSED";
+static uint8_t Warning[] = "WARNING";
+static uint8_t Failed[] = "FAILED";
+static uint8_t NotExe[] = "NOT EXECUTED";
+
+
+/*-----------------------------------------------------------------------------
+ * Test report function prototypes
+ *----------------------------------------------------------------------------*/
+static BOOL tr_Init (void);
+static BOOL tc_Init (void);
+static uint8_t *tr_Eval (void);
+static uint8_t *tc_Eval (void);
+static BOOL StatCount (TC_RES res);
+
+/*-----------------------------------------------------------------------------
+ * Printer function prototypes
+ *----------------------------------------------------------------------------*/
+static void MsgPrint (const char *msg, ...);
+static void MsgFlush (void);
+
+
+/*-----------------------------------------------------------------------------
+ * Assert interface function prototypes
+ *----------------------------------------------------------------------------*/
+static BOOL As_File_Result (TC_RES res);
+static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc);
+
+TC_ITF tcitf = {
+ As_File_Result,
+ As_File_Dbgi,
+};
+
+
+/*-----------------------------------------------------------------------------
+ * Test report interface function prototypes
+ *----------------------------------------------------------------------------*/
+BOOL tr_File_Init (void);
+BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn);
+BOOL tr_File_Close (void);
+BOOL tc_File_Open (uint32_t num, const char *fn);
+BOOL tc_File_Close (void);
+
+REPORT_ITF ritf = {
+ tr_File_Init,
+ tr_File_Open,
+ tr_File_Close,
+ tc_File_Open,
+ tc_File_Close
+};
+
+
+/*-----------------------------------------------------------------------------
+ * Init test report
+ *----------------------------------------------------------------------------*/
+BOOL tr_File_Init (void) {
+ return (tr_Init());
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Open test report
+ *----------------------------------------------------------------------------*/
+#if (PRINT_XML_REPORT==1)
+BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) {
+ PRINT(("<?xml version=\"1.0\"?>\n"));
+ PRINT(("<?xml-stylesheet href=\"TR_Style.xsl\" type=\"text/xsl\" ?>\n"));
+ PRINT(("<report>\n"));
+ PRINT(("<test>\n"));
+ PRINT(("<title>%s</title>\n", title));
+ PRINT(("<date>%s</date>\n", date));
+ PRINT(("<time>%s</time>\n", time));
+ PRINT(("<file>%s</file>\n", fn));
+ PRINT(("<test_cases>\n"));
+#else
+BOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) {
+ PRINT(("%s %s %s \n\n", title, date, time));
+#endif
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Open test case
+ *----------------------------------------------------------------------------*/
+BOOL tc_File_Open (uint32_t num, const char *fn) {
+ (void)tc_Init ();
+#if (PRINT_XML_REPORT==1)
+ PRINT(("<tc>\n"));
+ PRINT(("<no>%d</no>\n", num));
+ PRINT(("<func>%s</func>\n", fn));
+ PRINT(("<req></req>"));
+ PRINT(("<meth></meth>"));
+ PRINT(("<dbgi>\n"));
+#else
+ PRINT(("TEST %02d: %-32s ", num, fn));
+#endif
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Close test case
+ *----------------------------------------------------------------------------*/
+BOOL tc_File_Close (void) {
+ uint8_t *res = tc_Eval();
+#if (PRINT_XML_REPORT==1)
+ PRINT(("</dbgi>\n"));
+ PRINT(("<res>%s</res>\n", res));
+ PRINT(("</tc>\n"));
+#else
+ if ((res==Passed)||(res==NotExe)) {
+ PRINT(("%s\n", res));
+ } else {
+ PRINT(("\n"));
+ }
+#endif
+ FLUSH();
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Close test report
+ *----------------------------------------------------------------------------*/
+BOOL tr_File_Close (void) {
+#if (PRINT_XML_REPORT==1)
+ PRINT(("</test_cases>\n"));
+ PRINT(("<summary>\n"));
+ PRINT(("<tcnt>%d</tcnt>\n", test_report.tests));
+ PRINT(("<exec>%d</exec>\n", test_report.executed));
+ PRINT(("<pass>%d</pass>\n", test_report.passed));
+ PRINT(("<fail>%d</fail>\n", test_report.failed));
+ PRINT(("<warn>%d</warn>\n", test_report.warnings));
+ PRINT(("<tres>%s</tres>\n", tr_Eval()));
+ PRINT(("</summary>\n"));
+ PRINT(("</test>\n"));
+ PRINT(("</report>\n"));
+#else
+ PRINT(("\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\n",
+ test_report.tests,
+ test_report.executed,
+ test_report.passed,
+ test_report.failed,
+ test_report.warnings));
+ PRINT(("Test Result: %s\n", tr_Eval()));
+#endif
+ FLUSH();
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Assertion result counter
+ *----------------------------------------------------------------------------*/
+static BOOL As_File_Result (TC_RES res) {
+ return (StatCount (res));
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Set debug information state
+ *----------------------------------------------------------------------------*/
+#if (PRINT_XML_REPORT==1)
+static BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) {
+ PRINT(("<detail>\n"));
+ if (desc!=NULL) PRINT(("<desc>%s</desc>\n", desc));
+ PRINT(("<module>%s</module>\n", fn));
+ PRINT(("<line>%d</line>\n", ln));
+ PRINT(("</detail>\n"));
+#else
+static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) {
+ PRINT(("\n %s (%d)", fn, ln));
+ if (res==WARNING){ PRINT((" [WARNING]")); }
+ if (res==FAILED) { PRINT((" [FAILED]")); }
+ if (desc!=NULL) { PRINT((" %s", desc)); }
+#endif
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Init test report
+ *----------------------------------------------------------------------------*/
+static BOOL tr_Init (void) {
+ TAS->passed = 0;
+ TAS->failed = 0;
+ TAS->warnings = 0;
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Init test case
+ *----------------------------------------------------------------------------*/
+static BOOL tc_Init (void) {
+ CAS->passed = 0;
+ CAS->failed = 0;
+ CAS->warnings = 0;
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Evaluate test report results
+ *----------------------------------------------------------------------------*/
+static uint8_t *tr_Eval (void) {
+ if (test_report.failed > 0U) {
+ /* Test fails if any test case failed */
+ return (Failed);
+ }
+ else if (test_report.warnings > 0U) {
+ /* Test warns if any test case warnings */
+ return (Warning);
+ }
+ else if (test_report.passed > 0U) {
+ /* Test passes if at least one test case passed */
+ return (Passed);
+ }
+ else {
+ /* No test cases were executed */
+ return (NotExe);
+ }
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Evaluate test case results
+ *----------------------------------------------------------------------------*/
+static uint8_t *tc_Eval (void) {
+ test_report.tests++;
+ test_report.executed++;
+
+ if (CAS->failed > 0U) {
+ /* Test case fails if any failed assertion recorded */
+ test_report.failed++;
+ return Failed;
+ }
+ else if (CAS->warnings > 0U) {
+ /* Test case warns if any warnings assertion recorded */
+ test_report.warnings++;
+ return Warning;
+ }
+ else if (CAS->passed > 0U) {
+ /* Test case passes if at least one assertion passed */
+ test_report.passed++;
+ return Passed;
+ }
+ else {
+ /* Assert was not invoked - nothing to evaluate */
+ test_report.executed--;
+ return NotExe;
+ }
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Statistics result counter
+ *----------------------------------------------------------------------------*/
+static BOOL StatCount (TC_RES res) {
+ switch (res) {
+ case PASSED:
+ CAS->passed++;
+ TAS->passed++;
+ break;
+
+ case WARNING:
+ CAS->warnings++;
+ TAS->warnings++;
+ break;
+
+ case FAILED:
+ CAS->failed++;
+ TAS->failed++;
+ break;
+
+ case NOT_EXECUTED:
+ return (__FALSE);
+
+ default:
+ break;
+ }
+ return (__TRUE);
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Set result
+ *----------------------------------------------------------------------------*/
+TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) {
+
+ // save assertion result
+ switch (res) {
+ case PASSED:
+ if (TAS->passed < BUFFER_ASSERTIONS) {
+ test_report.assertions.info.passed[TAS->passed].module = fn;
+ test_report.assertions.info.passed[TAS->passed].line = ln;
+ }
+ break;
+ case FAILED:
+ if (TAS->failed < BUFFER_ASSERTIONS) {
+ test_report.assertions.info.failed[TAS->failed].module = fn;
+ test_report.assertions.info.failed[TAS->failed].line = ln;
+ }
+ break;
+ case WARNING:
+ if (TAS->warnings < BUFFER_ASSERTIONS) {
+ test_report.assertions.info.warnings[TAS->warnings].module = fn;
+ test_report.assertions.info.warnings[TAS->warnings].line = ln;
+ }
+ break;
+ case NOT_EXECUTED:
+ break;
+
+ default:
+ break;
+ }
+
+ // set debug info (if the test case didn't pass)
+ if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); }
+ // set result
+ (void)tcitf.Result (res);
+ return (res);
+}
+
+/*-----------------------------------------------------------------------------
+ * Assert true
+ *----------------------------------------------------------------------------*/
+TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) {
+ TC_RES res = FAILED;
+ if (cond != 0U) { res = PASSED; }
+ (void)__set_result(fn, ln, res, NULL);
+ return (res);
+}
+
+#ifndef DISABLE_SEMIHOSTING
+/*-----------------------------------------------------------------------------
+ * MsgFlush: Flush the standard output
+ *----------------------------------------------------------------------------*/
+static void MsgFlush(void) {
+ (void)fflush(stdout);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wformat-nonliteral"
+#endif
+/*-----------------------------------------------------------------------------
+ * MsgPrint: Print a message to the standard output
+ *----------------------------------------------------------------------------*/
+static void MsgPrint (const char *msg, ...) {
+ va_list args;
+ va_start(args, msg);
+ vprintf(msg, args);
+ va_end(args);
+}
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic pop
+#endif
+#endif // DISABLE_SEMIHOSTING
+
+/*-----------------------------------------------------------------------------
+ * End of file
+ *----------------------------------------------------------------------------*/
diff --git a/CMSIS/CoreValidation/Source/Config/CV_Config.h b/CMSIS/CoreValidation/Source/Config/CV_Config.h
new file mode 100644
index 0000000..2d8557b
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/Config/CV_Config.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREFUNC_ENDISIRQ_EN 1
+#define TC_COREFUNC_CONTROL_EN 1
+#define TC_COREFUNC_IPSR_EN 1
+#define TC_COREFUNC_APSR_EN 1
+#define TC_COREFUNC_PSP_EN 1
+#define TC_COREFUNC_MSP_EN 1
+#define TC_COREFUNC_PRIMASK_EN 1
+#define TC_COREFUNC_FAULTMASK_EN 1
+#define TC_COREFUNC_BASEPRI_EN 1
+#define TC_COREFUNC_FPSCR_EN 1
+
+#define TC_MPU_SETCLEAR_EN 1
+#define TC_MPU_LOAD_EN 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Source/Config/SaveXML.ini b/CMSIS/CoreValidation/Source/Config/SaveXML.ini
new file mode 100644
index 0000000..3b11517
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/Config/SaveXML.ini
@@ -0,0 +1,16 @@
+/*-----------------------------------------------------------------------------
+ * Name: SaveXML.ini
+ * Purpose: Default debug initialization script
+ *----------------------------------------------------------------------------
+ * Copyright(c) KEIL - An ARM Company
+ *----------------------------------------------------------------------------*/
+
+// Target initialization
+include Simulator.ini
+
+// Save test results
+G, tr_File_Open
+SLOG > TestReport\TestReport.xml
+G, closeDebug
+SLOG OFF
+EXIT
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Source/Config/Simulator.ini b/CMSIS/CoreValidation/Source/Config/Simulator.ini
new file mode 100644
index 0000000..085e450
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/Config/Simulator.ini
@@ -0,0 +1,12 @@
+/*-----------------------------------------------------------------------------
+ * Name: Simulator.ini
+ * Purpose: Set simulator debug functions and breakpoints
+ *----------------------------------------------------------------------------
+ * Copyright(c) KEIL - An ARM Company
+ *----------------------------------------------------------------------------*/
+
+FUNC void GetStates (void) {
+ SIM_CYCCNT=states;
+}
+
+BS GET_SIM_CYCCNT,1,"GetStates()"
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h b/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h
new file mode 100644
index 0000000..37d7fc8
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ * Name: CV_Config.h
+ * Purpose: CV Config header
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT 0
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS 128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN 1
+#define TC_COREINSTR_REV_EN 1
+#define TC_COREINSTR_REV16_EN 1
+#define TC_COREINSTR_REVSH_EN 1
+#define TC_COREINSTR_ROR_EN 1
+#define TC_COREINSTR_RBIT_EN 1
+#define TC_COREINSTR_CLZ_EN 1
+#define TC_COREINSTR_SSAT_EN 1
+#define TC_COREINSTR_USAT_EN 1
+
+#define TC_COREAFUNC_IRQ 1
+#define TC_COREAFUNC_FPSCR 1
+#define TC_COREAFUNC_CPSR 1
+#define TC_COREAFUNC_MODE 1
+#define TC_COREAFUNC_SP 1
+#define TC_COREAFUNC_SP_USR 1
+#define TC_COREAFUNC_FPEXC 1
+#define TC_COREAFUNC_ACTLR 1
+#define TC_COREAFUNC_CPACR 1
+#define TC_COREAFUNC_DFSR 1
+#define TC_COREAFUNC_IFSR 1
+#define TC_COREAFUNC_ISR 1
+#define TC_COREAFUNC_CBAR 1
+#define TC_COREAFUNC_TTBR0 1
+#define TC_COREAFUNC_DACR 1
+#define TC_COREAFUNC_SCTLR 1
+#define TC_COREAFUNC_ACTRL 1
+#define TC_COREAFUNC_MPIDR 1
+#define TC_COREAFUNC_VBAR 1
+
+#define TC_GENTIMER_CNTFRQ 1
+#define TC_GENTIMER_CNTP_TVAL 1
+#define TC_GENTIMER_CNTP_CTL 1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+
diff --git a/CMSIS/CoreValidation/Source/cmsis_cv.c b/CMSIS/CoreValidation/Source/cmsis_cv.c
new file mode 100644
index 0000000..68e40a3
--- /dev/null
+++ b/CMSIS/CoreValidation/Source/cmsis_cv.c
@@ -0,0 +1,131 @@
+/*-----------------------------------------------------------------------------
+ * Name: cmsis_cv.c
+ * Purpose: Driver validation test cases entry point
+ *----------------------------------------------------------------------------
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#include "cmsis_cv.h"
+#include "RTE_Components.h"
+#include "CV_Framework.h"
+#include "CV_Config.h"
+
+/*-----------------------------------------------------------------------------
+ * Prototypes
+ *----------------------------------------------------------------------------*/
+
+void WDT_IRQHandler(void);
+
+/*-----------------------------------------------------------------------------
+ * Variables declarations
+ *----------------------------------------------------------------------------*/
+
+void (*TST_IRQHandler)(void);
+
+void WDT_IRQHandler(void) {
+ if (TST_IRQHandler != NULL) TST_IRQHandler();
+}
+
+/*-----------------------------------------------------------------------------
+ * Init test suite
+ *----------------------------------------------------------------------------*/
+static void TS_Init (void) {
+ TST_IRQHandler = NULL;
+
+#ifdef RTE_CV_MEASURETICKS
+ StartCortexCycleCounter();
+#endif
+}
+
+/*-----------------------------------------------------------------------------
+ * Test cases list
+ *----------------------------------------------------------------------------*/
+static TEST_CASE TC_LIST[] = {
+#ifdef RTE_CV_COREINSTR
+ TCD ( TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ),
+ TCD ( TC_CoreInstr_REV, TC_COREINSTR_REV_EN ),
+ TCD ( TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ),
+ TCD ( TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ),
+ TCD ( TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ),
+ TCD ( TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ),
+ TCD ( TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ),
+ TCD ( TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ),
+ TCD ( TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ),
+#endif
+#ifdef RTE_CV_COREFUNC
+ #if defined(__CORTEX_M)
+ TCD ( TC_CoreFunc_EnDisIRQ, TC_COREFUNC_ENDISIRQ_EN ),
+ TCD ( TC_CoreFunc_Control, TC_COREFUNC_CONTROL_EN ),
+ TCD ( TC_CoreFunc_IPSR, TC_COREFUNC_IPSR_EN ),
+ TCD ( TC_CoreFunc_APSR, TC_COREFUNC_APSR_EN ),
+ TCD ( TC_CoreFunc_PSP, TC_COREFUNC_PSP_EN ),
+ TCD ( TC_CoreFunc_MSP, TC_COREFUNC_MSP_EN ),
+ TCD ( TC_CoreFunc_PRIMASK, TC_COREFUNC_PRIMASK_EN ),
+
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+ TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ),
+ TCD ( TC_CoreFunc_BASEPRI, TC_COREFUNC_BASEPRI_EN ),
+
+ #endif
+
+ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+ TCD ( TC_CoreFunc_FPSCR, TC_COREFUNC_FPSCR_EN ),
+
+ #endif
+ #elif defined(__CORTEX_A)
+ TCD ( TC_CoreAFunc_IRQ, TC_COREAFUNC_IRQ ),
+ TCD ( TC_CoreAFunc_FPSCR, TC_COREAFUNC_FPSCR ),
+ TCD ( TC_CoreAFunc_CPSR, TC_COREAFUNC_CPSR ),
+ TCD ( TC_CoreAFunc_Mode, TC_COREAFUNC_MODE ),
+ TCD ( TC_CoreAFunc_SP, TC_COREAFUNC_SP ),
+ TCD ( TC_CoreAFunc_SP_usr, TC_COREAFUNC_SP_USR ),
+ TCD ( TC_CoreAFunc_FPEXC, TC_COREAFUNC_FPEXC ),
+ TCD ( TC_CoreAFunc_ACTLR, TC_COREAFUNC_ACTLR ),
+ TCD ( TC_CoreAFunc_CPACR, TC_COREAFUNC_CPACR ),
+ TCD ( TC_CoreAFunc_DFSR, TC_COREAFUNC_DFSR ),
+ TCD ( TC_CoreAFunc_IFSR, TC_COREAFUNC_IFSR ),
+ TCD ( TC_CoreAFunc_ISR, TC_COREAFUNC_ISR ),
+ TCD ( TC_CoreAFunc_CBAR, TC_COREAFUNC_CBAR ),
+ TCD ( TC_CoreAFunc_TTBR0, TC_COREAFUNC_TTBR0 ),
+ TCD ( TC_CoreAFunc_DACR, TC_COREAFUNC_DACR ),
+ TCD ( TC_CoreAFunc_SCTLR, TC_COREAFUNC_SCTLR ),
+ TCD ( TC_CoreAFunc_ACTRL, TC_COREAFUNC_ACTRL ),
+ TCD ( TC_CoreAFunc_MPIDR, TC_COREAFUNC_MPIDR ),
+ TCD ( TC_CoreAFunc_VBAR, TC_COREAFUNC_VBAR ),
+ #endif
+#endif
+#ifdef RTE_CV_MPUFUNC
+#if defined(__MPU_PRESENT) && __MPU_PRESENT
+ TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ),
+ TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ),
+#endif
+#endif
+#ifdef RTE_CV_GENTIMER
+ TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ),
+ TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ),
+ TCD ( TC_GenTimer_CNTP_CTL, TC_GENTIMER_CNTP_CTL ),
+#endif
+};
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wdate-time"
+#endif
+/*-----------------------------------------------------------------------------
+ * Test suite description
+ *----------------------------------------------------------------------------*/
+TEST_SUITE ts = {
+ __FILE__, __DATE__, __TIME__,
+ "CMSIS-CORE Test Suite",
+ TS_Init,
+ 1,
+ TC_LIST,
+ ARRAY_SIZE (TC_LIST),
+};
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic pop
+#endif
diff --git a/CMSIS/CoreValidation/gen_pack.bat b/CMSIS/CoreValidation/gen_pack.bat
new file mode 100644
index 0000000..20130f9
--- /dev/null
+++ b/CMSIS/CoreValidation/gen_pack.bat
@@ -0,0 +1,81 @@
+:: Batch file for generating CMSIS pack
+:: This batch file uses:
+:: 7-Zip for packaging
+:: Doxygen version 1.8.2 and Mscgen version 0.20 for generating html documentation.
+:: The generated pack and pdsc file are placed in folder %RELEASE_PATH% (../../Local_Release)
+@ECHO off
+
+SETLOCAL
+
+:: Tool path for zipping tool 7-Zip
+SET ZIPPATH=C:\Program Files\7-Zip
+
+:: Tool path for doxygen
+SET DOXYGENPATH=C:\Program Files\doxygen\bin
+
+:: Tool path for mscgen utility
+SET MSCGENPATH=C:\Program Files (x86)\Mscgen
+
+:: These settings should be passed on to subprocesses as well
+SET PATH=%ZIPPATH%;%DOXYGENPATH%;%MSCGENPATH%;%PATH%
+
+:: Pack Path (where generated pack is stored)
+SET RELEASE_PATH=..\..\Local_Release
+
+:: !!!!!!!!!!!!!!!!!
+:: DO NOT EDIT BELOW
+:: !!!!!!!!!!!!!!!!!
+
+:: Remove previous build
+IF EXIST %RELEASE_PATH% (
+ ECHO removing %RELEASE_PATH%
+ RMDIR /Q /S %RELEASE_PATH%
+)
+
+:: Create build output directory
+MKDIR %RELEASE_PATH%
+
+
+:: Copy PDSC file
+COPY ARM.CMSIS-Core_Validation.pdsc %RELEASE_PATH%\ARM.CMSIS-Core_Validation.pdsc
+
+:: Copy LICENSE file
+COPY ..\..\LICENSE.txt %RELEASE_PATH%\LICENSE.txt
+
+:: Copy folders
+XCOPY /Q /S /Y Examples\*.* %RELEASE_PATH%\Examples\*.*
+XCOPY /Q /S /Y Include\*.* %RELEASE_PATH%\Include\*.*
+XCOPY /Q /S /Y Source\*.* %RELEASE_PATH%\Source\*.*
+
+:: Checking
+..\Utilities\Win32\PackChk.exe %RELEASE_PATH%\ARM.CMSIS-Core_Validation.pdsc -i ..\..\ARM.CMSIS.pdsc -n %RELEASE_PATH%\PackName.txt -x M353 -x M364
+
+:: --Check if PackChk.exe has completed successfully
+IF %errorlevel% neq 0 GOTO ErrPackChk
+
+:: Packing
+PUSHD %RELEASE_PATH%
+
+:: -- Pipe Pack's Name into Variable
+SET /P PackName=<PackName.txt
+DEL /Q PackName.txt
+
+:: Pack files
+ECHO Creating pack file ...
+7z.exe a %PackName% -tzip > zip.log
+ECHO Packaging complete
+POPD
+GOTO End
+
+:ErrPackChk
+ECHO PackChk.exe has encountered an error!
+EXIT /b
+
+:End
+ECHO Removing temporary files and folders
+RMDIR /Q /S %RELEASE_PATH%\CMSIS
+RMDIR /Q /S %RELEASE_PATH%\Device
+DEL %RELEASE_PATH%\LICENSE.txt
+DEL %RELEASE_PATH%\zip.log
+
+ECHO gen_pack.bat completed successfully