commit 4f14f49ff1292a9155151b9ba53a02bba812056e
author Kevin Bracey <kevin.bracey@arm.com> Mon Jan 14 10:03:14 2019 +0200
committer Jonatan Antoni <jonatan.antoni@arm.com> Tue Jul 30 16:57:20 2019 +0200
tree b67a731062cac9266e1cfafa410e855640dc8531
parent ff912334e93b1d129efde7ca5c81741799d73b02

GCC/Clang: cope with __set_CPSR changing condition codes

Add a "cc" clobber to __set_CPSR to reflect the fact that it could be
changing the condition codes.

CMSIS/Core_A/Include/cmsis_armclang.h

diff --git a/CMSIS/Core_A/Include/cmsis_armclang.h b/CMSIS/Core_A/Include/cmsis_armclang.h
index a8a67ba..c9479e4 100644
--- a/CMSIS/Core_A/Include/cmsis_armclang.h
+++ b/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -398,7 +398,7 @@
  */
 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
 {
-__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
 }
 
 /** \brief  Get Mode

CMSIS/Core_A/Include/cmsis_gcc.h

diff --git a/CMSIS/Core_A/Include/cmsis_gcc.h b/CMSIS/Core_A/Include/cmsis_gcc.h
index 1b9194b..3c9bdfb 100644
--- a/CMSIS/Core_A/Include/cmsis_gcc.h
+++ b/CMSIS/Core_A/Include/cmsis_gcc.h
@@ -637,7 +637,7 @@
  */
 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
 {
-__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
 }
 
 /** \brief  Get Mode