Core(A): Fixed __FPU_Enable function not to mess registers. (#589)
- Enhanced function to use only two temporary registers.
- Added used registers to clobber list.
Change-Id: If7c9462ed4424781e40379fbe12a5e4e3257920f
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index e20ea47..bb8ef9a 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,8 +8,12 @@
<url>http://www.keil.com/pack/</url>
<releases>
- <release version="5.5.2-dev2">
+ <release version="5.5.2-dev3">
Active development...
+ CMSIS-Core(A): 1.1.4 (see revision history for details)
+ - Fixed __FPU_Enable.
+ </release>
+ <release version="5.5.2-dev2">
CMSIS-Core(M): 5.3.0 (see revision history for details)
- Added provisions for compiler-independent C startup code.
CMSIS-RTOS:
diff --git a/CMSIS/Core_A/Include/cmsis_armcc.h b/CMSIS/Core_A/Include/cmsis_armcc.h
index 3808744..ec17393 100644
--- a/CMSIS/Core_A/Include/cmsis_armcc.h
+++ b/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.2
- * @date 10. January 2018
+ * @version V1.0.3
+ * @date 15. May 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -536,10 +536,10 @@
ENDIF
//Initialise FPSCR to a known state
- VMRS R2,FPSCR
- LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
- AND R2,R2,R3
- VMSR FPSCR,R2
+ VMRS R1,FPSCR
+ LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R1,R1,R2
+ VMSR FPSCR,R1
BX LR
}
diff --git a/CMSIS/Core_A/Include/cmsis_armclang.h b/CMSIS/Core_A/Include/cmsis_armclang.h
index 38e2fbe..0a53c4e 100644
--- a/CMSIS/Core_A/Include/cmsis_armclang.h
+++ b/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.1.0
- * @date 18. March 2019
+ * @version V1.1.1
+ * @date 15. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -574,10 +574,11 @@
#endif
//Initialise FPSCR to a known state
- " VMRS R2,FPSCR \n"
- " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
- " AND R2,R2,R3 \n"
- " VMSR FPSCR,R2 "
+ " VMRS R1,FPSCR \n"
+ " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R1,R1,R2 \n"
+ " VMSR FPSCR,R1 "
+ : : : "cc", "r1", "r2"
);
}
diff --git a/CMSIS/Core_A/Include/cmsis_gcc.h b/CMSIS/Core_A/Include/cmsis_gcc.h
index cab0cb3..2ab0ca3 100644
--- a/CMSIS/Core_A/Include/cmsis_gcc.h
+++ b/CMSIS/Core_A/Include/cmsis_gcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.1.0
- * @date 20. December 2018
+ * @version V1.1.1
+ * @date 15. May 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -801,10 +801,11 @@
#endif
//Initialise FPSCR to a known state
- " VMRS R2,FPSCR \n"
- " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
- " AND R2,R2,R3 \n"
- " VMSR FPSCR,R2 "
+ " VMRS R1,FPSCR \n"
+ " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R1,R1,R2 \n"
+ " VMSR FPSCR,R1 "
+ : : : "cc", "r1", "r2"
);
}
diff --git a/CMSIS/Core_A/Include/cmsis_iccarm.h b/CMSIS/Core_A/Include/cmsis_iccarm.h
index 64debd5..7d44107 100644
--- a/CMSIS/Core_A/Include/cmsis_iccarm.h
+++ b/CMSIS/Core_A/Include/cmsis_iccarm.h
@@ -2,12 +2,13 @@
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
- * @date 04. Semptember 2018
+ * @date 15. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2018-2019 Arm Limited
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
@@ -551,10 +552,12 @@
#endif
//Initialise FPSCR to a known state
- " VMRS R2,FPSCR \n"
- " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
- " AND R2,R2,R3 \n"
- " VMSR FPSCR,R2 \n");
+ " VMRS R1,FPSCR \n"
+ " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R1,R1,R2 \n"
+ " VMSR FPSCR,R1 \n"
+ : : : "cc", "r1", "r2"
+ );
}
diff --git a/CMSIS/DoxyGen/Core_A/core_A.dxy b/CMSIS/DoxyGen/Core_A/core_A.dxy
index 9189f62..48c3453 100644
--- a/CMSIS/DoxyGen/Core_A/core_A.dxy
+++ b/CMSIS/DoxyGen/Core_A/core_A.dxy
@@ -38,7 +38,7 @@
# could be handy for archiving the generated documentation or if some version
# control system is used.
-PROJECT_NUMBER = "Version 1.1.3"
+PROJECT_NUMBER = "Version 1.1.4"
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
diff --git a/CMSIS/DoxyGen/Core_A/src/Overview.txt b/CMSIS/DoxyGen/Core_A/src/Overview.txt
index 6d6ff61..fbdd942 100644
--- a/CMSIS/DoxyGen/Core_A/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Overview.txt
@@ -67,6 +67,14 @@
<th>Description</th>
</tr>
<tr>
+ <td>V1.1.4</td>
+ <td>
+ <ul>
+ <li>Fixed __FPU_Enable().</li>
+ </ul>
+ </td>
+ </tr>
+ <tr>
<td>V1.1.3</td>
<td>
<ul>