CMSIS-DSP: Added support in test framework for ARMv81MML and FVP
diff --git a/CMSIS/DSP/.gitignore b/CMSIS/DSP/.gitignore
index 81c7c8b..387ded4 100644
--- a/CMSIS/DSP/.gitignore
+++ b/CMSIS/DSP/.gitignore
@@ -1,4 +1,4 @@
DSP_Lib_TestSuite/build/
PythonWrapper/build/
PythonWrapper/cmsisdsp.cp36-win_amd64.pyd
-PythonWrapper/rec_2.dat
\ No newline at end of file
+PythonWrapper/rec_2.dat
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
new file mode 100755
index 0000000..335f001
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
@@ -0,0 +1,132 @@
+/**************************************************************************//**
+ * @file ARMv81MML_DP.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone)
+ * @version V1.0.0
+ * @date 25. February 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMv81MML_DSP_DP_H
+#define ARMv81MML_DSP_DP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* -------------------- Armv8.1-M Mainline Processor Exceptions Numbers --------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ------------------- Processor Interrupt Numbers ------------------------------ */
+ Interrupt0_IRQn = 0,
+ Interrupt1_IRQn = 1,
+ Interrupt2_IRQn = 2,
+ Interrupt3_IRQn = 3,
+ Interrupt4_IRQn = 4,
+ Interrupt5_IRQn = 5,
+ Interrupt6_IRQn = 6,
+ Interrupt7_IRQn = 7,
+ Interrupt8_IRQn = 8,
+ Interrupt9_IRQn = 9
+ /* Interrupts 10 .. 480 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------- Start of section using anonymous unions and disabling warnings ------- */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+/* --- Configuration of the Armv8.1-M Mainline Processor and Core Peripherals --- */
+#define __ARMv81MML_REV 0x0001U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __FPU_DP 1U /* double precision FPU */
+#define __DSP_PRESENT 1U /* DSP extension present */
+#define __MVE_PRESENT 1U /* MVE extensions present */
+#define __MVE_FP 1U /* MVE floating point present */
+
+#include "core_armv81mml.h" /* Processor and core peripherals */
+#include "system_ARMv81MML.h" /* System Header */
+
+
+/* -------- End of section using anonymous unions and disabling warnings -------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMv81MML_DSP_DP_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/system_ARMv81MML.h b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/system_ARMv81MML.h
new file mode 100755
index 0000000..43218c6
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Include/system_ARMv81MML.h
@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file system_ARMv81MML.h
+ * @brief CMSIS Device System Header File for
+ * Armv8.1-M Mainline Device Series
+ * @version V1.0.0
+ * @date 25. February 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMv81MML_H
+#define SYSTEM_ARMv81MML_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMv81MML_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/lnk.sct b/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/lnk.sct
new file mode 100755
index 0000000..4cc0dc9
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/lnk.sct
@@ -0,0 +1,76 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+#include "mem_ARMv81MML.h"
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x10000000
+#define __ROM_SIZE 0x00100000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x30000000
+#define __RAM_SIZE 0x00200000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE STACK_SIZE
+#define __HEAP_SIZE HEAP_SIZE
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE (__RAM_BASE )
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+; *(Veneer$$CMSE) ; uncomment for secure applications
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h b/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h
new file mode 100644
index 0000000..74cb212
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h
@@ -0,0 +1,38 @@
+/**************************************************************************//**
+ * @file mem_ARMCM7.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.1.0
+ * @date 15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMV81MML_H
+#define __MEM_ARMV81MML_H
+
+
+
+#define STACK_SIZE 0x00003000
+#define HEAP_SIZE 0x00100000
+
+
+
+#endif /* __MEM_ARMV81MML_H */
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/Startup/AC6/startup_ARMv81MML.c b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Startup/AC6/startup_ARMv81MML.c
new file mode 100755
index 0000000..b373ffc
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/Startup/AC6/startup_ARMv81MML.c
@@ -0,0 +1,149 @@
+/******************************************************************************
+ * @file startup_ARMv81MML.c
+ * @brief CMSIS Core Device Startup File for ARMv81MML Device
+ * @version V2.0.1
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMv81MML_DSP_DP_MVE_FP)
+ #include "ARMv81MML_DSP_DP_MVE_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) __NO_RETURN;
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+ const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
diff --git a/CMSIS/DSP/Platforms/FVP/ARMv81MML/system_ARMv81MML.c b/CMSIS/DSP/Platforms/FVP/ARMv81MML/system_ARMv81MML.c
new file mode 100644
index 0000000..2919ec0
--- /dev/null
+++ b/CMSIS/DSP/Platforms/FVP/ARMv81MML/system_ARMv81MML.c
@@ -0,0 +1,91 @@
+/**************************************************************************//**
+ * @file system_ARMv81MML.c
+ * @brief CMSIS Device System Source File for
+ * Armv8.1-M Mainline Device Series
+ * @version V1.2.0
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMv81MML_DSP_DP_MVE_FP)
+ #include "ARMv81MML_DSP_DP_MVE_FP.h"
+#else
+ #error device not specified!
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMv81MML.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __VECTOR_TABLE;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__MVE_USED) && (__MVE_USED == 1U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+
+}
diff --git a/CMSIS/DSP/Testing/.gitignore b/CMSIS/DSP/Testing/.gitignore
index 346ec0d..85aec6f 100644
--- a/CMSIS/DSP/Testing/.gitignore
+++ b/CMSIS/DSP/Testing/.gitignore
@@ -1,11 +1,5 @@
bench/
-build/
-build_m7/
-build_a5/
-build_m0/
-build_sdsim_a5/
-build_sdsim_a15/
-build_m33/
+build_*/
TODO.txt
olddesc.txt
oldprocessTests.py
diff --git a/CMSIS/DSP/Testing/FrameworkSource/Timing.cpp b/CMSIS/DSP/Testing/FrameworkSource/Timing.cpp
index 8b6737c..abc73ec 100644
--- a/CMSIS/DSP/Testing/FrameworkSource/Timing.cpp
+++ b/CMSIS/DSP/Testing/FrameworkSource/Timing.cpp
@@ -45,6 +45,8 @@
#include "ARMv8MML_DP.h"
#elif defined ARMv8MML_DSP_DP
#include "ARMv8MML_DSP_DP.h"
+#elif defined ARMv81MML_DSP_DP_MVE_FP
+ #include "ARMv81MML_DSP_DP_MVE_FP.h"
#elif defined ARMv7A
/* TODO */
#else
diff --git a/CMSIS/DSP/Toolchain/AC6.cmake b/CMSIS/DSP/Toolchain/AC6.cmake
index cb7ec76..8604f0c 100644
--- a/CMSIS/DSP/Toolchain/AC6.cmake
+++ b/CMSIS/DSP/Toolchain/AC6.cmake
@@ -65,14 +65,22 @@
target_compile_options(${PROJECTNAME} PUBLIC "-mfpu=vfpv4-d16")
endif()
endif()
+
+ if(EXPERIMENTAL)
+ experimentalCompilerSpecificCompileOptions(${PROJECTNAME} ${ROOT})
+ endif()
endfunction()
-function(toolchainSpecificLinkForCortexM PROJECTNAME ROOT CORE PLATFORMFOLDER)
+function(toolchainSpecificLinkForCortexM PROJECTNAME ROOT CORE PLATFORMFOLDER HASCSTARTUP)
# A specific library is created for ASM file
# since we do not want standard compile flags (for C) to be applied to
# ASM files.
- target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC6/startup_${CORE}.s)
+ if (HASCSTARTUP)
+ target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC6/startup_${CORE}.c)
+ else()
+ target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC6/startup_${CORE}.s)
+ endif()
target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/LinkScripts/AC6)
set(SCATTERFILE "${PLATFORMFOLDER}/${CORE}/LinkScripts/AC6/lnk.sct")
diff --git a/CMSIS/DSP/Toolchain/GCC.cmake b/CMSIS/DSP/Toolchain/GCC.cmake
index 00b3766..6efee1a 100644
--- a/CMSIS/DSP/Toolchain/GCC.cmake
+++ b/CMSIS/DSP/Toolchain/GCC.cmake
@@ -92,7 +92,7 @@
add_dependencies(${PROJECTNAME} scatter)
endfunction()
-function(toolchainSpecificLinkForCortexM PROJECTNAME ROOT CORE PLATFORMFOLDER)
+function(toolchainSpecificLinkForCortexM PROJECTNAME ROOT CORE PLATFORMFOLDER HASCSTARTUP)
target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/GCC/startup_${CORE}.S)
target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/GCC/support.c)
diff --git a/CMSIS/DSP/config.cmake b/CMSIS/DSP/config.cmake
index 6c52fc2..4a6c2a5 100755
--- a/CMSIS/DSP/config.cmake
+++ b/CMSIS/DSP/config.cmake
@@ -1,3 +1,8 @@
+if(EXPERIMENTAL)
+list(APPEND CMAKE_MODULE_PATH ${EXPROOT})
+include(experimental)
+endif()
+
include(Toolchain/Tools)
SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/FVP)
option(OPTIMIZED "Compile for speed" ON)
diff --git a/CMSIS/DSP/configBoot.cmake b/CMSIS/DSP/configBoot.cmake
index a85cfe8..fd3c663 100755
--- a/CMSIS/DSP/configBoot.cmake
+++ b/CMSIS/DSP/configBoot.cmake
@@ -15,14 +15,14 @@
cmake_print_variables(PROJECT_NAME)
-function(cortexm CORE PROJECT_NAME ROOT PLATFORMFOLDER)
+function(cortexm CORE PROJECT_NAME ROOT PLATFORMFOLDER CSTARTUP)
target_include_directories(${PROJECT_NAME} PRIVATE ${ROOT}/CMSIS/Core/Include)
target_sources(${PROJECT_NAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/system_${CORE}.c)
- toolchainSpecificLinkForCortexM(${PROJECT_NAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
+ toolchainSpecificLinkForCortexM(${PROJECT_NAME} ${ROOT} ${CORE} ${PLATFORMFOLDER} ${CSTARTUP})
configplatformForApp(${PROJECT_NAME} ${ROOT} ${CORE} ${PLATFORMFOLDER})
SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE)
@@ -49,12 +49,21 @@
target_include_directories(${PROJECT_NAME} PRIVATE ${ROOT}/CMSIS/DSP/Include)
set_platform_core()
+
+ if(EXPERIMENTAL)
+ experimentalConfigboot(${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ if (ISCORTEXM)
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} ${HASCSTARTUP})
+ else()
+ cortexa(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ endif()
+ endif()
###################
#
# Cortex cortex-m7
#
if (ARM_CPU STREQUAL "cortex-m7")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
@@ -63,7 +72,7 @@
# Cortex cortex-m4
#
if (ARM_CPU STREQUAL "cortex-m4")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
###################
@@ -71,7 +80,7 @@
# Cortex cortex-m35p
#
if (ARM_CPU STREQUAL "cortex-m35")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
@@ -80,7 +89,7 @@
# Cortex cortex-m33
#
if (ARM_CPU STREQUAL "cortex-m33")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
@@ -89,7 +98,7 @@
# Cortex cortex-m23
#
if (ARM_CPU STREQUAL "cortex-m23")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
@@ -98,7 +107,7 @@
# Cortex cortex-m0+
#
if (ARM_CPU STREQUAL "cortex-m0p")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
@@ -107,7 +116,7 @@
# Cortex cortex-m0
#
if (ARM_CPU STREQUAL "cortex-m0")
- cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER})
+ cortexm(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER} OFF)
endif()
diff --git a/CMSIS/DSP/configCore.cmake b/CMSIS/DSP/configCore.cmake
index e8523c0..eda57ec 100644
--- a/CMSIS/DSP/configCore.cmake
+++ b/CMSIS/DSP/configCore.cmake
@@ -19,6 +19,10 @@
function(configcore PROJECTNAME ROOT)
+ if(EXPERIMENTAL)
+ experimentalConfigcore(${PROJECTNAME} ${ROOT})
+ SET(COREID ${COREID} PARENT_SCOPE)
+ endif()
###################
#
# CORTEX-A
diff --git a/CMSIS/DSP/configPlatform.cmake b/CMSIS/DSP/configPlatform.cmake
index c08f930..bd306ad 100644
--- a/CMSIS/DSP/configPlatform.cmake
+++ b/CMSIS/DSP/configPlatform.cmake
@@ -17,6 +17,11 @@
include(platform)
function(set_platform_core)
+
+ if(EXPERIMENTAL)
+ experimental_set_platform_core()
+ SET(CORE ${CORE} PARENT_SCOPE)
+ endif()
###################
#
# Cortex cortex-m7