changed SystemInit function, add SVD files
diff --git a/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMCM0/Source/system_ARMCM0.c b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
index 666a1d7..682ba29 100644
--- a/Device/ARM/ARMCM0/Source/system_ARMCM0.c
+++ b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMCM0 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -36,14 +36,20 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
diff --git a/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
index d1cb4b6..bcf45d9 100644
--- a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
+++ b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -34,17 +34,35 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
SystemCoreClock = SYSTEM_CLOCK;
}
diff --git a/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMCM3/Source/system_ARMCM3.c b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
index 468fe50..3c9aa3a 100644
--- a/Device/ARM/ARMCM3/Source/system_ARMCM3.c
+++ b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -34,20 +34,35 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
SCB->VTOR = (uint32_t) &__Vectors;
+#endif
SystemCoreClock = SYSTEM_CLOCK;
}
diff --git a/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMCM4/Source/system_ARMCM4.c b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
index a504304..22fb6eb 100644
--- a/Device/ARM/ARMCM4/Source/system_ARMCM4.c
+++ b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMCM4 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -40,21 +40,35 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
SCB->VTOR = (uint32_t) &__Vectors;
-
+#endif
#if defined (__FPU_USED) && (__FPU_USED == 1)
SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */
diff --git a/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMCM7/Source/system_ARMCM7.c b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
index d6d0968..ac07e43 100644
--- a/Device/ARM/ARMCM7/Source/system_ARMCM7.c
+++ b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMCM7 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -42,21 +42,35 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
SCB->VTOR = (uint32_t) &__Vectors;
-
+#endif
#if defined (__FPU_USED) && (__FPU_USED == 1)
SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */
diff --git a/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld b/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMSC000/Source/system_ARMSC000.c b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
index 4d6d682..d8835b0 100644
--- a/Device/ARM/ARMSC000/Source/system_ARMSC000.c
+++ b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* for ARMSC000 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -36,14 +36,20 @@
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
diff --git a/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld b/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMSC300/Source/system_ARMSC300.c b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
index 07e207f..a3e5fd7 100644
--- a/Device/ARM/ARMSC300/Source/system_ARMSC300.c
+++ b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMSC300 Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -34,24 +34,39 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
SCB->VTOR = (uint32_t) &__Vectors;
+#endif
- #ifdef UNALIGNED_SUPPORT_DISABLE
- SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
- #endif
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
SystemCoreClock = SYSTEM_CLOCK;
}
diff --git a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
index ca23e20..0e52dd0 100644
--- a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
@@ -3,7 +3,7 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMv8MBL Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 08. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -103,11 +103,11 @@
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
-#define __SAU_PRESENT 1U /* SAU present or not */
-#define __MPU_PRESENT 0U /* MPU present or not */
-#define __VTOR_PRESENT 0U /* VTOR present or not */
-#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __SAU_PRESENT 1 /* SAU present or not */
+#define __MPU_PRESENT 0 /* MPU present or not */
+#define __VTOR_PRESENT 0 /* VTOR present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include "core_armv8mbl.h" /* Processor and core peripherals */
#include "system_ARMv8MBL.h" /* System Header */
diff --git a/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld b/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
index 6d65377..0b67974 100644
--- a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
+++ b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMv8MBL Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -38,19 +38,36 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML.h b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
index 5bc8a50..73f8663 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
@@ -3,7 +3,7 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMv8MML Device Series (configured for CM4 without FPU)
* @version V5.00
- * @date 02. March 2016
+ * @date 08. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -105,6 +105,7 @@
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAU_PRESENT 1 /* SAU present or not */
#define __MPU_PRESENT 1 /* MPU present or not */
+#define __VTOR_PRESENT 1 /* VTOR present */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /* no FPU present */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_FP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_FP.h
index 33b2bbe..626267e 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_FP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_FP.h
@@ -3,7 +3,7 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMv8MML Device Series (configured for CM4 with FPU)
* @version V5.00
- * @date 02. March 2016
+ * @date 08. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -105,9 +105,10 @@
#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
#define __SAU_PRESENT 1 /* SAU present or not */
#define __MPU_PRESENT 1 /* MPU present or not */
+#define __VTOR_PRESENT 1 /* VTOR present */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __FPU_PRESENT 1 /* FPU present */
#include "core_armv8mml.h" /* Processor and core peripherals */
#include "system_ARMv8MML.h" /* System Header */
diff --git a/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld b/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
index cf28eac..c8a11a5 100644
--- a/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
+++ b/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld
@@ -1,8 +1,8 @@
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
/* Library configurations */
diff --git a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
index 4830be4..7ef835e 100644
--- a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
+++ b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
@@ -3,7 +3,7 @@
* @brief CMSIS Device System Source File for
* ARMv8MML Device Series
* @version V5.00
- * @date 04. April 2016
+ * @date 08. April 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -44,21 +44,35 @@
/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
void SystemInit (void)
{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
SCB->VTOR = (uint32_t) &__Vectors;
-
+#endif
#if defined (__FPU_USED) && (__FPU_USED == 1)
SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */
diff --git a/Device/ARM/SVD/ARMCM0.svd b/Device/ARM/SVD/ARMCM0.svd
new file mode 100644
index 0000000..e40c842
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM0.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM0</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM0</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMCM0P.svd b/Device/ARM/SVD/ARMCM0P.svd
new file mode 100644
index 0000000..37ab758
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM0P.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM0P</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM0+</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMCM1.svd b/Device/ARM/SVD/ARMCM1.svd
new file mode 100644
index 0000000..13eb1d5
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM1.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM1</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM1</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMCM3.svd b/Device/ARM/SVD/ARMCM3.svd
new file mode 100644
index 0000000..78a53ae
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM3.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM3</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM3</name>
+ <revision>r1p1</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>4</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMCM4.svd b/Device/ARM/SVD/ARMCM4.svd
new file mode 100644
index 0000000..63a9ac6
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM4.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM4</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM4</name>
+ <revision>r1p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMCM7.svd b/Device/ARM/SVD/ARMCM7.svd
new file mode 100644
index 0000000..34adfb1
--- /dev/null
+++ b/Device/ARM/SVD/ARMCM7.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMCM7</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM7</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMSC000.svd b/Device/ARM/SVD/ARMSC000.svd
new file mode 100644
index 0000000..b3e8637
--- /dev/null
+++ b/Device/ARM/SVD/ARMSC000.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMSC000</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>SC000</name>
+ <revision>r1p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMSC300.svd b/Device/ARM/SVD/ARMSC300.svd
new file mode 100644
index 0000000..3a066dc
--- /dev/null
+++ b/Device/ARM/SVD/ARMSC300.svd
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMSC300</name> <!-- name of part-->
+ <series>ARMCM</series> <!-- device series the device belongs to -->
+ <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>SC300</name>
+ <revision>r1p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <peripheral>
+ <name>SysTick</name>
+ <description>24Bit System Tick Timer for use in RTOS</description>
+ <baseAddress>0xE000E010</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>SysTick Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLE</name>
+ <description>Enable SysTick Timer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TICKINT</name>
+ <description>Generate Tick Interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Enable SysTick Exception</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Disable SysTick Exception</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKSOURCE</name>
+ <description>Source to count from</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>External Clock</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>CPU Clock</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COUNTFLAG</name>
+ <description>SysTick counted to zero</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RVR</name>
+ <description>SysTick Reload Value Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Value to auto reload SysTick after reaching zero</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CVR</name>
+ <description>SysTick Current Value Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CURRENT</name>
+ <description>Current value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIB</name>
+ <description>SysTick Calibration Value Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TENMS</name>
+ <description>Reload value to use for 10ms timing</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SKEW</name>
+ <description>Clock Skew</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>10ms calibration value is exact</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>10ms calibration value is inexact, because of the clock frequency</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NOREF</name>
+ <description>No Ref</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>0</name>
+ <description>Ref Clk available</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1</name>
+ <description>Ref Clk not available</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer</description>
+ <baseAddress>0x40001000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x10</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <interrupt>
+ <name>WDT</name>
+ <value>1</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CSR</name>
+ <description>Watchdog Control and Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <resetValue>0x4</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMv8MBL.svd b/Device/ARM/SVD/ARMv8MBL.svd
new file mode 100644
index 0000000..14b1d86
--- /dev/null
+++ b/Device/ARM/SVD/ARMv8MBL.svd
@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMv8MBL</name> <!-- name of part-->
+ <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit v8-M Baseline based device</description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM3</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>true</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ <sauNumRegions>4</sauNumRegions>
+ <sauRegionsConfig enabled="true" protectionWhenDisabled="s">
+ <region enabled="true" name="SauRegion0">
+ <base>0x00000000</base>
+ <limit>0x001FFFE0</limit>
+ <!-- secure / non-secure callable -->
+ <access>c</access>
+ </region>
+ <region enabled="true" name="SauRegion1">
+ <base>0x00200000</base>
+ <limit>0x003FFFE0</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ <region enabled="true" name="SauRegion2">
+ <base>0x20200000</base>
+ <limit>0x203FFFE0</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ <region enabled="true" name="SauRegion3">
+ <base>0x40000000</base>
+ <limit>0x40040000</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ </sauRegionsConfig>
+
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <!-- Timer 0 -->
+ <peripheral>
+ <name>SAU</name>
+ <version>1.0</version>
+ <description>Security Attribution Unit</description>
+ <groupName>SAU</groupName>
+ <baseAddress>0xE000EDD0</baseAddress>
+ <size>32</size>
+ <access>read-write</access>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x20</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <!-- CTRL: Control Register -->
+ <register>
+ <name>CTRL</name>
+ <description>Control Register</description>
+ <addressOffset>0x00</addressOffset>
+ <fields>
+ <!-- EN: Enable -->
+ <field>
+ <name>ENABLE</name>
+ <description>Enable</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disable</name>
+ <description>SAU is disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enable</name>
+ <description>SAU is enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+
+ <!-- RST: Reset -->
+ <field>
+ <name>ALLNS</name>
+ <description>Security attribution if SAU disabled</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Secure</name>
+ <description>Memory is marked as secure</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Non_Secure</name>
+ <description>Memory is marked as non-secure</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+
+ <!-- TYPE: -->
+ <register>
+ <name>TYPE</name>
+ <description>Type Register</description>
+ <addressOffset>0x04</addressOffset>
+ <access>read-only</access>
+ <fields>
+ <!-- SREGION: -->
+ <field>
+ <name>SREGION</name>
+ <description>Number of implemented SAU regions</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RNR: -->
+ <register>
+ <name>RNR</name>
+ <description>Region Number Register</description>
+ <addressOffset>0x08</addressOffset>
+ <fields>
+ <!-- REGION: -->
+ <field>
+ <name>REGION</name>
+ <description>Currently selected SAU region</description>
+ <bitRange>[7:0]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SAU_Region_0</name>
+ <description>Select SAU Region 0</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_1</name>
+ <description>Select SAU Region 1</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_2</name>
+ <description>Select SAU Region 2</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_3</name>
+ <description>Select SAU Region 3</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RBAR: -->
+ <register>
+ <name>RBAR</name>
+ <description>Region Base Address Register</description>
+ <addressOffset>0x0C</addressOffset>
+ <fields>
+ <!-- BADDR: -->
+ <field>
+ <name>BADDR</name>
+ <description>Base Address</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RBAR: -->
+ <register>
+ <name>RLAR</name>
+ <description>Region Limit Address Register</description>
+ <addressOffset>0x10</addressOffset>
+ <fields>
+ <!-- LADDR: -->
+ <field>
+ <name>LADDR</name>
+ <description>Limit Address</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ <!-- NSC: -->
+ <field>
+ <name>NSC</name>
+ <description>Non-Secure Callable</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <!-- ENABLE: -->
+ <field>
+ <name>ENABLE</name>
+ <description>SAU Region enabled</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/Device/ARM/SVD/ARMv8MML.svd b/Device/ARM/SVD/ARMv8MML.svd
new file mode 100644
index 0000000..b9a639f
--- /dev/null
+++ b/Device/ARM/SVD/ARMv8MML.svd
@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <part/series name>.svd -->
+
+<!--
+ Copyright (C) 2012-2014 ARM Limited. All rights reserved.
+
+ Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+ This is a description of a none-existent and incomplete device
+ for demonstration purposes only.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ -->
+
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
+ <vendor>ARM Ltd.</vendor> <!-- device vendor name -->
+ <vendorID>ARM</vendorID> <!-- device vendor short name -->
+ <name>ARMv8MML</name> <!-- name of part-->
+ <series>ARMV8M</series> <!-- device series the device belongs to -->
+ <version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+ <description>ARM 32-bit v8-M Baseline based device</description>
+ <licenseText> <!-- this license text will appear in header file. \n force line breaks -->
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ </licenseText>
+ <cpu> <!-- details about the cpu embedded in the device -->
+ <name>CM4</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>true</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ <sauNumRegions>4</sauNumRegions>
+ <sauRegionsConfig enabled="true" protectionWhenDisabled="s">
+ <region enabled="true" name="SauRegion0">
+ <base>0x00000000</base>
+ <limit>0x001FFFE0</limit>
+ <!-- secure / non-secure callable -->
+ <access>c</access>
+ </region>
+ <region enabled="true" name="SauRegion1">
+ <base>0x00200000</base>
+ <limit>0x003FFFE0</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ <region enabled="true" name="SauRegion2">
+ <base>0x20200000</base>
+ <limit>0x203FFFE0</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ <region enabled="true" name="SauRegion3">
+ <base>0x40000000</base>
+ <limit>0x40040000</limit>
+ <!-- non-secure -->
+ <access>n</access>
+ </region>
+ </sauRegionsConfig>
+
+ </cpu>
+ <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
+ <width>32</width> <!-- bus width is 32 bits -->
+ <!-- default settings implicitly inherited by subsequent sections -->
+ <size>32</size> <!-- this is the default size (number of bits) of all peripherals
+ and register that do not define "size" themselves -->
+ <access>read-write</access> <!-- default access permission for all subsequent registers -->
+ <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
+ <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
+
+ <peripherals>
+ <!-- Timer 0 -->
+ <peripheral>
+ <name>SAU</name>
+ <version>1.0</version>
+ <description>Security Attribution Unit</description>
+ <groupName>SAU</groupName>
+ <baseAddress>0xE000EDD0</baseAddress>
+ <size>32</size>
+ <access>read-write</access>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x20</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <!-- CTRL: Control Register -->
+ <register>
+ <name>CTRL</name>
+ <description>Control Register</description>
+ <addressOffset>0x00</addressOffset>
+ <fields>
+ <!-- EN: Enable -->
+ <field>
+ <name>ENABLE</name>
+ <description>Enable</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disable</name>
+ <description>SAU is disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enable</name>
+ <description>SAU is enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+
+ <!-- RST: Reset -->
+ <field>
+ <name>ALLNS</name>
+ <description>Security attribution if SAU disabled</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Secure</name>
+ <description>Memory is marked as secure</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Non_Secure</name>
+ <description>Memory is marked as non-secure</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+
+ <!-- TYPE: -->
+ <register>
+ <name>TYPE</name>
+ <description>Type Register</description>
+ <addressOffset>0x04</addressOffset>
+ <access>read-only</access>
+ <fields>
+ <!-- SREGION: -->
+ <field>
+ <name>SREGION</name>
+ <description>Number of implemented SAU regions</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RNR: -->
+ <register>
+ <name>RNR</name>
+ <description>Region Number Register</description>
+ <addressOffset>0x08</addressOffset>
+ <fields>
+ <!-- REGION: -->
+ <field>
+ <name>REGION</name>
+ <description>Currently selected SAU region</description>
+ <bitRange>[7:0]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SAU_Region_0</name>
+ <description>Select SAU Region 0</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_1</name>
+ <description>Select SAU Region 1</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_2</name>
+ <description>Select SAU Region 2</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAU_Region_3</name>
+ <description>Select SAU Region 3</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RBAR: -->
+ <register>
+ <name>RBAR</name>
+ <description>Region Base Address Register</description>
+ <addressOffset>0x0C</addressOffset>
+ <fields>
+ <!-- BADDR: -->
+ <field>
+ <name>BADDR</name>
+ <description>Base Address</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+ <!-- RBAR: -->
+ <register>
+ <name>RLAR</name>
+ <description>Region Limit Address Register</description>
+ <addressOffset>0x10</addressOffset>
+ <fields>
+ <!-- LADDR: -->
+ <field>
+ <name>LADDR</name>
+ <description>Limit Address</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ <!-- NSC: -->
+ <field>
+ <name>NSC</name>
+ <description>Non-Secure Callable</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <!-- ENABLE: -->
+ <field>
+ <name>ENABLE</name>
+ <description>SAU Region enabled</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>