RTX5: added support for MVE-I (Armv8.1-M)
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index a2ea7f6..650d23b 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -1141,10 +1141,6 @@
<description>Cortex-M35P processor based device using Floating Point Unit</description>
<require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
</condition>
- <condition id="CM55">
- <description>Cortex-M55 processor based device</description>
- <require Dcore="Cortex-M55"/>
- </condition>
<condition id="ARMv8MBL">
<description>Armv8-M Baseline processor based device</description>
<require Dcore="ARMV8MBL"/>
@@ -1193,9 +1189,14 @@
<require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
</condition>
- <condition id="CM55_NOFPU">
- <description>Cortex-M55, no FPU</description>
- <require Dcore="Cortex-M55" Dfpu="NO_FPU"/>
+ <condition id="CM55_NOFPU_NOMVE">
+ <description>Cortex-M55, no FPU, no MVE</description>
+ <require Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="NO_MVE"/>
+ </condition>
+ <condition id="CM55_NOFPU_MVE">
+ <description>Cortex-M55, no FPU, MVE</description>
+ <accept Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="MVE"/>
+ <accept Dcore="Cortex-M55" Dfpu="NO_FPU" Dmve="FP_MVE"/>
</condition>
<condition id="CM55_FPU">
<description>Cortex-M55, FPU</description>
@@ -1524,20 +1525,14 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM55_ARMCC">
- <description>Cortex-M55 processor based device for the Arm Compiler</description>
- <require condition="CM55"/>
+ <condition id="CM55_NOFPU_NOMVE_ARMCC">
+ <description>Cortex-M55 processor, no FPU, no MVE, Arm Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE"/>
<require Tcompiler="ARMCC"/>
</condition>
- <condition id="CM55_LE_ARMCC">
- <description>Cortex-M55 processor based device in little endian mode for the Arm Compiler</description>
- <require condition="CM55_ARMCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_ARMCC">
- <description>Cortex-M55 processor, no FPU, Arm Compiler</description>
- <require condition="CM55_NOFPU"/>
+ <condition id="CM55_NOFPU_MVE_ARMCC">
+ <description>Cortex-M55 processor, no FPU, MVE, Arm Compiler</description>
+ <require condition="CM55_NOFPU_MVE"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM55_FPU_ARMCC">
@@ -1545,9 +1540,9 @@
<require condition="CM55_FPU"/>
<require Tcompiler="ARMCC"/>
</condition>
- <condition id="CM55_NOFPU_LE_ARMCC">
- <description>Cortex-M55 processor, little endian, no FPU, Arm Compiler</description>
- <require condition="CM55_NOFPU_ARMCC"/>
+ <condition id="CM55_NOFPU_NOMVE_LE_ARMCC">
+ <description>Cortex-M55 processor, little endian, no FPU, no MVE, Arm Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM55_FPU_LE_ARMCC">
@@ -1908,20 +1903,14 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM55_GCC">
- <description>Cortex-M55 processor based device for the GCC Compiler</description>
- <require condition="CM55"/>
+ <condition id="CM55_NOFPU_NOMVE_GCC">
+ <description>Cortex-M55 processor, no FPU, no MVE, GCC Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE"/>
<require Tcompiler="GCC"/>
</condition>
- <condition id="CM55_LE_GCC">
- <description>Cortex-M55 processor based device in little endian mode for the GCC Compiler</description>
- <require condition="CM55_GCC"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_GCC">
- <description>Cortex-M55 processor, no FPU, GCC Compiler</description>
- <require condition="CM55_NOFPU"/>
+ <condition id="CM55_NOFPU_MVE_GCC">
+ <description>Cortex-M55 processor, no FPU, MVE, GCC Compiler</description>
+ <require condition="CM55_NOFPU_MVE"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="CM55_FPU_GCC">
@@ -1929,9 +1918,9 @@
<require condition="CM55_FPU"/>
<require Tcompiler="GCC"/>
</condition>
- <condition id="CM55_NOFPU_LE_GCC">
- <description>Cortex-M55 processor, little endian, no FPU, GCC Compiler</description>
- <require condition="CM55_NOFPU_GCC"/>
+ <condition id="CM55_NOFPU_NOMVE_LE_GCC">
+ <description>Cortex-M55 processor, little endian, no FPU, no MVE, GCC Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM55_FPU_LE_GCC">
@@ -2302,20 +2291,14 @@
<require Dendian="Little-endian"/>
</condition>
- <condition id="CM55_IAR">
- <description>Cortex-M55 processor based device for the IAR Compiler</description>
- <require condition="CM55"/>
+ <condition id="CM55_NOFPU_NOMVE_IAR">
+ <description>Cortex-M55 processor, no FPU, no MVE, IAR Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE"/>
<require Tcompiler="IAR"/>
</condition>
- <condition id="CM55_LE_IAR">
- <description>Cortex-M55 processor based device in little endian mode for the IAR Compiler</description>
- <require condition="CM55_IAR"/>
- <require Dendian="Little-endian"/>
- </condition>
-
- <condition id="CM55_NOFPU_IAR">
- <description>Cortex-M55 processor, no FPU, IAR Compiler</description>
- <require condition="CM55_NOFPU"/>
+ <condition id="CM55_NOFPU_MVE_IAR">
+ <description>Cortex-M55 processor, no FPU, MVE, IAR Compiler</description>
+ <require condition="CM55_NOFPU_MVE"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="CM55_FPU_IAR">
@@ -2323,9 +2306,9 @@
<require condition="CM55_FPU"/>
<require Tcompiler="IAR"/>
</condition>
- <condition id="CM55_NOFPU_LE_IAR">
- <description>Cortex-M55 processor, little endian, no FPU, IAR Compiler</description>
- <require condition="CM55_NOFPU_IAR"/>
+ <condition id="CM55_NOFPU_NOMVE_LE_IAR">
+ <description>Cortex-M55 processor, little endian, no FPU, no MVE, IAR Compiler</description>
+ <require condition="CM55_NOFPU_NOMVE_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM55_FPU_LE_IAR">
@@ -2569,13 +2552,6 @@
<require Cclass="Device" Cgroup="OS Tick"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
- <condition id="RTOS2 RTX5 Lib">
- <description>Components required for RTOS2 RTX5 Library</description>
- <require condition="ARMv6_7_8-M Device"/>
- <require condition="ARMCC GCC IAR"/>
- <require Cclass="CMSIS" Cgroup="CORE"/>
- <require Cclass="Device" Cgroup="Startup"/>
- </condition>
<condition id="RTOS2 RTX5 NS">
<description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
<require condition="ARMv8-M Device"/>
@@ -3472,8 +3448,8 @@
</component>
<!-- CMSIS-RTOS2 Keil RTX5 component -->
- <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.2" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
- <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
+ <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.2" Capiversion="2.1.3" condition="RTOS2 RTX5">
+ <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -3507,63 +3483,63 @@
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
- <file category="library" condition="CM0_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM0_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM1_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM3_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
- <file category="library" condition="CM0_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM0_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM1_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM3_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
- <file category="library" condition="CM0_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM1_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM3_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM7_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM0_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM1_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM3_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM7_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.2" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
- <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
+ <description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -3598,42 +3574,42 @@
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
- <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
- <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_GCC" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
- <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_NOFPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
- <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM23_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM33_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM35P_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_NOFPU_NOMVE_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="CM55_FPU_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
+ <file category="library" condition="ARMv8MML_FP_LE_IAR" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.2" Capiversion="2.1.3" condition="RTOS2 RTX5">
- <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
+ <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -3691,8 +3667,9 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM33_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM35P_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM35P_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM55_FPU_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_MVE_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_FPU_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s" condition="ARMv8MBL_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_FP_ARMCC"/>
@@ -3709,7 +3686,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM35P_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM55_NOFPU_NOMVE_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM55_NOFPU_MVE_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM55_FPU_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="ARMv8MBL_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_GCC"/>
@@ -3727,7 +3705,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM35P_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_NOMVE_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_NOFPU_MVE_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM55_FPU_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="ARMv8MBL_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="ARMv8MML_IAR"/>
@@ -3794,7 +3773,7 @@
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.2" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
- <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
+ <description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -3846,8 +3825,9 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM33_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM35P_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="CM35P_FP_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_NOFPU_ARMCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM55_FPU_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_NOFPU_NOMVE_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_NOFPU_MVE_ARMCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_FPU_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s" condition="ARMv8MBL_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="ARMv8MML_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s" condition="ARMv8MML_FP_ARMCC"/>
@@ -3857,7 +3837,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM35P_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_NOFPU_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="CM55_NOFPU_NOMVE_GCC"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM55_NOFPU_MVE_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM55_FPU_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S" condition="ARMv8MBL_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S" condition="ARMv8MML_GCC"/>
@@ -3868,7 +3849,8 @@
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM33_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM35P_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM35P_FP_IAR"/>
- <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM55_NOFPU_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM55_NOFPU_NOMVE_IAR"/>
+ <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM55_NOFPU_MVE_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="CM55_FPU_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s" condition="ARMv8MBL_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s" condition="ARMv8MML_IAR"/>
diff --git a/CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvprojx b/CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvprojx
index e880c29..44a114c 100644
--- a/CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvprojx
+++ b/CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvprojx
@@ -3938,7 +3938,7 @@
<interw>0</interw>
<VariousControls>
<MiscControls>-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard</MiscControls>
- <Define>__FPU_USED=1</Define>
+ <Define>FPU_USED=1</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
@@ -4478,7 +4478,7 @@
<interw>0</interw>
<VariousControls>
<MiscControls>-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard</MiscControls>
- <Define>__FPU_USED=1 DOMAIN_NS=1</Define>
+ <Define>FPU_USED=1 DOMAIN_NS=1</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
index c03b941..65cfc4e 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s
@@ -29,9 +29,9 @@
ENDIF
IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
-__FPU_USED EQU 1
+FPU_USED EQU 1
ELSE
-__FPU_USED EQU 0
+FPU_USED EQU 0
ENDIF
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
@@ -88,7 +88,7 @@
IT EQ
BXEQ LR ; Exit when threads are the same
- IF __FPU_USED = 1
+ IF FPU_USED = 1
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
@@ -113,7 +113,7 @@
SVC_ContextSave1
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
- IF __FPU_USED = 1
+ IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
@@ -154,7 +154,7 @@
BNE SVC_ContextRestore2 ; Branch if secure
ENDIF
- IF __FPU_USED = 1
+ IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
@@ -247,7 +247,7 @@
Sys_ContextSave2
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
- IF __FPU_USED = 1
+ IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
@@ -288,7 +288,7 @@
BNE Sys_ContextRestore2 ; Branch if secure
ENDIF
- IF __FPU_USED = 1
+ IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
index 3a704a2..6a9b298 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S
@@ -27,7 +27,7 @@
.syntax unified
.ifndef DOMAIN_NS
- .equ DOMAIN_NS, 0
+ .equ DOMAIN_NS, 0
.endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
index 256f894..b86ce1d 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
@@ -27,11 +27,23 @@
.syntax unified
.ifndef DOMAIN_NS
- .equ DOMAIN_NS, 0
+ .equ DOMAIN_NS, 0
.endif
- .ifndef __FPU_USED
- .equ __FPU_USED, 0
+ .ifndef FPU_USED
+ #if (defined(__ARM_FP) && (__ARM_FP > 0))
+ .equ FPU_USED, 1
+ #else
+ .equ FPU_USED, 0
+ #endif
+ .endif
+
+ .ifndef MVE_USED
+ #if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))
+ .equ MVE_USED, 1
+ #else
+ .equ MVE_USED, 0
+ #endif
.endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
@@ -81,7 +93,7 @@
IT EQ
BXEQ LR // Exit when threads are the same
- .if __FPU_USED == 1
+ .if (FPU_USED == 1) || (MVE_USED == 1)
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch
@@ -106,7 +118,7 @@
SVC_ContextSave1:
MRS R0,PSP // Get PSP
STMDB R0!,{R4-R11} // Save R4..R11
- .if __FPU_USED == 1
+ .if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31
@@ -140,7 +152,7 @@
BNE SVC_ContextRestore2 // Branch if secure
.endif
- .if __FPU_USED == 1
+ .if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
@@ -235,7 +247,7 @@
Sys_ContextSave2:
MRS R0,PSP // Get PSP
STMDB R0!,{R4-R11} // Save R4..R11
- .if __FPU_USED == 1
+ .if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31
@@ -269,7 +281,7 @@
BNE Sys_ContextRestore2 // Branch if secure
.endif
- .if __FPU_USED == 1
+ .if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S
index 4e78031..e756127 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S
@@ -1,3 +1,3 @@
- .equ __FPU_USED, 1
+ .equ FPU_USED, 1
.include "../Source/GCC/irq_armv8mml.S"
.end
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S
index a2ee55a..5618dc3 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S
@@ -1,4 +1,4 @@
- .equ __FPU_USED, 1
+ .equ FPU_USED, 1
.equ DOMAIN_NS, 1
.include "../Source/GCC/irq_armv8mml.S"
.end
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s
index d033e6f..48b1538 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s
@@ -29,9 +29,15 @@
#endif
#ifdef __ARMVFP__
-__FPU_USED EQU 1
+FPU_USED EQU 1
#else
-__FPU_USED EQU 0
+FPU_USED EQU 0
+#endif
+
+#if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))
+MVE_USED EQU 1
+#else
+MVE_USED EQU 0
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
@@ -85,7 +91,7 @@
IT EQ
BXEQ LR ; Exit when threads are the same
- #if (__FPU_USED == 1)
+ #if ((FPU_USED == 1) || (MVE_USED == 1))
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
@@ -110,7 +116,7 @@
SVC_ContextSave1
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
- #if (__FPU_USED == 1)
+ #if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
@@ -144,7 +150,7 @@
BNE SVC_ContextRestore2 ; Branch if secure
#endif
- #if (__FPU_USED == 1)
+ #if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
@@ -226,7 +232,7 @@
Sys_ContextSave2
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
- #if (__FPU_USED == 1)
+ #if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
@@ -260,7 +266,7 @@
BNE Sys_ContextRestore2 ; Branch if secure
#endif
- #if (__FPU_USED == 1)
+ #if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
index 7abf1d9..9bd0c88 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
@@ -97,7 +97,8 @@
/// \param[in] stack_frame Stack Frame (EXC_RETURN[7..0])
/// \return R0 Offset
__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
-#if (__FPU_USED == 1U)
+#if ((__FPU_USED == 1U) || \
+ (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0)))
return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U));
#else
(void)stack_frame;