Updating company brand
- Converted ARM to Arm in all documentative text in source, header, and doxygen.
- Converted ARM to Arm in descriptive texts in pack description file.
All identifier strings, like vendor, are kept unchanged due to compatibility reasons.
- Updated copyright year and file date.
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 26ec04a..9f2427a 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,8 +8,13 @@
<url>http://www.keil.com/pack/</url>
<releases>
+ <release version="5.2.1-dev3">
+ Active development...
+ </release>
+ <release version="5.2.1-dev2">
+ Updated company brand.
+ </release>
<release version="5.2.1-dev1">
- Active development...
CMSIS-RTOS2:
- RTX 5.3.0 (see revision history for details)
- OS Tick API 1.0.1
@@ -212,7 +217,7 @@
<family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
<description>
-The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -234,7 +239,7 @@
<family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
<description>
-The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -261,7 +266,7 @@
<family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
<description>
-The Cortex-M3 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -283,7 +288,7 @@
<family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
<description>
-The Cortex-M4 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -310,7 +315,7 @@
<family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
<description>
-The Cortex-M7 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
+The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -342,8 +347,8 @@
<family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
<description>
-The ARM Cortex-M23 is based on the ARMv8-M baseline architecture.
-It is the smallest and most energy efficient ARM processor with ARM TrustZone technology.
+The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
+It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
</description>
<debug svd="Device/ARM/SVD/ARMCM23.svd"/>
@@ -368,8 +373,8 @@
<family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
<description>
-The ARM Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
-class processor based on the ARMv8-M mainline architecture with ARM TrustZone security.
+The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
+class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
</description>
<debug svd="Device/ARM/SVD/ARMCM33.svd"/>
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
@@ -414,7 +419,7 @@
<!-- ****************************** ARMSC000 ****************************** -->
<family Dfamily="ARM SC000" Dvendor="ARM:82">
<description>
-The ARM SC000 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
+The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
@@ -455,7 +460,7 @@
<family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf" title="ARMv8MBL Device Generic Users Guide"/-->
<description>
-ARMv8-M Baseline based device with TrustZone
+Armv8-M Baseline based device with TrustZone
</description>
<debug svd="Device/ARM/SVD/ARMv8MBL.svd"/>
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
@@ -474,7 +479,7 @@
<family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf" title="ARMv8MML Device Generic Users Guide"/-->
<description>
-ARMv8-M Mainline based device with TrustZone
+Armv8-M Mainline based device with TrustZone
</description>
<debug svd="Device/ARM/SVD/ARMv8MML.svd"/>
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
@@ -536,9 +541,9 @@
<family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
<description>
-The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full
-virtual memory capabilities. The Cortex-A5 processor implements the ARMv7-A architecture profile and can execute 32-bit
-ARM instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
+The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
+virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
+Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
</description>
<memory id="IROM1" start="0x80000000" size="0x00200000" startup="1" default="1"/>
@@ -554,7 +559,7 @@
<family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
<description>
-The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the ARMv7-A architecture.
+The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
an optional integrated GIC, and an optional L2 cache controller.
</description>
@@ -572,8 +577,8 @@
<family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
<description>
-The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
-The Cortex-A9 processor implements the ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions,
+The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
+The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
and 8-bit Java bytecodes in Jazelle state.
</description>
@@ -740,45 +745,45 @@
<accept Tcompiler="IAR"/>
</condition>
- <!-- ARM architecture -->
+ <!-- Arm architecture -->
<condition id="ARMv6-M Device">
- <description>ARMv6-M architecture based device</description>
+ <description>Armv6-M architecture based device</description>
<accept Dcore="Cortex-M0"/>
<accept Dcore="Cortex-M0+"/>
<accept Dcore="SC000"/>
</condition>
<condition id="ARMv7-M Device">
- <description>ARMv7-M architecture based device</description>
+ <description>Armv7-M architecture based device</description>
<accept Dcore="Cortex-M3"/>
<accept Dcore="Cortex-M4"/>
<accept Dcore="Cortex-M7"/>
<accept Dcore="SC300"/>
</condition>
<condition id="ARMv8-M Device">
- <description>ARMv8-M architecture based device</description>
+ <description>Armv8-M architecture based device</description>
<accept Dcore="ARMV8MBL"/>
<accept Dcore="ARMV8MML"/>
<accept Dcore="Cortex-M23"/>
<accept Dcore="Cortex-M33"/>
</condition>
<condition id="ARMv8-M TZ Device">
- <description>ARMv8-M architecture based device with TrustZone</description>
+ <description>Armv8-M architecture based device with TrustZone</description>
<require condition="ARMv8-M Device"/>
<require Dtz="TZ"/>
</condition>
<condition id="ARMv6_7-M Device">
- <description>ARMv6_7-M architecture based device</description>
+ <description>Armv6_7-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
</condition>
<condition id="ARMv6_7_8-M Device">
- <description>ARMv6_7_8-M architecture based device</description>
+ <description>Armv6_7_8-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
<accept condition="ARMv8-M Device"/>
</condition>
<condition id="ARMv7-A Device">
- <description>ARMv7-A architecture based device</description>
+ <description>Armv7-A architecture based device</description>
<accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A7"/>
<accept Dcore="Cortex-A9"/>
@@ -836,15 +841,15 @@
<require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
</condition>
<condition id="ARMv8MBL">
- <description>ARMv8-M Baseline processor based device</description>
+ <description>Armv8-M Baseline processor based device</description>
<require Dcore="ARMV8MBL"/>
</condition>
<condition id="ARMv8MML">
- <description>ARMv8-M Mainline processor based device</description>
+ <description>Armv8-M Mainline processor based device</description>
<require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_FP">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
<accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
<accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
</condition>
@@ -867,19 +872,19 @@
</condition>
<condition id="ARMv8MML_NODSP_NOFPU">
- <description>ARMv8MML, no DSP, no FPU</description>
+ <description>Armv8-M Mainline, no DSP, no FPU</description>
<require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU">
- <description>ARMv8MML, DSP, no FPU</description>
+ <description>Armv8-M Mainline, DSP, no FPU</description>
<require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_NODSP_SP">
- <description>ARMv8MML, no DSP, SP FPU</description>
+ <description>Armv8-M Mainline, no DSP, SP FPU</description>
<require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
</condition>
<condition id="ARMv8MML_DSP_SP">
- <description>ARMv8MML, DSP, SP FPU</description>
+ <description>Armv8-M Mainline, DSP, SP FPU</description>
<require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
</condition>
@@ -896,318 +901,318 @@
<!-- ARMCC compiler -->
<condition id="CA_ARMCC5">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the ARM Compiler 5</description>
+ <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC5"/>
</condition>
<condition id="CA_ARMCC6">
- <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the ARM Compiler 6</description>
+ <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC6"/>
</condition>
<condition id="CM0_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the ARM Compiler</description>
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
<require condition="CM0"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM0_LE_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM0_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM0_BE_ARMCC">
- <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM0_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM3_ARMCC">
- <description>Cortex-M3 or SC300 processor based device for the ARM Compiler</description>
+ <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
<require condition="CM3"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM3_LE_ARMCC">
- <description>Cortex-M3 or SC300 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM3_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM3_BE_ARMCC">
- <description>Cortex-M3 or SC300 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM3_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM4_ARMCC">
- <description>Cortex-M4 processor based device for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device for the Arm Compiler</description>
<require condition="CM4"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM4_LE_ARMCC">
- <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM4_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM4_BE_ARMCC">
- <description>Cortex-M4 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM4_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM4_FP_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
<require condition="CM4_FP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM4_FP_LE_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
<require condition="CM4_FP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM4_FP_BE_ARMCC">
- <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
<require condition="CM4_FP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM7_ARMCC">
- <description>Cortex-M7 processor based device for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device for the Arm Compiler</description>
<require condition="CM7"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM7_LE_ARMCC">
- <description>Cortex-M7 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM7_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM7_BE_ARMCC">
- <description>Cortex-M7 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM7_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM7_FP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
<require condition="CM7_FP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM7_FP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
<require condition="CM7_FP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM7_FP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
<require condition="CM7_FP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM7_SP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
<require condition="CM7_SP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM7_SP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
<require condition="CM7_SP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM7_SP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
<require condition="CM7_SP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM7_DP_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
<require condition="CM7_DP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM7_DP_LE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
<require condition="CM7_DP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM7_DP_BE_ARMCC">
- <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
<require condition="CM7_DP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM23_ARMCC">
- <description>Cortex-M23 processor based device for the ARM Compiler</description>
+ <description>Cortex-M23 processor based device for the Arm Compiler</description>
<require condition="CM23"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM23_LE_ARMCC">
- <description>Cortex-M23 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM23_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM23_BE_ARMCC">
- <description>Cortex-M23 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM23_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM33_ARMCC">
- <description>Cortex-M33 processor based device for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device for the Arm Compiler</description>
<require condition="CM33"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_LE_ARMCC">
- <description>Cortex-M33 processor based device in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM33_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM33_BE_ARMCC">
- <description>Cortex-M33 processor based device in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM33_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM33_FP_ARMCC">
- <description>Cortex-M33 processor based device using Floating Point Unit for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
<require condition="CM33_FP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_FP_LE_ARMCC">
- <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
<require condition="CM33_FP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM33_FP_BE_ARMCC">
- <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+ <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
<require condition="CM33_FP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM33_NODSP_NOFPU_ARMCC">
- <description>CM33, no DSP, no FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
<require condition="CM33_NODSP_NOFPU"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_DSP_NOFPU_ARMCC">
- <description>CM33, DSP, no FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
<require condition="CM33_DSP_NOFPU"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_NODSP_SP_ARMCC">
- <description>CM33, no DSP, SP FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
<require condition="CM33_NODSP_SP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_DSP_SP_ARMCC">
- <description>CM33, DSP, SP FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
<require condition="CM33_DSP_SP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM33_NODSP_NOFPU_LE_ARMCC">
- <description>CM33, little endian, no DSP, no FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
<require condition="CM33_NODSP_NOFPU_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM33_DSP_NOFPU_LE_ARMCC">
- <description>CM33, little endian, DSP, no FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
<require condition="CM33_DSP_NOFPU_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM33_NODSP_SP_LE_ARMCC">
- <description>CM33, little endian, no DSP, SP FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
<require condition="CM33_NODSP_SP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM33_DSP_SP_LE_ARMCC">
- <description>CM33, little endian, DSP, SP FPU, ARM Compiler</description>
+ <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
<require condition="CM33_DSP_SP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MBL_ARMCC">
- <description>ARMv8-M Baseline processor based device for the ARM Compiler</description>
+ <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
<require condition="ARMv8MBL"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MBL_LE_ARMCC">
- <description>ARMv8-M Baseline processor based device in little endian mode for the ARM Compiler</description>
+ <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
<require condition="ARMv8MBL_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MBL_BE_ARMCC">
- <description>ARMv8-M Baseline processor based device in big endian mode for the ARM Compiler</description>
+ <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
<require condition="ARMv8MBL_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_ARMCC">
- <description>ARMv8-M Mainline processor based device for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
<require condition="ARMv8MML"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_LE_ARMCC">
- <description>ARMv8-M Mainline processor based device in little endian mode for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
<require condition="ARMv8MML_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_BE_ARMCC">
- <description>ARMv8-M Mainline processor based device in big endian mode for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
<require condition="ARMv8MML_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_FP_ARMCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
<require condition="ARMv8MML_FP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_FP_LE_ARMCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
<require condition="ARMv8MML_FP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_FP_BE_ARMCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
<require condition="ARMv8MML_FP_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
- <description>ARMv8MML, no DSP, no FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_ARMCC">
- <description>ARMv8MML, DSP, no FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_ARMCC">
- <description>ARMv8MML, no DSP, SP FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
<require condition="ARMv8MML_NODSP_SP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_DSP_SP_ARMCC">
- <description>ARMv8MML, DSP, SP FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
<require condition="ARMv8MML_DSP_SP"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
- <description>ARMv8MML, little endian, no DSP, no FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
- <description>ARMv8MML, little endian, DSP, no FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
- <description>ARMv8MML, little endian, no DSP, SP FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
<require condition="ARMv8MML_NODSP_SP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_SP_LE_ARMCC">
- <description>ARMv8MML, little endian, DSP, SP FPU, ARM Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
<require condition="ARMv8MML_DSP_SP_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
@@ -1437,90 +1442,90 @@
</condition>
<condition id="ARMv8MBL_GCC">
- <description>ARMv8-M Baseline processor based device for the GCC Compiler</description>
+ <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
<require condition="ARMv8MBL"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MBL_LE_GCC">
- <description>ARMv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
+ <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
<require condition="ARMv8MBL_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MBL_BE_GCC">
- <description>ARMv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
+ <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
<require condition="ARMv8MBL_GCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_GCC">
- <description>ARMv8-M Mainline processor based device for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
<require condition="ARMv8MML"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_LE_GCC">
- <description>ARMv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
<require condition="ARMv8MML_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_BE_GCC">
- <description>ARMv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
<require condition="ARMv8MML_GCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_FP_GCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
<require condition="ARMv8MML_FP"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_FP_LE_GCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
<require condition="ARMv8MML_FP_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_FP_BE_GCC">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
<require condition="ARMv8MML_FP_GCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_GCC">
- <description>ARMv8MML, no DSP, no FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_GCC">
- <description>ARMv8MML, DSP, no FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_GCC">
- <description>ARMv8MML, no DSP, SP FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
<require condition="ARMv8MML_NODSP_SP"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_DSP_SP_GCC">
- <description>ARMv8MML, DSP, SP FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
<require condition="ARMv8MML_DSP_SP"/>
<require Tcompiler="GCC"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
- <description>ARMv8MML, little endian, no DSP, no FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
- <description>ARMv8MML, little endian, DSP, no FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_LE_GCC">
- <description>ARMv8MML, little endian, no DSP, SP FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
<require condition="ARMv8MML_NODSP_SP_GCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_SP_LE_GCC">
- <description>ARMv8MML, little endian, DSP, SP FPU, GCC Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
<require condition="ARMv8MML_DSP_SP_GCC"/>
<require Dendian="Little-endian"/>
</condition>
@@ -1750,90 +1755,90 @@
</condition>
<condition id="ARMv8MBL_IAR">
- <description>ARMv8-M Baseline processor based device for the IAR Compiler</description>
+ <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
<require condition="ARMv8MBL"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MBL_LE_IAR">
- <description>ARMv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
+ <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
<require condition="ARMv8MBL_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MBL_BE_IAR">
- <description>ARMv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
+ <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
<require condition="ARMv8MBL_IAR"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_IAR">
- <description>ARMv8-M Mainline processor based device for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
<require condition="ARMv8MML"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_LE_IAR">
- <description>ARMv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
<require condition="ARMv8MML_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_BE_IAR">
- <description>ARMv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
<require condition="ARMv8MML_IAR"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_FP_IAR">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
<require condition="ARMv8MML_FP"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_FP_LE_IAR">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
<require condition="ARMv8MML_FP_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_FP_BE_IAR">
- <description>ARMv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+ <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
<require condition="ARMv8MML_FP_IAR"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_IAR">
- <description>ARMv8MML, no DSP, no FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_IAR">
- <description>ARMv8MML, DSP, no FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_IAR">
- <description>ARMv8MML, no DSP, SP FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
<require condition="ARMv8MML_NODSP_SP"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_DSP_SP_IAR">
- <description>ARMv8MML, DSP, SP FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
<require condition="ARMv8MML_DSP_SP"/>
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
- <description>ARMv8MML, little endian, no DSP, no FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
<require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
- <description>ARMv8MML, little endian, DSP, no FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
<require condition="ARMv8MML_DSP_NOFPU_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_NODSP_SP_LE_IAR">
- <description>ARMv8MML, little endian, no DSP, SP FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
<require condition="ARMv8MML_NODSP_SP_IAR"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMv8MML_DSP_SP_LE_IAR">
- <description>ARMv8MML, little endian, DSP, SP FPU, IAR Compiler</description>
+ <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
<require condition="ARMv8MML_DSP_SP_IAR"/>
<require Dendian="Little-endian"/>
</condition>
@@ -1841,7 +1846,7 @@
<!-- conditions selecting single devices and CMSIS Core -->
<!-- used for component startup, GCC version is used for C-Startup -->
<condition id="ARMCM0 CMSIS">
- <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
@@ -1852,129 +1857,129 @@
</condition>
<condition id="ARMCM0+ CMSIS">
- <description>Generic ARM Cortex-M0+ device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0P*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM0+ CMSIS GCC">
- <description>Generic ARM Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
<require condition="ARMCM0+ CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCM3 CMSIS">
- <description>Generic ARM Cortex-M3 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM3"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM3 CMSIS GCC">
- <description>Generic ARM Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMCM3 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCM4 CMSIS">
- <description>Generic ARM Cortex-M4 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM4*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM4 CMSIS GCC">
- <description>Generic ARM Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMCM4 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCM7 CMSIS">
- <description>Generic ARM Cortex-M7 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM7*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM7 CMSIS GCC">
- <description>Generic ARM Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMCM7 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCM23 CMSIS">
- <description>Generic ARM Cortex-M23 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM23*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM23 CMSIS GCC">
- <description>Generic ARM Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMCM23 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCM33 CMSIS">
- <description>Generic ARM Cortex-M33 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM33*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM33 CMSIS GCC">
- <description>Generic ARM Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMCM33 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMSC000 CMSIS">
- <description>Generic ARM SC000 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC000"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC000 CMSIS GCC">
- <description>Generic ARM SC000 device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMSC000 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMSC300 CMSIS">
- <description>Generic ARM SC300 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC300"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC300 CMSIS GCC">
- <description>Generic ARM SC300 device startup and dependson CMSIS Core requiring GCC</description>
+ <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
<require condition="ARMSC300 CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMv8MBL CMSIS">
- <description>Generic ARM ARMv8MBL device startup and depends on CMSIS Core</description>
+ <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMv8MBL"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMv8MBL CMSIS GCC">
- <description>Generic ARM ARMv8MBL device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMv8MBL CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMv8MML CMSIS">
- <description>Generic ARM ARMv8MML device startup and depends on CMSIS Core</description>
+ <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMv8MML*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMv8MML CMSIS GCC">
- <description>Generic ARM ARMv8MML device startup and depends on CMSIS Core requiring GCC</description>
+ <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
<require condition="ARMv8MML CMSIS"/>
<require condition="GCC"/>
</condition>
<condition id="ARMCA5 CMSIS">
- <description>Generic ARM Cortex-A5 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA5"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA7 CMSIS">
- <description>Generic ARM Cortex-A7 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA7"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA9 CMSIS">
- <description>Generic ARM Cortex-A9 device startup and depends on CMSIS Core</description>
+ <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA9"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
@@ -2017,7 +2022,7 @@
<require Cclass="Device" Cgroup="Startup"/>
</condition>
<condition id="RTOS2 RTX5 v7-A">
- <description>Components required for RTOS2 RTX5 v7-A</description>
+ <description>Components required for RTOS2 RTX5 on Armv7-A</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
@@ -2082,7 +2087,7 @@
<!-- CMSIS-Startup components -->
<!-- Cortex-M0 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M0 device</description>
+ <description>System and Startup for Generic Arm Cortex-M0 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
@@ -2095,7 +2100,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M0 device</description>
+ <description>System and Startup for Generic Arm Cortex-M0 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
@@ -2108,7 +2113,7 @@
<!-- Cortex-M0+ -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS">
- <description>System and Startup for Generic ARM Cortex-M0+ device</description>
+ <description>System and Startup for Generic Arm Cortex-M0+ device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
@@ -2121,7 +2126,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M0+ device</description>
+ <description>System and Startup for Generic Arm Cortex-M0+ device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
@@ -2134,7 +2139,7 @@
<!-- Cortex-M3 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M3 device</description>
+ <description>System and Startup for Generic Arm Cortex-M3 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
@@ -2147,7 +2152,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M3 device</description>
+ <description>System and Startup for Generic Arm Cortex-M3 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
@@ -2160,7 +2165,7 @@
<!-- Cortex-M4 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M4 device</description>
+ <description>System and Startup for Generic Arm Cortex-M4 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM4/Include/"/>
@@ -2173,7 +2178,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M4 device</description>
+ <description>System and Startup for Generic Arm Cortex-M4 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM4/Include/"/>
@@ -2186,7 +2191,7 @@
<!-- Cortex-M7 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M7 device</description>
+ <description>System and Startup for Generic Arm Cortex-M7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM7/Include/"/>
@@ -2199,7 +2204,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M7 device</description>
+ <description>System and Startup for Generic Arm Cortex-M7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM7/Include/"/>
@@ -2212,7 +2217,7 @@
<!-- Cortex-M23 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M23 device</description>
+ <description>System and Startup for Generic Arm Cortex-M23 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
@@ -2227,7 +2232,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M23 device</description>
+ <description>System and Startup for Generic Arm Cortex-M23 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
@@ -2242,7 +2247,7 @@
<!-- Cortex-M33 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS">
- <description>System and Startup for Generic ARM Cortex-M33 device</description>
+ <description>System and Startup for Generic Arm Cortex-M33 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
@@ -2257,7 +2262,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
- <description>System and Startup for Generic ARM Cortex-M33 device</description>
+ <description>System and Startup for Generic Arm Cortex-M33 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
@@ -2272,7 +2277,7 @@
<!-- Cortex-SC000 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS">
- <description>System and Startup for Generic ARM SC000 device</description>
+ <description>System and Startup for Generic Arm SC000 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
@@ -2285,7 +2290,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
- <description>System and Startup for Generic ARM SC000 device</description>
+ <description>System and Startup for Generic Arm SC000 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
@@ -2298,7 +2303,7 @@
<!-- Cortex-SC300 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS">
- <description>System and Startup for Generic ARM SC300 device</description>
+ <description>System and Startup for Generic Arm SC300 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
@@ -2311,7 +2316,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
- <description>System and Startup for Generic ARM SC300 device</description>
+ <description>System and Startup for Generic Arm SC300 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
@@ -2324,7 +2329,7 @@
<!-- ARMv8MBL -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS">
- <description>System and Startup for Generic ARM ARMv8MBL device</description>
+ <description>System and Startup for Generic Armv8-M Baseline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
@@ -2338,7 +2343,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
- <description>System and Startup for Generic ARM ARMv8MBL device</description>
+ <description>System and Startup for Generic Armv8-M Baseline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
@@ -2353,7 +2358,7 @@
<!-- ARMv8MML -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS">
- <description>System and Startup for Generic ARM ARMv8MML device</description>
+ <description>System and Startup for Generic Armv8-M Mainline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
@@ -2367,7 +2372,7 @@
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
- <description>System and Startup for Generic ARM ARMv8MML device</description>
+ <description>System and Startup for Generic Armv8-M Mainline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
@@ -2382,7 +2387,7 @@
<!-- Cortex-A5 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMCA5 CMSIS">
- <description>System and Startup for Generic ARM Cortex-A5 device</description>
+ <description>System and Startup for Generic Arm Cortex-A5 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA5/Include/"/>
@@ -2405,7 +2410,7 @@
<!-- Cortex-A7 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMCA7 CMSIS">
- <description>System and Startup for Generic ARM Cortex-A7 device</description>
+ <description>System and Startup for Generic Arm Cortex-A7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA7/Include/"/>
@@ -2427,7 +2432,7 @@
<!-- Cortex-A9 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCA9 CMSIS">
- <description>System and Startup for Generic ARM Cortex-A9 device</description>
+ <description>System and Startup for Generic Arm Cortex-A9 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA9/Include/"/>
@@ -2662,7 +2667,7 @@
<!-- CMSIS-RTOS2 Keil RTX5 component -->
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 Lib">
- <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and ARMv8-M (Library)</description>
+ <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -2731,12 +2736,12 @@
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
- <description>CMSIS-RTOS2 RTX5 for ARMv8-M Non-Secure Domain (Library)</description>
+ <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
- #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 ARMv8-M Non-secure domain */
+ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
@@ -2782,7 +2787,7 @@
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5">
- <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and ARMv8-M (Source)</description>
+ <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -2871,7 +2876,7 @@
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 v7-A">
- <description>CMSIS-RTOS2 RTX5 for ARMv7-A (Source)</description>
+ <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
@@ -2928,13 +2933,13 @@
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
- <description>CMSIS-RTOS2 RTX5 for ARMv8-M Non-Secure Domain (Source)</description>
+ <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
- #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 ARMv8-M Non-secure domain */
+ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
diff --git a/CMSIS/Core/Include/cmsis_armcc.h b/CMSIS/Core/Include/cmsis_armcc.h
index 1a69d61..093d35b 100644
--- a/CMSIS/Core/Include/cmsis_armcc.h
+++ b/CMSIS/Core/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
- * @brief CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version V5.0.3
- * @date 01. December 2017
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -27,7 +27,7 @@
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
diff --git a/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS/Core/Include/cmsis_armclang.h
index a049ca6..5c4c20e 100644
--- a/CMSIS/Core/Include/cmsis_armclang.h
+++ b/CMSIS/Core/Include/cmsis_armclang.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang.h
- * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version V5.0.3
- * @date 27. March 2017
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -30,7 +30,7 @@
#pragma clang system_header /* treat file as system include file */
#ifndef __ARM_COMPAT_H
-#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif
/* CMSIS compiler specific defines */
diff --git a/CMSIS/Core/Include/cmsis_compiler.h b/CMSIS/Core/Include/cmsis_compiler.h
index db16aed..94212eb 100644
--- a/CMSIS/Core/Include/cmsis_compiler.h
+++ b/CMSIS/Core/Include/cmsis_compiler.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
- * @version V5.0.3
- * @date 01. December 2017
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -28,14 +28,14 @@
#include <stdint.h>
/*
- * ARM Compiler 4/5
+ * Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
- * ARM Compiler 6 (armclang)
+ * Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
@@ -56,7 +56,7 @@
/*
- * TI ARM Compiler
+ * TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h
index bbe9707..edcaee3 100644
--- a/CMSIS/Core/Include/cmsis_iccarm.h
+++ b/CMSIS/Core/Include/cmsis_iccarm.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
- * @brief CMSIS compiler ICCARM (IAR compiler) header file
- * @version V5.0.4
- * @date 01. December 2017
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.5
+ * @date 10. January 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
-// Copyright (c) 2017 IAR Systems
+// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
diff --git a/CMSIS/Core/Include/core_armv8mbl.h b/CMSIS/Core/Include/core_armv8mbl.h
index dcf1b6e..47a3989 100644
--- a/CMSIS/Core/Include/core_armv8mbl.h
+++ b/CMSIS/Core/Include/core_armv8mbl.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_armv8mbl.h
- * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 09. August 2017
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -1239,8 +1239,8 @@
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
@@ -1266,7 +1266,7 @@
#define NVIC_USER_IRQ_OFFSET 16
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
diff --git a/CMSIS/Core/Include/core_armv8mml.h b/CMSIS/Core/Include/core_armv8mml.h
index a17f625..0951a1f 100644
--- a/CMSIS/Core/Include/core_armv8mml.h
+++ b/CMSIS/Core/Include/core_armv8mml.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_armv8mml.h
- * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 09. August 2017
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -62,7 +62,7 @@
#include "cmsis_version.h"
-/* CMSIS ARMv8MML definitions */
+/* CMSIS Armv8MML definitions */
#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
diff --git a/CMSIS/Core/Include/core_cm0.h b/CMSIS/Core/Include/core_cm0.h
index c6d2d98..a3f1b9a 100644
--- a/CMSIS/Core/Include/core_cm0.h
+++ b/CMSIS/Core/Include/core_cm0.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V5.0.2
- * @date 19. April 2017
+ * @version V5.0.3
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -599,7 +599,7 @@
#define NVIC_USER_IRQ_OFFSET 16
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
diff --git a/CMSIS/Core/Include/core_cm0plus.h b/CMSIS/Core/Include/core_cm0plus.h
index de557de..f8f30c3 100644
--- a/CMSIS/Core/Include/core_cm0plus.h
+++ b/CMSIS/Core/Include/core_cm0plus.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 09. August 2017
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -717,7 +717,7 @@
#define NVIC_USER_IRQ_OFFSET 16
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
diff --git a/CMSIS/Core/Include/core_cm23.h b/CMSIS/Core/Include/core_cm23.h
index 85f4f6c..7d1d478 100644
--- a/CMSIS/Core/Include/core_cm23.h
+++ b/CMSIS/Core/Include/core_cm23.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm23.h
* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 09. August 2017
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -1269,7 +1269,7 @@
#define NVIC_USER_IRQ_OFFSET 16
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
diff --git a/CMSIS/Core/Include/core_sc000.h b/CMSIS/Core/Include/core_sc000.h
index c4cd5e7..9aab5e5 100644
--- a/CMSIS/Core/Include/core_sc000.h
+++ b/CMSIS/Core/Include/core_sc000.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V5.0.2
- * @date 19. April 2017
+ * @version V5.0.3
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -727,7 +727,7 @@
#define NVIC_USER_IRQ_OFFSET 16
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
diff --git a/CMSIS/Core/Include/core_sc300.h b/CMSIS/Core/Include/core_sc300.h
index d39bf21..a569ef2 100644
--- a/CMSIS/Core/Include/core_sc300.h
+++ b/CMSIS/Core/Include/core_sc300.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V5.0.2
- * @date 19. April 2017
+ * @version V5.0.3
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Core/Include/mpu_armv7.h b/CMSIS/Core/Include/mpu_armv7.h
index 14ad8c4..aa180c9 100644
--- a/CMSIS/Core/Include/mpu_armv7.h
+++ b/CMSIS/Core/Include/mpu_armv7.h
@@ -1,11 +1,11 @@
/******************************************************************************
* @file mpu_armv7.h
- * @brief CMSIS MPU API for ARMv7 MPU
- * @version V5.0.3
- * @date 09. August 2017
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Core/Include/mpu_armv8.h b/CMSIS/Core/Include/mpu_armv8.h
index d7a4646..0ccfc74 100644
--- a/CMSIS/Core/Include/mpu_armv8.h
+++ b/CMSIS/Core/Include/mpu_armv8.h
@@ -1,11 +1,11 @@
/******************************************************************************
* @file mpu_armv8.h
- * @brief CMSIS MPU API for ARMv8 MPU
- * @version V5.0.3
- * @date 09. August 2017
+ * @brief CMSIS MPU API for Armv8-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Core/Include/tz_context.h b/CMSIS/Core/Include/tz_context.h
index c3a9d8b..0d09749 100644
--- a/CMSIS/Core/Include/tz_context.h
+++ b/CMSIS/Core/Include/tz_context.h
@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,18 +20,7 @@
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date: 21. September 2016
- * $Revision: V1.0
- *
- * Project: TrustZone for ARMv8-M
- * Title: Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- * Initial Release
- *---------------------------------------------------------------------------*/
+ */
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
diff --git a/CMSIS/Core/Template/ARMv8-M/main_s.c b/CMSIS/Core/Template/ARMv8-M/main_s.c
index 449c576..273607b 100644
--- a/CMSIS/Core/Template/ARMv8-M/main_s.c
+++ b/CMSIS/Core/Template/ARMv8-M/main_s.c
@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file main_s.c
+ * @brief Code template for secure main function
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,17 +20,8 @@
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 15. October 2016
- * $Revision: 1.1.0
- *
- * Project: TrustZone for ARMv8-M
- * Title: Code template for secure main function
- *
- *---------------------------------------------------------------------------*/
-
+ */
+
/* Use CMSE intrinsics */
#include <arm_cmse.h>
diff --git a/CMSIS/Core/Template/ARMv8-M/tz_context.c b/CMSIS/Core/Template/ARMv8-M/tz_context.c
index f315289..e2e8294 100644
--- a/CMSIS/Core/Template/ARMv8-M/tz_context.c
+++ b/CMSIS/Core/Template/ARMv8-M/tz_context.c
@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file tz_context.c
+ * @brief Context Management for Armv8-M TrustZone - Sample implementation
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,17 +20,8 @@
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date: 15. October 2016
- * $Revision: 1.1.0
- *
- * Project: TrustZone for ARMv8-M
- * Title: Context Management for ARMv8-M TrustZone - Sample implementation
- *
- *---------------------------------------------------------------------------*/
-
+ */
+
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
diff --git a/CMSIS/Core_A/Include/cmsis_armcc.h b/CMSIS/Core_A/Include/cmsis_armcc.h
index cef7694..7c4c948 100644
--- a/CMSIS/Core_A/Include/cmsis_armcc.h
+++ b/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.1
- * @date 07. Sep 2017
+ * @version V1.0.2
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -26,7 +26,7 @@
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
diff --git a/CMSIS/Core_A/Include/cmsis_armclang.h b/CMSIS/Core_A/Include/cmsis_armclang.h
index 8853836..5883364 100644
--- a/CMSIS/Core_A/Include/cmsis_armclang.h
+++ b/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.1
- * @date 07. Sep 2017
+ * @version V1.0.2
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -28,7 +28,7 @@
#pragma clang system_header /* treat file as system include file */
#ifndef __ARM_COMPAT_H
-#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif
/* CMSIS compiler specific defines */
diff --git a/CMSIS/Core_A/Include/cmsis_compiler.h b/CMSIS/Core_A/Include/cmsis_compiler.h
index d1ef182..b00c6ba 100644
--- a/CMSIS/Core_A/Include/cmsis_compiler.h
+++ b/CMSIS/Core_A/Include/cmsis_compiler.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.1
- * @date 01. December 2017
+ * @version V1.0.2
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -28,14 +28,14 @@
#include <stdint.h>
/*
- * ARM Compiler 4/5
+ * Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
- * ARM Compiler 6 (armclang)
+ * Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
@@ -56,7 +56,7 @@
/*
- * TI ARM Compiler
+ * TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
diff --git a/CMSIS/Core_A/Include/cmsis_iccarm.h b/CMSIS/Core_A/Include/cmsis_iccarm.h
index beddfe8..a441e2d 100644
--- a/CMSIS/Core_A/Include/cmsis_iccarm.h
+++ b/CMSIS/Core_A/Include/cmsis_iccarm.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
- * @brief CMSIS compiler ICCARM (IAR compiler) header file
- * @version V5.0.4
- * @date 01. December 2017
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.5
+ * @date 10. January 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
-// Copyright (c) 2017 IAR Systems
+// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
diff --git a/CMSIS/DSP/Include/arm_math.h b/CMSIS/DSP/Include/arm_math.h
index fcaf797..ea9dd26 100644
--- a/CMSIS/DSP/Include/arm_math.h
+++ b/CMSIS/DSP/Include/arm_math.h
@@ -1,15 +1,11 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_math.h
- * Description: Public header file for CMSIS DSP Library
- *
- * $Date: 19. September 2017
- * $Revision: V.1.5.2
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.5.3
+ * @date 10. January 2018
+ ******************************************************************************/
/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -68,19 +64,19 @@
* - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
* - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
* - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
- * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
- * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
- * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
- * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
- * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
*
* The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
* Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
* public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
- * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
*
*
* Examples
@@ -91,22 +87,22 @@
* Toolchain Support
* ------------
*
- * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library has been developed and tested with MDK version 5.14.0.0
* The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
*
* Building the Library
* ------------
*
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
* - arm_cortexM_math.uvprojx
*
*
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
*
- * Pre-processor Macros
+ * Preprocessor Macros
* ------------
*
- * Each library project have differant pre-processor macros.
+ * Each library project have different preprocessor macros.
*
* - UNALIGNED_SUPPORT_DISABLE:
*
@@ -132,8 +128,8 @@
*
* - ARM_MATH_ARMV8MxL:
*
- * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MML for building library
- * on ARMv8M Mainline target.
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
*
* - __FPU_PRESENT:
*
@@ -141,7 +137,7 @@
*
* - __DSP_PRESENT:
*
- * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
*
* <hr>
* CMSIS-DSP in ARM::CMSIS Pack
@@ -163,7 +159,7 @@
* Copyright Notice
* ------------
*
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
*/
@@ -243,9 +239,9 @@
*
* \par Size Checking
* By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
+ * output matrices. For example, the matrix addition function verifies that the
* two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
+ * columns. If the size check fails the functions return:
* <pre>
* ARM_MATH_SIZE_MISMATCH
* </pre>
@@ -259,9 +255,9 @@
* ARM_MATH_MATRIX_CHECK
* </pre>
* within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
+ * and size checking is enabled. By changing the project settings and
* undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
+ * run a bit faster. With size checking disabled the functions always
* return <code>ARM_MATH_SUCCESS</code>.
*/
diff --git a/CMSIS/DoxyGen/Core/src/Overview.txt b/CMSIS/DoxyGen/Core/src/Overview.txt
index e8488bc..ffdc9fb 100644
--- a/CMSIS/DoxyGen/Core/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core/src/Overview.txt
@@ -12,8 +12,8 @@
The following sections provide details about the CMSIS-Core (Cortex-M):
- \ref using_pg describes the project setup and shows a simple program example.
- - \ref using_TrustZone_pg "Using TrustZone® for ARMv8-M" describes how to use the security extensions available in the ARMv8-M architecture.
- - \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by ARM to silicon vendor devices.
+ - \ref using_TrustZone_pg "Using TrustZone® for Armv8-M" describes how to use the security extensions available in the Armv8-M architecture.
+ - \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
- \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
- <a href="Modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
- <a href="Annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
@@ -28,7 +28,7 @@
|------------------------------|------------------------------------------------------------------------|
|\b CMSIS\\Documentation\\Core | This documentation |
|\b CMSIS\\Core\\Include | CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) |
-|\b Device | \ref using_ARM_pg "ARM reference implementations" of Cortex-M devices |
+|\b Device | \ref using_ARM_pg "Arm reference implementations" of Cortex-M devices |
|\b Device\\\_Template_Vendor | \ref templates_pg for extension by silicon vendors |
<hr>
@@ -36,39 +36,39 @@
\section ref_v6-v8M Processor Support
CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and
-the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>ARMv8-M architecture</b></a> including security extensions.
+the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.
\subsection ref_man_sec Cortex-M Reference Manuals
The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (ARMv6-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (ARMv6-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (ARMv7-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (ARMv7-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)
The \b Cortex-M23 and \b Cortex-M33 are described with Technical Reference Manuals that are available here:
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (ARMv8-M baseline architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (ARMv8-M mainline architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)
-\subsection ARMv8M ARMv8-M Architecture
+\subsection ARMv8M Armv8-M Architecture
-ARMv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
-Both ARMv8-M profiles are supported by CMSIS.
+Armv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
+Both Armv8-M profiles are supported by CMSIS.
-The ARMv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>ARMv8-M Architecture Reference Manual</b></a>.
+The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.
<hr>
\section tested_tools_sec Tested and Verified Toolchains
-The \ref templates_pg supplied by ARM have been tested and verified with the following toolchains:
- - ARM: ARM Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, ARMv8-M)
- - ARM: ARM Compiler 6.9
- - ARM: ARM Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, ARMv8-M)
- - GNU: GNU Tools for ARM Embedded 6.3.1 20170620
- - IAR: IAR ANSI C/C++ Compiler for ARM 8.20.1.14183
+The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
+ - Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
+ - Arm: Arm Compiler 6.9
+ - Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
+ - GNU: GNU Tools for Arm Embedded 6.3.1 20170620
+ - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
<hr>
*/
@@ -173,7 +173,7 @@
Corrected: DoxyGen function parameter comments.\n
Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).\n
Corrected: GCC toolchain: suppressed irrelevant compiler warnings.\n
- Added: Support files for ARM Compiler v6 (cmsis_armcc_v6.h).
+ Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
</td>
</tr>
<tr>
diff --git a/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt b/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt
index bf83f59..5bd9745 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt
@@ -12,41 +12,41 @@
/**
\def __ARM_ARCH_6M__
-\brief Set to 1 when generating code for ARMv6-M (Cortex-M0, Cortex-M1)
+\brief Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1)
\details
-The <b>\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the ARMv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
+The <b>\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
*/
#define __ARM_ARCH_6M__
/**
\def __ARM_ARCH_7M__
-\brief Set to 1 when generating code for ARMv7-M (Cortex-M3)
+\brief Set to 1 when generating code for Armv7-M (Cortex-M3)
\details
-The <b>\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the ARMv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
+The <b>\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
*/
#define __ARM_ARCH_7M__
/**
\def __ARM_ARCH_7EM__
-\brief Set to 1 when generating code for ARMv7-M (Cortex-M4) with FPU
+\brief Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU
\details
-The <b>\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the ARMv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU
+The <b>\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU
*/
#define __ARM_ARCH_7EM__
/**
\def __ARM_ARCH_8M_BASE__
-\brief Set to 1 when generating code for ARMv8-M Baseline
+\brief Set to 1 when generating code for Armv8-M Baseline
\details
-The <b>\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the ARMv8-M architecture baseline variant.
+The <b>\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the Armv8-M architecture baseline variant.
*/
#define __ARM_ARCH_8M_BASE__
/**
\def __ARM_ARCH_8M_MAIN__
-\brief Set to 1 when generating code for ARMv8-M Mainline
+\brief Set to 1 when generating code for Armv8-M Mainline
\details
-The <b>\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the ARMv8-M architecture mainline variant.
+The <b>\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the Armv8-M architecture mainline variant.
*/
#define __ARM_ARCH_8M_MAIN__
@@ -229,7 +229,7 @@
It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
@@ -250,7 +250,7 @@
\brief Pointer for unaligned read of a uint16_t variable.
\details
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
@@ -271,7 +271,7 @@
\brief Pointer for unaligned write of a uint16_t variable.
\details
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
@@ -292,7 +292,7 @@
\brief Pointer for unaligned read of a uint32_t variable.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
@@ -313,7 +313,7 @@
\brief Pointer for unaligned write of a uint32_t variable.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
diff --git a/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt b/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt
index 9d89739..6667748 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt
@@ -684,49 +684,49 @@
/**
\brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __get_PSPLIM(void);
/**
\brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
void __set_PSPLIM(uint32_t ProcStackPtrLimit);
/**
\brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __get_MSPLIM(void);
/**
\brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
__set_MSPLIM(uint32_t MainStackPtrLimit);
diff --git a/CMSIS/DoxyGen/Core/src/Ref_FPU.txt b/CMSIS/DoxyGen/Core/src/Ref_FPU.txt
index e43757c..b53d09b 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_FPU.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_FPU.txt
@@ -5,7 +5,7 @@
Some Cortex-M processors include optional floating-point arithmetic functionality, with support
for single and double-precision arithmetic.
The Cortex-M processor with FPU is an implementation of the single-precision and
-double-precision variant of the ARMv7-M Architecture with Floating-Point Extension (FPv5).
+double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5).
@{
*/
diff --git a/CMSIS/DoxyGen/Core/src/Ref_MPU.txt b/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
index 91c7570..d9105fb 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
@@ -1,5 +1,5 @@
/**
-\defgroup mpu_functions MPU Functions for ARMv7-M
+\defgroup mpu_functions MPU Functions for Armv7-M
\brief Functions that relate to the Memory Protection Unit.
\details
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.
@@ -247,10 +247,10 @@
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------ |
| [31:24] | - | Reserved. |
-| [23:16] | IREGION | Instruction region. RAZ. ARMv7-M only supports a unified MPU. |
+| [23:16] | IREGION | Instruction region. RAZ. Armv7-M only supports a unified MPU. |
| [15:8] | DREGION | Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. |
| [7:1] | - | Reserved. |
-| [0] | SEPARATE | Indicates support for separate instruction and data address maps. RAZ. ARMv7-M only supports a unified MPU. |
+| [0] | SEPARATE | Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. |
\var MPU_Type::CTRL
Enables the MPU, and when the MPU is enabled, controls whether the default memory map
diff --git a/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt b/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt
index f685969..ad3f87f 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt
@@ -5,7 +5,7 @@
\details
This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).
-ARM provides a template file <strong>startup_<em>device</em></strong> for each supported
+Arm provides a template file <strong>startup_<em>device</em></strong> for each supported
compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific
interrupt handlers. Each interrupt handler is defined as a <strong><em>weak</em></strong> function
to an dummy handler. These interrupt handlers can be used directly in application software
@@ -24,8 +24,8 @@
<th>M7</th>
<th>SC000</th>
<th>SC300</th>
- <th>ARMv8-M<br/>Baseline</th>
- <th>ARMv8-M<br/>Mainline</th>
+ <th>Armv8-M<br/>Baseline</th>
+ <th>Armv8-M<br/>Mainline</th>
<th>Description</th>
</tr>
<tr>
@@ -179,7 +179,7 @@
<b>__Vectors</b> is the address of the vector table in the startup code and the
register <b>SCB->VTOR</b> holds the start address of the vector table.
-An ARMv8-M implementation with TrustZone provides two vector tables:
+An Armv8-M implementation with TrustZone provides two vector tables:
- vector table for Secure handlers
- vector table for Non-Secure handlers
@@ -189,7 +189,7 @@
--------------------
At the beginning of the vector table, the initial stack value and the
exception vectors of the processor are defined. The vector table below
-shows the exception vectors of a ARMv8-M Mainline processor. Other processor
+shows the exception vectors of a Armv8-M Mainline processor. Other processor
variants may have fewer vectors.
\code
@@ -390,7 +390,7 @@
MemoryManagement_IRQn = -12, ///< Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]
BusFault_IRQn = -11, ///< Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]
UsageFault_IRQn = -10, ///< Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]
- SecureFault_IRQn = -9, ///< Exception 7: Secure Fault Interrupt [only on ARMv8-M]
+ SecureFault_IRQn = -9, ///< Exception 7: Secure Fault Interrupt [only on Armv8-M]
SVCall_IRQn = -5, ///< Exception 11: SV Call Interrupt
DebugMonitor_IRQn = -4, ///< Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]
PendSV_IRQn = -2, ///< Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]
@@ -787,7 +787,7 @@
- 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
\remarks
- - Only available for ARMv8-M in secure state.
+ - Only available for Armv8-M in secure state.
\sa
- \ref NVIC_ClearTargetState; NVIC_SetTargetState;
@@ -802,7 +802,7 @@
- 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
\remarks
- - Only available for ARMv8-M in secure state.
+ - Only available for Armv8-M in secure state.
\sa
- \ref NVIC_ClearTargetState; NVIC_GetTargetState;
@@ -817,7 +817,7 @@
- 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
\remarks
- - Only available for ARMv8-M in secure state.
+ - Only available for Armv8-M in secure state.
\sa
- \ref NVIC_GetTargetState; NVIC_SetTargetState;
diff --git a/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt b/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt
index 186cc19..30da540 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt
@@ -4,7 +4,7 @@
\defgroup system_init_gr System and Clock Configuration
\brief Functions for system and clock setup available in system_<i>device</i>.c.
\details
-ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
+Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
the silicon vendor to match their actual device. As a <b>minimum requirement</b>,
this file must provide:
- A device-specific system configuration function, \ref SystemInit().
diff --git a/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt b/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt
index 7d9db8d..7394d2c 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt
@@ -1,10 +1,10 @@
/**
-\defgroup trustzone_functions TrustZone for ARMv8-M
-\brief Functions that related to optional ARMv8-M security extension
+\defgroup trustzone_functions TrustZone for Armv8-M
+\brief Functions that related to optional Armv8-M security extension
@{
\details
-The ARMv8-M architecture has optional ARMv8-M security extension based on ARM TrustZone technology.
-To access ARM TrustZone extensions for ARMv8-M additional CMSIS functions are provided:
+The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology.
+To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:
- \ref coreregister_trustzone_functions
- \ref nvic_trustzone_functions
- \ref systick_trustzone_functions
@@ -14,7 +14,7 @@
/**
\defgroup coreregister_trustzone_functions Core Register Access Functions
- \brief Core register Access functions related to TrustZone for ARMv8-M.
+ \brief Core register Access functions related to TrustZone for Armv8-M.
@{
*/
@@ -142,7 +142,7 @@
/**
\brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
@@ -152,7 +152,7 @@
/**
\brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
@@ -162,7 +162,7 @@
/**
\brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
@@ -172,7 +172,7 @@
/**
\brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
@@ -186,7 +186,7 @@
/**
\defgroup nvic_trustzone_functions NVIC Functions
- \brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for ARMv8-M
+ \brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M
@{
*/
@@ -198,7 +198,7 @@
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
- \note Only available for ARMv8-M Mainline.
+ \note Only available for Armv8-M Mainline.
\sa
- \ref NVIC_SetPriorityGrouping
*/
@@ -208,7 +208,7 @@
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- \note Only available for ARMv8-M Mainline.
+ \note Only available for Armv8-M Mainline.
\sa
- \ref NVIC_GetPriorityGrouping
*/
@@ -314,7 +314,7 @@
/**
\defgroup systick_trustzone_functions SysTick Functions
- \brief SysTick functions related to TrustZone for ARMv8-M.
+ \brief SysTick functions related to TrustZone for Armv8-M.
@{
*/
@@ -340,7 +340,7 @@
/**
\defgroup sau_trustzone_functions SAU Functions
- \brief Secure Attribution Unit (SAU) functions related to TrustZone for ARMv8-M.
+ \brief Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.
@{
\details
The Secure Attribution Unit (SAU) functions SAU
@@ -383,7 +383,7 @@
/**
\defgroup context_trustzone_functions RTOS Context Management
- \brief RTOS Thread Context Management for ARMv8-M TrustZone.
+ \brief RTOS Thread Context Management for Armv8-M TrustZone.
@{
\details The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to \ref RTOS_TrustZone.
*/
diff --git a/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt b/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt
index 77a4875..055015b 100644
--- a/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt
+++ b/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt
@@ -7,9 +7,9 @@
Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions.
\note
-When using the ARM Compiler Toolchain the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler: \ref __RRX, <Bruno: add more...>.
+When using the Arm Compiler Toolchain the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler: \ref __RRX, <Bruno: add more...>.
The usage of the Embedded Assembler can be disabled by with <b><i>define __NO_EMBEDDED_ASM</i></b>. This avoids potential side effects of the Embedded Assembler.
-Refer to <b>Compiler User Guide - Using the Inline and Embedded Assemblers of the ARM Compiler</b> for more information.
+Refer to <b>Compiler User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information.
*/
/**************************************************************************************************/
@@ -260,7 +260,7 @@
This function counts the number of leading zeros of a data value.
- On ARMv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
+ On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
instruction and thus __CLZ is implemented in software.
\param [in] value Value to count the leading zeros
@@ -352,7 +352,7 @@
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint8_t __LDAB(volatile uint8_t *ptr);
@@ -361,7 +361,7 @@
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint16_t __LDAH(volatile uint16_t *ptr);
@@ -370,7 +370,7 @@
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __LDA(volatile uint32_t *ptr);
@@ -379,7 +379,7 @@
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
void __STLB(uint8_t value, volatile uint8_t *ptr);
@@ -388,7 +388,7 @@
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
void __STLH(uint16_t value, volatile uint16_t *ptr);
@@ -397,7 +397,7 @@
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
void __STL(uint32_t value, volatile uint32_t *ptr);
@@ -406,7 +406,7 @@
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint8_t __LDAEXB(volatile uint32_t *ptr);
@@ -415,7 +415,7 @@
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint16_t __LDAEXH(volatile uint32_t *ptr);
@@ -424,7 +424,7 @@
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __LDAEX(volatile uint32_t *ptr);
@@ -435,7 +435,7 @@
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
@@ -446,7 +446,7 @@
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
@@ -457,7 +457,7 @@
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
- \note Only availabe for ARMv8-M Architecture.
+ \note Only availabe for Armv8-M Architecture.
*/
uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr);
diff --git a/CMSIS/DoxyGen/Core/src/Template.txt b/CMSIS/DoxyGen/Core/src/Template.txt
index 8427bce..8195755 100644
--- a/CMSIS/DoxyGen/Core/src/Template.txt
+++ b/CMSIS/DoxyGen/Core/src/Template.txt
@@ -3,7 +3,7 @@
\details
-ARM supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors.
+Arm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors.
Refer to the list of \ref tested_tools_sec for compliance.
@@ -18,7 +18,7 @@
\section CMSIS_Processor_files CMSIS-Core Processor Files
-The CMSIS-Core processor files provided by ARM are in the directory .\\CMSIS\\Core\\Include. These header files define all processor specific attributes do not need any modifications.
+The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core\\Include. These header files define all processor specific attributes do not need any modifications.
The <b>core_<cpu>.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:
Header File | Processor
@@ -32,8 +32,8 @@
core_cm33.h | for the Cortex-M33 processor
core_sc000.h | for the SecurCore SC000 processor
core_sc300.h | for the SecurCore SC300 processor
-core_armv8mbl.h | for the ARMv8-M Baseline processor
-core_armv8mml.h | for the ARMv8-M Mainline processor
+core_armv8mbl.h | for the Armv8-M Baseline processor
+core_armv8mml.h | for the Armv8-M Mainline processor
\section device_examples Device Examples
@@ -59,13 +59,13 @@
ARM Cortex-M33 | ARMCM33_DSP_FP_TZ | Cortex-M23 based device with TrustZone, SIMD, FPU
ARM SC000 | ARM SC000 | SC000 based device
ARM SC300 | ARM SC300 | SC300 based device
-ARMv8-M Baseline | ARMv8MBL | ARMv8-M Baseline based device with TrustZone
-ARMv8-M Mainline | ARMv8MML | ARMv8-M Mainline based device with TrustZone
-ARMv8-M Mainline | ARMv8MML_DP | ARMv8-M Mainline based device with TrustZone and double precision FPU
-ARMv8-M Mainline | ARMv8MML_SP | ARMv8-M Mainline based device with TrustZone and single precision FPU
-ARMv8-M Mainline | ARMv8MML_DSP | ARMv8-M Mainline based device with TrustZone and SIMD
-ARMv8-M Mainline | ARMv8MML_DSP_DP | ARMv8-M Mainline based device with TrustZone, SIMD, and double precision FPU
-ARMv8-M Mainline | ARMv8MML_DSP_SP | ARMv8-M Mainline based device with TrustZone, SIMD, and single precision FPU
+ARMv8-M Baseline | ARMv8MBL | Armv8-M Baseline based device with TrustZone
+ARMv8-M Mainline | ARMv8MML | Armv8-M Mainline based device with TrustZone
+ARMv8-M Mainline | ARMv8MML_DP | Armv8-M Mainline based device with TrustZone and double precision FPU
+ARMv8-M Mainline | ARMv8MML_SP | Armv8-M Mainline based device with TrustZone and single precision FPU
+ARMv8-M Mainline | ARMv8MML_DSP | Armv8-M Mainline based device with TrustZone and SIMD
+ARMv8-M Mainline | ARMv8MML_DSP_DP | Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU
+ARMv8-M Mainline | ARMv8MML_DSP_SP | Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU
\section template_files_sec Template Files
@@ -83,11 +83,11 @@
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\ARM\\startup_Device.s</td>
- <td>Startup file template for ARM C/C++ Compiler.</td>
+ <td>Startup file template for Arm C/C++ Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\GCC\\startup_Device.s</td>
- <td>Startup file template for GNU GCC ARM Embedded Compiler.</td>
+ <td>Startup file template for GNU GCC Arm Embedded Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\IAR\\startup_Device.s</td>
@@ -203,7 +203,7 @@
\section startup_s_sec startup_Device.s Template File
-An ARM Compiler \ref startup_s_sec for an ARMv7-M processor like Cortex-M3 is shown below.
+An Arm Compiler \ref startup_s_sec for an Armv7-M processor like Cortex-M3 is shown below.
The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
\verbinclude "Source\ARM\startup_Device.s"
@@ -827,7 +827,7 @@
/**
\page partition_h_pg System Partition Header File partition_<device>.h
-The \ref partition_h_pg contains the initial setup of the TrustZone hardware in an ARMv8-M system.
+The \ref partition_h_pg contains the initial setup of the TrustZone hardware in an Armv8-M system.
The function \ref TZ_SAU_Setup is call from \ref SystemInit and uses the settings in this file to
initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS).
The following initializations are performed:
diff --git a/CMSIS/DoxyGen/Core/src/Using.txt b/CMSIS/DoxyGen/Core/src/Using.txt
index 536daa9..466407a 100644
--- a/CMSIS/DoxyGen/Core/src/Using.txt
+++ b/CMSIS/DoxyGen/Core/src/Using.txt
@@ -35,7 +35,7 @@
The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.
-For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:
+For example, the following files are provided in MDK to support the STM32F10x Connectivity Line device variants:
<table class="cmtable">
<tr>
@@ -61,14 +61,14 @@
</table>
-\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \ref templates_pg provide by ARM.
+\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \ref templates_pg provide by Arm.
Thereafter, the functions described under <a href="Modules.html">\b Reference </a> can be used in the application.
\b Examples
- \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
- \subpage using_VTOR_pg shows how to remap the interrupt vector table.
- - \subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for ARM processors.
+ - \subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for Arm processors.
\page using_CMSIS Basic CMSIS Example
@@ -184,11 +184,11 @@
}
\endcode
-\page using_ARM_pg Using CMSIS with generic ARM Processors
+\page using_ARM_pg Using CMSIS with generic Arm Processors
-ARM provides CMSIS-Core (Cortex-M) files for the supported ARM Processors and for various compiler vendors.
-These files can be used when standard ARM processors should be used in a project.
-The table below lists the folder and device names of the ARM processors.
+Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors.
+These files can be used when standard Arm processors should be used in a project.
+The table below lists the folder and device names of the Arm processors.
<table class="cmtable">
<tr>
diff --git a/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt b/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt
index 5da44a4..020de00 100644
--- a/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt
+++ b/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt
@@ -1,36 +1,36 @@
/**
-\page using_TrustZone_pg Using TrustZone for ARMv8-M
+\page using_TrustZone_pg Using TrustZone for Armv8-M
\details
-The optional ARMv8-M security extension is similar to ARM TrustZone technology used in Cortex-A processors, but is
-optimized for ultra-low power embedded applications. TrustZone for ARMv8-M enables of multiple software security
+The optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is
+optimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security
domains that restrict access to secure memory and I/O only for trusted software.
-TrustZone for ARMv8-M:
+TrustZone for Armv8-M:
- preserves low interrupt latencies for both Secure and Non-secure domains.
- does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.
- introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.
\b Notations
-This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for ARMv8-M:
+This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:
- - prefix \b TZ or \b __TZ indicates a function that is available only in ARMv8-M TrustZone enabled devices.
+ - prefix \b TZ or \b __TZ indicates a function that is available only in Armv8-M TrustZone enabled devices.
- postfix \b _NS indicates a hardware resource that belongs to the Non-secure state.
- postfix \b _S indicates a hardware resource that belongs to the Secure state.
\section useCase_TrustZone Simplified Use Case with TrustZone
-An ARMv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted
+An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted
software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection,
or multi-party embedded software deployments.
The figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b>
(executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state).
- - <b>System Start:</b> after power on or reset, an ARMv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.
+ - <b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.
- <b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.
@@ -40,23 +40,23 @@
\image html "SimpleUseCase.png" "Simplified Use Case"
Program execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures.
-For example, an ARMv8-M system may implement two independent SYSTICK timers which allows to stop code execution
+For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution
in <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b>
to <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently
executing code in <b>Non-secure state</b>.
\subsection Example_TrustZone Program Examples
-This CMSIS software pack contains the following program examples that show the usage of TrustZone for ARMv8-M on Cortex-M33 devices:
+This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:
Example | Description
:-------------------------------------------|:----------------
-TrustZone for ARMv8-M No RTOS | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
-TrustZone for ARMv8-M RTOS | secure/non-secure RTOS example with thread context management
-TrustZone for ARMv8-M RTOS Security Tests | secure/non-secure RTOS example with security test cases and system recovery
+TrustZone for Armv8-M No RTOS | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
+TrustZone for Armv8-M RTOS | secure/non-secure RTOS example with thread context management
+TrustZone for Armv8-M RTOS Security Tests | secure/non-secure RTOS example with security test cases and system recovery
-Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>ARMv8MBL Secure/Non-Secure example</b> that is available in
-the Software Pack <b>Keil - ARM V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b>
+Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in
+the Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b>
(Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).
\section Model_TrustZone Programmers Model with TrustZone
@@ -88,7 +88,7 @@
\anchor MemoryMap_NS
\image html "MemoryMap_NS.png" "Non-Secure Memory Map"
-The figure <b>Registers</b> shows the register view of the ARMv8-M system with TrustZone. As the general purpose registers
+The figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers
are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter
and return values.
@@ -96,17 +96,17 @@
accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or
thread=normal code execution).
-In ARMv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)
+In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)
that traps stack overflows with the \b UsageFault exception (register UFSR bit STKOF=1).
-An ARMv8-M system with TrustZone has an independent \b CONTROL register for each state (Secure or Non-secure).
+An Armv8-M system with TrustZone has an independent \b CONTROL register for each state (Secure or Non-secure).
The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure),
however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that
secure interrupts have always higher priority.
The core registers of the current state (Secure or Non-secure) are accessed using the standard \ref Core_Register_gr
functions. In Secure state all non-secure registers are accessible using the \ref coreregister_trustzone_functions
-related to TrustZone for ARMv8-M.
+related to TrustZone for Armv8-M.
\image html "Registers.png" "Registers"
@@ -123,14 +123,14 @@
\subsection RTOS_TrustZone RTOS Thread Context Management
-To provide a consistent RTOS thread context management for ARMv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.
+To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.
An <i>non-secure application</i> which uses an RTOS and calls <i>secure</i> library modules requires the management of the <i>secure</i> stack space. Since <i>secure state</i> registers cannot be accessed
by the RTOS that runs in <i>non-secure state</i> secure functions implement the thread context switch.
As the <i>non-secure state</i> and <i>secure state</i> parts of an application are separated, the API for managing the <i>secure</i> stack space should be standardized. Otherwise the <i>secure</i> library modules
would force the <i>non-secure state</i> application to use a matching RTOS implementation.
-\image html "TZ_context.png" "RTOS Thread Context Management for ARMv8-M TrustZone"
+\image html "TZ_context.png" "RTOS Thread Context Management for Armv8-M TrustZone"
To allocate the context memory for threads, an RTOS kernel that runs in <i>non-secure state</i> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are
part of the <i>secure state</i> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory
diff --git a/CMSIS/DoxyGen/Core_A/src/Overview.txt b/CMSIS/DoxyGen/Core_A/src/Overview.txt
index d367cea..b6ed47b 100644
--- a/CMSIS/DoxyGen/Core_A/src/Overview.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Overview.txt
@@ -12,7 +12,7 @@
The following sections provide details about the CMSIS-Core (Cortex-A):
- \ref using_pg describes the project setup and shows a simple program example.
- - \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by ARM to silicon vendor devices.
+ - \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
- \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
- <a href="Modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
- <a href="Annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
@@ -27,7 +27,7 @@
|--------------------------------|------------------------------------------------------------------------|
|\b CMSIS\\Documentation\\Core_A | This documentation |
|\b CMSIS\\Core_A\\Include | CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.) |
-|\b Device | \ref using_ARM_pg "ARM reference implementations" of Cortex-A devices |
+|\b Device | \ref using_ARM_pg "Arm reference implementations" of Cortex-A devices |
|\b Device\\\_Template_Vendor | \ref templates_pg for extension by silicon vendors |
<hr>
@@ -38,21 +38,21 @@
\subsection ref_man_ca_sec Cortex-A Technical Reference Manuals
-The following Technical Reference Manuals describe the various ARM Cortex-A processors:
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf" target="_blank"><b>Cortex-A5</b></a> (ARMv7-A architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf" target="_blank"><b>Cortex-A7</b></a> (ARMv7-A architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf" target="_blank"><b>Cortex-A9</b></a> (ARMv7-A architecture)
+The following Technical Reference Manuals describe the various Arm Cortex-A processors:
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf" target="_blank"><b>Cortex-A5</b></a> (Armv7-A architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf" target="_blank"><b>Cortex-A7</b></a> (Armv7-A architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf" target="_blank"><b>Cortex-A9</b></a> (Armv7-A architecture)
<hr>
\section tested_tools_sec Tested and Verified Toolchains
-The \ref templates_pg supplied by ARM have been tested and verified with the following toolchains:
- - ARM: ARM Compiler 5.06 update 6
- - ARM: ARM Compiler 6.9
- - ARM: ARM Compiler 6.6.2
- - GNU: GNU Tools for ARM Embedded 6.3.1 20170620
- - IAR: IAR ANSI C/C++ Compiler for ARM 8.20.1.14183
+The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
+ - Arm: Arm Compiler 5.06 update 6
+ - Arm: Arm Compiler 6.9
+ - Arm: Arm Compiler 6.6.2
+ - GNU: GNU Tools for Arm Embedded 6.3.1 20170620
+ - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
<hr>
*/
diff --git a/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt b/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt
index b4a1c6b..6720c6e 100644
--- a/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt
@@ -4,7 +4,7 @@
\defgroup system_init_gr System and Clock Configuration
\brief Functions for system and clock setup available in system_<i>device</i>.c.
\details
-ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
+Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
the silicon vendor to match their actual device. As a <b>minimum requirement</b>,
this file must provide:
- A device-specific system configuration function, \ref SystemInit().
@@ -17,13 +17,13 @@
\note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
used throughout the whole system initialization and runtime to calculate frequency/time related values.
Thus one must assure that the variable always reflects the actual system clock speed. Be aware that
-a value stored to \c SystemCoreClock during low level initializaton (i.e. \c SystemInit()) might get
-overwritten by C libray startup code. Thus its highly recommended to call \ref SystemCoreClockUpdate
+a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
+overwritten by C library startup code. Thus its highly recommended to call \ref SystemCoreClockUpdate
at the beginning of the user \c main() routine.
\section system_init_code_ex_sec Code Example
The code below shows the usage of the variable \ref SystemCoreClock and the functions
-SystemInit() and SystemCoreClockUpdate() with an arbitratry ARM Cortex-A9.
+SystemInit() and SystemCoreClockUpdate() with an arbitrary Arm Cortex-A9.
\code
#include "ARMCA9.h"
diff --git a/CMSIS/DoxyGen/Core_A/src/Template.txt b/CMSIS/DoxyGen/Core_A/src/Template.txt
index da3a79a..eec6c47 100644
--- a/CMSIS/DoxyGen/Core_A/src/Template.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Template.txt
@@ -3,7 +3,7 @@
\details
-ARM supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
+Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
Refer to the list of \ref tested_tools_sec for compliance.
These CMSIS-Core device template files include the following:
@@ -17,7 +17,7 @@
\section CMSIS_Processor_files CMSIS-Core Processor Files
-The CMSIS-Core processor files provided by ARM are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
+The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
The <b>core_<cpu>.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:
Header File | Processor
@@ -52,11 +52,11 @@
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\startup_Device.c</td>
- <td>Startup file template for ARM C/C++ Compiler.</td>
+ <td>Startup file template for Arm C/C++ Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\Device.sct</td>
- <td>Linker scatter file template for ARM C/C++ Compiler.</td>
+ <td>Linker scatter file template for Arm C/C++ Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\system_Device.c</td>
@@ -137,7 +137,7 @@
\section startup_c_sec startup_Device.c Template File
-An ARM Compiler specific startup file for an ARMv7-A processor like Cortex-A9 is shown below.
+An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below.
The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
\verbinclude "Source\ARM\startup_Device.c"
@@ -186,10 +186,10 @@
\section interrupt_number_sec Interrupt Number Definition
\ref device_h_pg contains the enumeration \ref IRQn_Type that defines all exceptions and interrupts of the device.
-For devices implementing an ARM GIC these are defined as:
+For devices implementing an Arm GIC these are defined as:
- IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
- IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
- - IRQn 32-1019 represents shared peripheral interrups (SPI), routeable to all processor cores.
+ - IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
- IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.
\b Example:
diff --git a/CMSIS/DoxyGen/Core_A/src/Using.txt b/CMSIS/DoxyGen/Core_A/src/Using.txt
index de31d78..8a497a9 100644
--- a/CMSIS/DoxyGen/Core_A/src/Using.txt
+++ b/CMSIS/DoxyGen/Core_A/src/Using.txt
@@ -41,13 +41,13 @@
The CMSIS-Core-A user files are device specific. In addition, the \ref startup_c_pg is also compiler vendor specific.
The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.
-\note The silicon vendors create these device-specific CMSIS-Core-A files based on \ref templates_pg provide by ARM.
+\note The silicon vendors create these device-specific CMSIS-Core-A files based on \ref templates_pg provide by Arm.
Thereafter, the functions described under <a href="Modules.html">\b Reference </a> can be used in the application.
\b Examples
- \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
- - \subpage using_ARM_pg explains how to use CMSIS-Core-M for ARM processors.
+ - \subpage using_ARM_pg explains how to use CMSIS-Core-M for Arm processors.
\page using_CMSIS Basic CMSIS Example
@@ -112,11 +112,11 @@
}
\endcode
-\page using_ARM_pg Using CMSIS with generic ARM Processors
+\page using_ARM_pg Using CMSIS with generic Arm Processors
-ARM provides CMSIS-Core-A files for the supported ARM Processors and for various compiler vendors.
-These files can be used when standard ARM processors should be used in a project.
-The table below lists the folder and device names of the ARM processors.
+Arm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors.
+These files can be used when standard Arm processors should be used in a project.
+The table below lists the folder and device names of the Arm processors.
<table class="cmtable">
<tr>
diff --git a/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt b/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
index 80c7ed9..6ea1475 100644
--- a/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
+++ b/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt
@@ -20,9 +20,9 @@
/**
\def __ARM_ARCH_7A__
-\brief Set to 1 when generating code for ARMv7-A (Cortex-A7)
+\brief Set to 1 when generating code for Armv7-A (Cortex-A7)
\details
-The \b \#define __ARM_ARCH_7A__ is set to 1 when generating code for the ARMv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
+The \b \#define __ARM_ARCH_7A__ is set to 1 when generating code for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
*/
/**
diff --git a/CMSIS/DoxyGen/Core_A/src/core_ca.txt b/CMSIS/DoxyGen/Core_A/src/core_ca.txt
index b5d3afd..24d67bf 100644
--- a/CMSIS/DoxyGen/Core_A/src/core_ca.txt
+++ b/CMSIS/DoxyGen/Core_A/src/core_ca.txt
@@ -345,7 +345,7 @@
\defgroup FPU_functions Floating Point Unit Functions
\ingroup CMSIS_Core_FunctionInterface
\brief FPU Functions enable the use of Floating Point instructions and extensions.\n
-Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition</a>.
+Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
@{
\fn __STATIC_INLINE __ASM void __FPU_Enable(void)
@}
diff --git a/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt b/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt
index fefb55d..16ec896 100644
--- a/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt
+++ b/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt
@@ -7,10 +7,10 @@
\details This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers.
The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.
-\note The default implementation for \ref GIC_functions "ARM GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c.
+\note The default implementation for \ref GIC_functions "Arm GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c.
It uses \c weak functions thus it can easily be overwritten by an alternative user implementation if needed.
-The ARMv7-A architecture defines a common set of first level exceptions, see table below.
+The Armv7-A architecture defines a common set of first level exceptions, see table below.
| Exception | CMSIS Handler | Offset | Description |
|-------------------------------|---------------|--------|-----------------------------------------------------------------------------|
@@ -138,7 +138,7 @@
configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should
be set to NULL.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
/// Number of implemented interrupt lines
@@ -166,7 +166,7 @@
\details This function registers address of the interrupt handler callback function corresponding to the specified interrupt
ID number.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
@@ -190,7 +190,7 @@
\details This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt
ID number.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
@@ -212,7 +212,7 @@
\fn int32_t IRQ_Enable (IRQn_ID_t irqn)
\details This function enables forwarding of the corresponding interrupt to the CPU.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_Enable (IRQn_ID_t irqn) {
@@ -235,7 +235,7 @@
\fn int32_t IRQ_Disable (IRQn_ID_t irqn)
\details This function disables forwarding of the corresponding interrupt to the CPU.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_Disable (IRQn_ID_t irqn) {
@@ -261,7 +261,7 @@
Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts
which cannot be identified by irqn.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
@@ -285,7 +285,7 @@
\details This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt
(see \ref irq_mode_defs) identified by the irqn parameter.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
@@ -364,7 +364,7 @@
\details This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter.
\ref IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
@@ -402,7 +402,7 @@
\fn IRQn_ID_t IRQ_GetActiveIRQ (void)
\details This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
IRQn_ID_t IRQ_GetActiveIRQ (void) {
@@ -420,7 +420,7 @@
\fn IRQn_ID_t IRQ_GetActiveFIQ (void)
\details This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
IRQn_ID_t IRQ_GetActiveFIQ (void) {
@@ -438,7 +438,7 @@
The parameter irqn should specify the value previously returned by the \ref IRQ_GetActiveIRQ or \ref IRQ_GetActiveFIQ functions.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
@@ -466,7 +466,7 @@
\fn int32_t IRQ_SetPending (IRQn_ID_t irqn)
\details This function sets the pending status of the interrupt identified by the irqn parameter.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPending (IRQn_ID_t irqn) {
@@ -492,7 +492,7 @@
Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which
cannot be identified by irqn.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
@@ -514,7 +514,7 @@
\fn int32_t IRQ_ClearPending (IRQn_ID_t irqn)
\details This function clears the pending status of the interrupt identified by the irqn parameter.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
@@ -543,7 +543,7 @@
The number of implemented priority bits can be determined by setting value \ref IRQ_PRIORITY_Msk to arbitrary irqn and by
retrieving the actual stored value with IRQ_GetPriority function.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
@@ -569,7 +569,7 @@
The valid priority value can be from zero (0) to the value of \ref IRQ_PRIORITY_Msk. \ref IRQ_PRIORITY_ERROR bit is set in
returned value for interrupts which cannot be identified by irqn.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
@@ -594,7 +594,7 @@
It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor.
Function returns error status -1 if priority masking is not supported.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
IRQ_SetPriorityMask (uint32_t priority) {
@@ -611,7 +611,7 @@
\ref IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriorityMask (void) {
@@ -630,7 +630,7 @@
actual stored value with \ref IRQ_GetPriorityGroupBits function.
Function returns error status -1 if priority grouping is not supported.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
@@ -660,7 +660,7 @@
\ref IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriorityGroupBits (void) {
diff --git a/CMSIS/DoxyGen/Core_A/src/ref_core_register.txt b/CMSIS/DoxyGen/Core_A/src/ref_core_register.txt
index 53b0bce..2ed9e3c 100644
--- a/CMSIS/DoxyGen/Core_A/src/ref_core_register.txt
+++ b/CMSIS/DoxyGen/Core_A/src/ref_core_register.txt
@@ -13,7 +13,7 @@
\ingroup CMSIS_core_register
\brief The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
\details
-The ACTLR characteristics are differs between various ARMv7-A implementations.
+The ACTLR characteristics are differs between various Armv7-A implementations.
<b>Cortex-A5</b>
@@ -1044,7 +1044,7 @@
/**
\defgroup CMSIS_TLB TLB maintenance operations
\ingroup CMSIS_core_register
-\brief This section describes the TLB operations that are implemented on all ARMv7-A implementations.
+\brief This section describes the TLB operations that are implemented on all Armv7-A implementations.
\details
TLB maintenance operations provide a mechanism to invalidate entries from a TLB.
diff --git a/CMSIS/DoxyGen/Core_A/src/ref_gic.txt b/CMSIS/DoxyGen/Core_A/src/ref_gic.txt
index ea138ae..e05bb63 100644
--- a/CMSIS/DoxyGen/Core_A/src/ref_gic.txt
+++ b/CMSIS/DoxyGen/Core_A/src/ref_gic.txt
@@ -330,7 +330,7 @@
The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
refer to the section Interrupt prioritization in the
-<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">ARM Generic Interrupt Controller Architecture Specificaton</a>
+<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a>
for details.
\var __IOM uint32_t GICInterface_Type::ABPR
diff --git a/CMSIS/DoxyGen/Core_A/src/ref_mmu.txt b/CMSIS/DoxyGen/Core_A/src/ref_mmu.txt
index d6b4e14..47eb68b 100644
--- a/CMSIS/DoxyGen/Core_A/src/ref_mmu.txt
+++ b/CMSIS/DoxyGen/Core_A/src/ref_mmu.txt
@@ -3,7 +3,7 @@
\defgroup MMU_functions Memory Management Unit Functions
\ingroup CMSIS_Core_FunctionInterface
\brief MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.\n
-Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition</a>.
+Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
*/
/** @{ */
diff --git a/CMSIS/DoxyGen/DAP/src/dap.txt b/CMSIS/DoxyGen/DAP/src/dap.txt
index f888d5c..b468523 100644
--- a/CMSIS/DoxyGen/DAP/src/dap.txt
+++ b/CMSIS/DoxyGen/DAP/src/dap.txt
@@ -3,7 +3,7 @@
<b>CMSIS-DAP</b> is a specification and a implementation of a <b>Firmware</b> that supports access to the CoreSight <b>Debug Access Port</b> (DAP).\n\n
-The various ARM Cortex processors provide <a href="http://www.arm.com/products/system-ip/coresight/index.php" target="_blank">
+The various Arm Cortex processors provide <a href="http://www.arm.com/products/system-ip/coresight/index.php" target="_blank">
<b>CoreSight Debug and Trace</b></a>. CMSIS-DAP supports target Devices that contain one or more Cortex processors.
A Device provides a Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD)
interface that connects to a Debug Unit. CMSIS-DAP is the interface firmware for a Debug Unit that connects
@@ -62,7 +62,7 @@
Debug Access
------------
\note
-ARM plans to provide the <b>RDDI-DAP Access DLL</b> that connects a debugger to the CMSIS-DAP Firmware.
+Arm plans to provide the <b>RDDI-DAP Access DLL</b> that connects a debugger to the CMSIS-DAP Firmware.
However as the DAP registers are standard in all Cortex devices, the debug access is well understood
by the industry.
diff --git a/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt b/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt
index de1bab6..77729ed 100644
--- a/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt
+++ b/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt
@@ -592,7 +592,7 @@
\brief Configure SWD Protocol
\details
The <b>DAP_SWD_Configure Command</b> sets the SWD protocol configuration. For more information about
-the SWD protocol refer to the <b>ARM Debug Interface v5 - Interface Specification.</b>
+the SWD protocol refer to the <b>Arm Debug Interface v5 - Interface Specification.</b>
<b>DAP_SWD_Configure Command</b>:
\code
diff --git a/CMSIS/DoxyGen/DAP/src/dap_config.txt b/CMSIS/DoxyGen/DAP/src/dap_config.txt
index 0c4446d..4900bbf 100644
--- a/CMSIS/DoxyGen/DAP/src/dap_config.txt
+++ b/CMSIS/DoxyGen/DAP/src/dap_config.txt
@@ -216,7 +216,7 @@
@{
A CMSIS-DAP conforming Debug Unit must be validated.
-A CMSIS-DAP Debug Unit must be validate using the Keil MDK-ARM Debugger.
+A CMSIS-DAP Debug Unit must be validate using the Keil MDK Debugger.
A validation project for MDK is provided in the folder <b>.\\Validation\\MDK</b>.
The project <b>Blinky.uvproj</b> is a "Blinky" application and needs to be adapted for the target hardware
that is connected to the Debug Unit. Once the adaptation is complete, you may open a Command Prompt and
diff --git a/CMSIS/DoxyGen/DSP/src/Change Log.txt b/CMSIS/DoxyGen/DSP/src/Change Log.txt
index 5b9da75..47b9557 100644
--- a/CMSIS/DoxyGen/DSP/src/Change Log.txt
+++ b/CMSIS/DoxyGen/DSP/src/Change Log.txt
@@ -58,7 +58,7 @@
- corrected arm_sin_f32() for very small negative input values.
Modified arm_sin_f32.c
-- Updated Texas Instruments ARM compiler support.
+- Updated Texas Instruments Arm Compiler support.
Updated documentation
- function \ref arm_rfft_fast_f32.
diff --git a/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html b/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html
index b7ea88b..7e24f10 100644
--- a/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html
+++ b/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html
@@ -3,7 +3,7 @@
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
$navpath
- <li class="footer">Generated on $datetime for $projectname by ARM Ltd. All rights reserved.
+ <li class="footer">Generated on $datetime for $projectname by Arm Ltd. All rights reserved.
<!--
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="$relpath$doxygen.png" alt="doxygen"/></a> $doxygenversion
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_ETH.c b/CMSIS/DoxyGen/Driver/src/Driver_ETH.c
index 8d6e808..923a79b 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_ETH.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_ETH.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: Ethernet Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup eth_interface_gr Ethernet Interface
\brief Ethernet common definitions (%Driver_ETH.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c b/CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c
index fff5fef..d5ca696 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: Ethernet MAC Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup eth_mac_interface_gr Ethernet MAC Interface
\ingroup eth_interface_gr
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c b/CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c
index 9404b06..8bab658 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: Ethernet PHY Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup eth_phy_interface_gr Ethernet PHY Interface
\ingroup eth_interface_gr
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_Flash.c b/CMSIS/DoxyGen/Driver/src/Driver_Flash.c
index 5f2e11a..259ca63 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_Flash.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_Flash.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: Flash Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup flash_interface_gr Flash Interface
\brief Driver API for Flash Device Interface (%Driver_Flash.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_I2C.c b/CMSIS/DoxyGen/Driver/src/Driver_I2C.c
index 17be13d..4e10b20 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_I2C.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_I2C.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: I2C Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup i2c_interface_gr I2C Interface
\brief Driver API for I2C Bus Peripheral (%Driver_I2C.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_MCI.c b/CMSIS/DoxyGen/Driver/src/Driver_MCI.c
index 8164256..c6031a2 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_MCI.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_MCI.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: MCI Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup mci_interface_gr MCI Interface
\brief Driver API for Memory Card Interface using SD/MMC interface (%Driver_MCI.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_NAND.c b/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
index 7ac4c20..a4bf194 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: NAND Flash Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup nand_interface_gr NAND Interface
\brief Driver API for NAND Flash Device Interface (%Driver_NAND.h).
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_SPI.c b/CMSIS/DoxyGen/Driver/src/Driver_SPI.c
index 84924b6..ecca438 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_SPI.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_SPI.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: SPI Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup spi_interface_gr SPI Interface
\brief Driver API for SPI Bus Peripheral (%Driver_SPI.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_Storage.c b/CMSIS/DoxyGen/Driver/src/Driver_Storage.c
index 6cd43d8..5100e46 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_Storage.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_Storage.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
- *
- * $Date: 7. March 2016
- * $Revision: V1.00
- *
- * Project: Storage Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup storage_interface_gr Storage Interface
\brief Driver API for Storage Device Interface (%Driver_Storage.h)
@@ -625,7 +615,7 @@
asynchronous driver implementations.
\code
-// Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+// Copyright (c) 2006-2016, Arm Limited, All Rights Reserved
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_USART.c b/CMSIS/DoxyGen/Driver/src/Driver_USART.c
index e28432a..1d89d5e 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_USART.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_USART.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: USART Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup usart_interface_gr USART Interface
\brief Driver API for Universal Synchronous Asynchronous Receiver/Transmitter (%Driver_USART.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_USB.c b/CMSIS/DoxyGen/Driver/src/Driver_USB.c
index ee6cb40..017b3e3 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_USB.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_USB.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: USB Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup usb_interface_gr USB Interface
\brief USB common definitions (%Driver_USB.h)
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_USBD.c b/CMSIS/DoxyGen/Driver/src/Driver_USBD.c
index 75d49f7..9f31511 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_USBD.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_USBD.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: USB Device Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup usbd_interface_gr USB Device Interface
\ingroup usb_interface_gr
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_USBH.c b/CMSIS/DoxyGen/Driver/src/Driver_USBH.c
index 33f6d2f..73f968a 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_USBH.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_USBH.c
@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *
- * $Date: 2. January 2014
- * $Revision: V2.00
- *
- * Project: USB Host Driver API
- * -------------------------------------------------------------------------- */
-
-
/**
\defgroup usbh_interface_gr USB Host Interface
\ingroup usb_interface_gr
diff --git a/CMSIS/DoxyGen/General/src/introduction.txt b/CMSIS/DoxyGen/General/src/introduction.txt
index 3c80172..59f530e 100644
--- a/CMSIS/DoxyGen/General/src/introduction.txt
+++ b/CMSIS/DoxyGen/General/src/introduction.txt
@@ -13,8 +13,8 @@
and middleware components. The CMSIS is intended to enable the combination of software components
from multiple middleware vendors.
-CMSIS Version 5 supports also the <a class="el" href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMv8-M architecture</a>
-including <a class="el" href="http://www.arm.com/products/processors/technologies/trustzone/index.php" target="_blank">TrustZone® for ARMv8-M</a> hardware security extensions and the
+CMSIS Version 5 supports also the <a class="el" href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">Armv8-M architecture</a>
+including <a class="el" href="http://www.arm.com/products/processors/technologies/trustzone/index.php" target="_blank">TrustZone® for Armv8-M</a> hardware security extensions and the
<a class="el" href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">Cortex-M23</a> and <a class="el" href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">Cortex-M33</a> processors.
\anchor CM_Components
@@ -35,7 +35,7 @@
- <a href="../../RTOS/html/index.html"><b>CMSIS-RTOS v1</b></a>: Common API for Real-Time Operating Systems along with reference implementation based on RTX.
It provides a standardized programming interface that is portable to many RTOS and enables software components that can work across multiple RTOS systems.
- - <a href="../../RTOS2/html/index.html"><b>CMSIS-RTOS v2</b></a>: extends CMSIS-RTOS v1 with support for ARMv8-M architecture, dynamic object creation,
+ - <a href="../../RTOS2/html/index.html"><b>CMSIS-RTOS v2</b></a>: extends CMSIS-RTOS v1 with support for Armv8-M architecture, dynamic object creation,
provisions for multi-core systems, and binary compatible interface across ABI compliant compilers.
- <a href="../../Pack/html/index.html"><b>CMSIS-Pack</b></a>: describes with an XML-based package description (PDSC) file the user and device relevant parts of a file collection (called a software pack) that includes source, header and library files, documentation,
@@ -109,27 +109,27 @@
\section Validation Validation
The various components of CMSIS Version 5 are validated using mainstream compilers. To get a diverse coverage,
-ARM uses the ARM Compiler v5 (based on EDG front-end), the ARM Compiler v6 (based on LLVM front-end), and the
+Arm uses the Arm Compiler v5 (based on EDG front-end), the Arm Compiler v6 (based on LLVM front-end), and the
GCC Compiler in the various tests. For each component, the section \b "Validation" describes the scope of the
various verifications.
CMSIS components are compatible with a range of C and C++ language standards. The CMSIS components comply with
the <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0036b/index.html">Application Binary
-Interface (ABI) for the ARM Architecture</a> (exception CMSIS-RTOS v1). This ensures C API interfaces that support
+Interface (ABI) for the Arm Architecture</a> (exception CMSIS-RTOS v1). This ensures C API interfaces that support
inter-operation between various toolchains.
As CMSIS defines API interfaces and functions that scale to a wide range of processors and devices, the scope of
the run-time test coverage is limited. However, several components are validated using dedicated test suites.
The CMSIS source code is checked for MISRA C:2012 conformance using PC-Lint. MISRA deviations are documented with
-reasonable effort, however ARM does not claim MISRA compliance as there is today for example no guideline enforcement
+reasonable effort, however Arm does not claim MISRA compliance as there is today for example no guideline enforcement
plan. The CMSIS source code is not checked for MISRA C++:2008 conformance as there is a risk that it is incompatible
with C language standards, specifically warnings that may be generated by the various C compilers.
\section License License
-The CMSIS is provided free of charge by ARM under Apache 2.0 license.
+The CMSIS is provided free of charge by Arm under Apache 2.0 license.
View the <a href="LICENSE.txt">Apache 2.0 License</a>.
@@ -142,7 +142,7 @@
\b ARM.CMSIS.pdsc |Package description file in CMSIS-Pack format.
\b LICENSE.txt |CMSIS License Agreement (Apache 2.0)
\b CMSIS |\ref CM_Components "CMSIS components" (see below)
-\b Device |CMSIS reference implementations of ARM Cortex-M processor based devices
+\b Device |CMSIS reference implementations of Arm Cortex-M processor based devices
CMSIS Directory
---------------
@@ -193,7 +193,7 @@
<tr>
<td>5.2.0</td>
<td>
- - CMSIS-Core (Cortex-M) 5.1.0 MPU fuctions for ARMv8-M, cmsis_iccarm.h replacing cmsis_iar.h
+ - CMSIS-Core (Cortex-M) 5.1.0 MPU functions for ARMv8-M, cmsis_iccarm.h replacing cmsis_iar.h
- CMSIS-Core (Cortex-A) 1.1.0 cmsis_iccarm.h, additional physical timer access functions
- CMSIS-Driver 2.6.0 Enhanced CAN and NAND driver interface.
- CMSIS-DSP 1.5.2 Fixed diagnostics and moved SSAT/USST intrinsics to CMSIS-Core.
diff --git a/CMSIS/DoxyGen/Pack/src/General.txt b/CMSIS/DoxyGen/Pack/src/General.txt
index d127a76..7a247eb 100644
--- a/CMSIS/DoxyGen/Pack/src/General.txt
+++ b/CMSIS/DoxyGen/Pack/src/General.txt
@@ -27,7 +27,7 @@
The figure above shows the following use cases for Software Packs:
- <b>Device Family Pack (DFP):</b> contains CMSIS system/startup files, drivers, and flash algorithms for a microcontroller
device family.
- - <b>CMSIS Software Pack:</b> contains the generic CMSIS components (CORE, DSP Library, and RTOS implementation) supplied by ARM.
+ - <b>CMSIS Software Pack:</b> contains the generic CMSIS components (CORE, DSP Library, and RTOS implementation) supplied by Arm.
- <b>Middleware Pack:</b> contains software components belonging to a middleware (such as source code or libraries).
- <b>Board Support Pack (BSP):</b> contains documentation, schematics, and drivers for a certain development board.
- <b>In-house Software Packs:</b> usually contain software components that can be distributed within a
@@ -101,7 +101,7 @@
<td>Modifications compared to Version 1.4.6
- added multiple version types to tighten the schema checking depending on context
- added new generator sections for exe, web and eclipse based generators in \<generator>
-- added new processor attributes Dtz = Trustzone and Ddsp = DSP instructions for ARMv8-M
+- added new processor attributes Dtz = Trustzone and Ddsp = DSP instructions for Armv8-M
- added new attributes Dtz, Ddsp, Dsecure to conditions \<require>, \<deny>, \<accept>
- added new processors Cortex-M23 and Cortex-M33 and other in DcoreEnum
- added new attribute public to books and images to indicate public use of documents and board images
diff --git a/CMSIS/DoxyGen/Pack/src/boards_schema.txt b/CMSIS/DoxyGen/Pack/src/boards_schema.txt
index 3634b01..c752523 100644
--- a/CMSIS/DoxyGen/Pack/src/boards_schema.txt
+++ b/CMSIS/DoxyGen/Pack/src/boards_schema.txt
@@ -478,7 +478,7 @@
\b Example
\code
-<debugInterface adapter="JTAG/SW" connector="20-pin ARM Standard JTAG Connector (0.1 inch connector)"/>
+<debugInterface adapter="JTAG/SW" connector="20-pin Arm Standard JTAG Connector (0.1 inch connector)"/>
<debugInterface adapter="JTAG/SW" connector="10-pin Cortex Debug Connector (0.05 inch connector)"/>
<debugInterface adapter="JTAG/SW" connector="20-pin Cortex Debug + ETM Connector (0.05 inch connector)"/>
<debugInterface adapter="ST-Link" connector="Mini-USB"/>
@@ -509,7 +509,7 @@
</tr>
<tr>
<td>connector</td>
- <td>String describing the debug connector. Usually one of these: \token{10-pin Cortex Debug Connector}, \token{20-pin ARM Standard JTAG Connector},
+ <td>String describing the debug connector. Usually one of these: \token{10-pin Cortex Debug Connector}, \token{20-pin Arm Standard JTAG Connector},
\token{20-pin Cortex Debug + ETM Connector}, \token{Mini-USB}, \token{Micro-USB}.</td>
<td>xs:string</td>
<td>optional</td>
diff --git a/CMSIS/DoxyGen/Pack/src/components_schema.txt b/CMSIS/DoxyGen/Pack/src/components_schema.txt
index e5c06ea..a8960cc 100644
--- a/CMSIS/DoxyGen/Pack/src/components_schema.txt
+++ b/CMSIS/DoxyGen/Pack/src/components_schema.txt
@@ -66,7 +66,7 @@
</component>
<component condition="ARM_CM0" Cclass="Device" Cgroup="Startup" Cversion="3.1.1">
- <description>System Startup for generic ARM Cortex-M0 device</description>
+ <description>System Startup for generic Arm Cortex-M0 device</description>
<files>
<file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
<file category="header" name="Device/ARM/ARMCM0/Include/system_ARMCM0.h"/>
diff --git a/CMSIS/DoxyGen/Pack/src/conditions_schema.txt b/CMSIS/DoxyGen/Pack/src/conditions_schema.txt
index 4d8fd81..0ccebd4 100644
--- a/CMSIS/DoxyGen/Pack/src/conditions_schema.txt
+++ b/CMSIS/DoxyGen/Pack/src/conditions_schema.txt
@@ -328,9 +328,9 @@
<tr>
<td>Toptions</td>
<td>Specifies compiler specific options being active. For <em>Tcompiler="ARMCC"</em> available Toptions are:
- - <b>AC5</b>: ARM Compiler Version 5 is in used
- - <b>AC6</b>: ARM Compiler Version 6 (aka: ARM Clang 6) is in use
- - <b>AC6LTO</b>: ARM Compiler Version 6 with Link Time Optimization (aka: LTO) is in use
+ - <b>AC5</b>: Arm Compiler Version 5 is in used
+ - <b>AC6</b>: Arm Compiler Version 6 (armclang) is in use
+ - <b>AC6LTO</b>: Arm Compiler Version 6 with Link Time Optimization (LTO) is in use
This attribute can be used to select compatible libraries for the selected compiler version or optimization mode.
</td>
@@ -370,8 +370,8 @@
</tr>
<tr>
<td class="XML-Token">GCC</td>
- <td>GNU Tools for ARM Embedded Processors.
- Refer to <a href="https://launchpad.net/gcc-arm-embedded/4.7" target="_blank">ARM GCC</a>.</td>
+ <td>GNU Tools for Arm Embedded Processors.
+ Refer to <a href="https://launchpad.net/gcc-arm-embedded/4.7" target="_blank">Arm GCC</a>.</td>
</tr>
<tr>
<td class="XML-Token">G++</td>
@@ -379,9 +379,9 @@
</tr>
<tr>
<td class="XML-Token">ARMCC</td>
- <td>ARM compiler for C and C++.
+ <td>Arm Compiler for C and C++.
Refer to <a href="http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.coretools/index.html" target="_blank">
- ARM Compiler from ARM</a>.</td>
+ Arm Compiler</a>.</td>
</tr>
<tr>
<td class="XML-Token">IAR</td>
diff --git a/CMSIS/DoxyGen/Pack/src/devices_schema.txt b/CMSIS/DoxyGen/Pack/src/devices_schema.txt
index 2f39e5e..9768753 100644
--- a/CMSIS/DoxyGen/Pack/src/devices_schema.txt
+++ b/CMSIS/DoxyGen/Pack/src/devices_schema.txt
@@ -49,7 +49,7 @@
<book name="doc/STM32F2.PDF" title="STM32F2 Reference Manual"/>
<description>
- ARM 32-bit Cortex-M3 CPU based Microcontroller
+ Arm 32-bit Cortex-M3 CPU based Microcontroller
- 120 MHz maximum frequency producing 150 DMIPS/1.25 DMIPS/MHz
- Memory Protection Unit
- Flexible static memory controller (supports Compact Flash, SRAM, PSRAM, NOR, NAND memories)
@@ -1524,7 +1524,7 @@
</tr>
<tr>
<td>Dtz</td>
- <td>Specifies whether an ARMv8-M based device implements TrustZone. Use predefined values as listed in the table \ref DtzEnum "Device TZ".</td>
+ <td>Specifies whether an Armv8-M based device implements TrustZone. Use predefined values as listed in the table \ref DtzEnum "Device TZ".</td>
<td>DtzEnum</td>
<td>required for ARMv8-M based devices</td>
</tr>
@@ -1841,7 +1841,7 @@
</tr>
<tr>
<td class="XML-Token">Keil</td>
- <td>\ref flashAlgorithm as defined by ARM/Keil</td>
+ <td>\ref flashAlgorithm as defined by Arm/Keil</td>
</tr>
<tr>
<td class="XML-Token">IAR</td>
@@ -1873,35 +1873,35 @@
</tr>
<tr>
<td class="XML-Token">Cortex-M0</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0.php" target="_blank">ARM Cortex-M0</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0.php" target="_blank">Arm Cortex-M0</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M0+</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php" target="_blank">ARM Cortex-M0+</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php" target="_blank">Arm Cortex-M0+</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M1</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m1.php" target="_blank">ARM Cortex-M1</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m1.php" target="_blank">Arm Cortex-M1</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M3</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m3.php" target="_blank">ARM Cortex-M3</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m3.php" target="_blank">Arm Cortex-M3</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M4</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php" target="_blank">ARM Cortex-M4</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php" target="_blank">Arm Cortex-M4</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M7</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php" target="_blank">ARM Cortex-M7</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php" target="_blank">Arm Cortex-M7</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M23</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">ARM Cortex-M23</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">Arm Cortex-M23</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-M33</td>
- <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">ARM Cortex-M33</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">Arm Cortex-M33</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">SC000</td>
@@ -1913,75 +1913,75 @@
</tr>
<tr>
<td class="XML-Token">ARMV8MBL</td>
- <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMV8MBL</a> compliant with the ARMv8-M Baseline Architecture.</td>
+ <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ArmV8MBL</a> compliant with the Armv8-M Baseline Architecture.</td>
</tr>
<tr>
<td class="XML-Token">ARMV8MML</td>
- <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMV8MML</a> compliant with the ARMv8-M Mainline Architecture.</td>
+ <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ArmV8MML</a> compliant with the Armv8-M Mainline Architecture.</td>
</tr>
<tr>
<td class="XML-Token">Cortex-R4</td>
- <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r4.php" target="_blank">ARM Cortex-R4</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r4.php" target="_blank">Arm Cortex-R4</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-R5</td>
- <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r5.php" target="_blank">ARM Cortex-R5</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r5.php" target="_blank">Arm Cortex-R5</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-R7</td>
- <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r7.php" target="_blank">ARM Cortex-R7</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r7.php" target="_blank">Arm Cortex-R7</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-R8</td>
- <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r8.php" target="_blank">ARM Cortex-R8</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r8.php" target="_blank">Arm Cortex-R8</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A5</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a5.php" target="_blank">ARM Cortex-A5</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a5.php" target="_blank">Arm Cortex-A5</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A7</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a7.php" target="_blank">ARM Cortex-A7</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a7.php" target="_blank">Arm Cortex-A7</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A8</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a8.php" target="_blank">ARM Cortex-A8</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a8.php" target="_blank">Arm Cortex-A8</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A9</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a9.php" target="_blank">ARM Cortex-A9</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a9.php" target="_blank">Arm Cortex-A9</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A15</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a15.php" target="_blank">ARM Cortex-A15</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a15.php" target="_blank">Arm Cortex-A15</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A17</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a17.php" target="_blank">ARM Cortex-A17</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a17.php" target="_blank">Arm Cortex-A17</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A32</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a32.php" target="_blank">ARM Cortex-A32</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a32.php" target="_blank">Arm Cortex-A32</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A35</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a35.php" target="_blank">ARM Cortex-A35</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a35.php" target="_blank">Arm Cortex-A35</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A53</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a53.php" target="_blank">ARM Cortex-A53</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a53.php" target="_blank">Arm Cortex-A53</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A57</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a57.php" target="_blank">ARM Cortex-A57</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a57.php" target="_blank">Arm Cortex-A57</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A72</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a72.php" target="_blank">ARM Cortex-A72</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a72.php" target="_blank">Arm Cortex-A72</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">Cortex-A73</td>
- <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a73.php" target="_blank">ARM Cortex-A73</a> processor based device</td>
+ <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a73.php" target="_blank">Arm Cortex-A73</a> processor based device</td>
</tr>
<tr>
<td class="XML-Token">*</td>
@@ -2265,7 +2265,7 @@
<tr>
<td class="XML-Token">swd</td>
<td>
- ARM Serial Wire Debug (SWD) protocol.
+ Arm Serial Wire Debug (SWD) protocol.
</td>
</tr>
<tr>
@@ -2715,7 +2715,7 @@
\section element_dp_swd /package/devices/family/.../debugport/swd
-Indicates availability of an ARM Serial Wire Debug (SWD) interface for the <b>debugport</b> parent element.
+Indicates availability of an Arm Serial Wire Debug (SWD) interface for the <b>debugport</b> parent element.
Its attributes allow the manual override of SWD port characteristics as read from the target and provide
information for the port selection in a system with multi-drop SWD support.
diff --git a/CMSIS/DoxyGen/Pack/src/pack_creation.txt b/CMSIS/DoxyGen/Pack/src/pack_creation.txt
index 68b5ea4..687ff37 100644
--- a/CMSIS/DoxyGen/Pack/src/pack_creation.txt
+++ b/CMSIS/DoxyGen/Pack/src/pack_creation.txt
@@ -70,7 +70,7 @@
- Board Support: Generic interfaces for evaluation and development boards
- CMSIS: <i>Cortex Microcontroller Software Interface Standard</i> components
- CMSIS Driver: Unified device drivers compliant to the CMSIS-Driver specification
-- Compiler: ARM Compiler software extensions
+- Compiler: Arm Compiler software extensions
- Data Exchange: Software components for data exchange
- Device: Startup and system setup components
- File System*: File drive support and file system
diff --git a/CMSIS/DoxyGen/Pack/src/pack_dfp.txt b/CMSIS/DoxyGen/Pack/src/pack_dfp.txt
index 927ed0a..d9de3630 100644
--- a/CMSIS/DoxyGen/Pack/src/pack_dfp.txt
+++ b/CMSIS/DoxyGen/Pack/src/pack_dfp.txt
@@ -237,7 +237,7 @@
<name>MVCM3xxx</name> <!-- name of part-->
<series>MVCM3xxx</series> <!-- device series the device belongs to -->
<version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
- <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 100 MHz.</description>
+ <description>Arm 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 100 MHz.</description>
\endcode
</li>
<li>
@@ -250,7 +250,7 @@
You should see some output of SVDConv similar to this:
\verbatim
CMSIS-SVD SVD Consistency Checker / Header File Generator V2.86g
-Copyright (C) 2010 - 2014 ARM Ltd and ARM Germany GmbH. All rights reserved.
+Copyright (C) 2010 - 2014 Arm Ltd and Arm Germany GmbH. All rights reserved.
Options: "Files\SVD\MVCM3xxx.svd" --generate=header --fields=macro
Reading file: "Files\SVD\MVCM3xxx.svd"
diff --git a/CMSIS/DoxyGen/Pack/src/pack_publish.txt b/CMSIS/DoxyGen/Pack/src/pack_publish.txt
index 69c2cdc..00ff713 100644
--- a/CMSIS/DoxyGen/Pack/src/pack_publish.txt
+++ b/CMSIS/DoxyGen/Pack/src/pack_publish.txt
@@ -53,7 +53,7 @@
\section cp_KeilComPack Publishing on www.keil.com/pack
-ARM maintains a list of available software packs. If you wish to add your packs to that list, send either your vendor.pidx
+Arm maintains a list of available software packs. If you wish to add your packs to that list, send either your vendor.pidx
file or your PDSC file to the following email address: <a href="mailto:CMSIS@arm.com">CMSIS@arm.com</a>. The PIDX file will
be processed and all referenced PDSC files will be validated. The following content will be processed in order to generate
the web site (<a href="http://www.keil.com/dd2/pack">www.keil.com/dd2/pack</a>) and index file
diff --git a/CMSIS/DoxyGen/Pack/src/pack_swcomponents.txt b/CMSIS/DoxyGen/Pack/src/pack_swcomponents.txt
index dc94dde..2cc15a3 100644
--- a/CMSIS/DoxyGen/Pack/src/pack_swcomponents.txt
+++ b/CMSIS/DoxyGen/Pack/src/pack_swcomponents.txt
@@ -290,7 +290,7 @@
<file category="library" condition="CM4_CM7" name="MySWComp/Lib/mylib_cm4.lib"/>
\endcode
Note that library files should always have a condition with regards to a specific C/C++ compiler. To accomplish this, each
-processor condition has the additional requirement for the ARM C/C++ compiler.
+processor condition has the additional requirement for the Arm C/C++ compiler.
</li>
<li>
Add a new version number to the header of the PDSC file so that a Pack with a new version number will be created:
diff --git a/CMSIS/DoxyGen/Pack/src/pdsc_format.txt b/CMSIS/DoxyGen/Pack/src/pdsc_format.txt
index f89b6d7..5698bbb 100644
--- a/CMSIS/DoxyGen/Pack/src/pdsc_format.txt
+++ b/CMSIS/DoxyGen/Pack/src/pdsc_format.txt
@@ -42,7 +42,7 @@
Example filenames for software packs:
-Software Pack for CMSIS Version 4.0 released by ARM.
+Software Pack for CMSIS Version 4.0 released by Arm.
- <b>ARM.CMSIS.4.0.0.pack</b>: filename of the \ref cp_SWComponents "Software Pack".
- <b>ARM.CMSIS.pdsc</b>: filename of the <b>Pack Description</b> (*.PDSC) file.
@@ -94,7 +94,7 @@
<package schemaVersion="1.4" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>ExampleVendor</vendor>
<name>STM32F2xx_DFP</name> <!-- name of package -->
- <description>Device Family Package for STMicroelectronics STM32F2 Family of ARM Cortex-M3 based Microcontroller</description>
+ <description>Device Family Package for STMicroelectronics STM32F2 Family of Arm Cortex-M3 based Microcontroller</description>
<url></url>
<supportContact>http://www.arm.com/support</supportContact>
<license>./END_USER_LICENCE_AGREEMENT.rtf</license>
diff --git a/CMSIS/DoxyGen/Pack/src/xml_types.txt b/CMSIS/DoxyGen/Pack/src/xml_types.txt
index 903164d..3e662a3 100644
--- a/CMSIS/DoxyGen/Pack/src/xml_types.txt
+++ b/CMSIS/DoxyGen/Pack/src/xml_types.txt
@@ -105,7 +105,7 @@
executed when no sequence definition exists in the PDSC file.
\note Default debug access sequences read the System Control Space (SCS) of the processor and assume that the SCS offset is
-implemented as defined in the ARMv6-M/ARMv7-M/ARMv8-M architecture reference manual.
+implemented as defined in the Armv6-M/Armv7-M/Armv8-M architecture reference manual.
<table class="cmtable" summary="Enumeration: SequenceNameEnum">
<tr>
@@ -115,7 +115,7 @@
<tr>
<td class="XML-Token">\ref debugPortSetup</td>
<td>Prepare the target debug port for connection; is executed before acquiring access to the debug port.<br>
- May include for example an SWJ-DP switch sequence as defined in the ARM Debug Interface (ADI) Architecture Specification.<br>
+ May include for example an SWJ-DP switch sequence as defined in the Arm Debug Interface (ADI) Architecture Specification.<br>
<b>This sequence must not contain debug port/access port register and target memory accesses other than:</b>
- <b>Reading the \em DPIDR debug port register to release an SWD connection from its line reset.</b>
- <b>Writing the \em TARGETSEL debug port register (SWD protocol v2).</b>
@@ -418,7 +418,7 @@
<sequence name="DebugCoreStart">
<block>
- // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+ // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
__var SCS_Addr = 0xE000E000;
__var DHCSR_Addr = SCS_Addr + 0xDF0;
@@ -439,7 +439,7 @@
<sequence name="DebugCoreStop">
<block>
- // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+ // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
__var SCS_Addr = 0xE000E000;
__var DHCSR_Addr = SCS_Addr + 0xDF0;
@@ -465,7 +465,7 @@
<sequence name="ResetSystem">
<block>
- // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+ // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
__var SCS_Addr = 0xE000E000;
__var AIRCR_Addr = SCS_Addr + 0xD0C;
@@ -486,13 +486,13 @@
Execute a processor reset via software mechanisms.
-\note This Default Debug Access Sequence is empty for ARMv6-M and ARMv8-M based processors.
+\note This Default Debug Access Sequence is empty for Armv6-M and Armv8-M based processors.
\code
<sequence name="ResetProcessor">
<block>
- // System Control Space (SCS) offset as defined in ARMv7-M.
+ // System Control Space (SCS) offset as defined in Armv7-M.
__var SCS_Addr = 0xE000E000;
__var AIRCR_Addr = SCS_Addr + 0xD0C;
@@ -604,7 +604,7 @@
<block>
// System Control Space (SCS) offset as defined
- // in ARMv6-M/ARMv7-M. Reimplement this sequence
+ // in Armv6-M/Armv7-M. Reimplement this sequence
// if the SCS is located at a different offset.
__var SCS_Addr = 0xE000E000;
@@ -633,7 +633,7 @@
<block>
// System Control Space (SCS) offset as defined
- // in ARMv6-M/ARMv7-M. Reimplement this sequence
+ // in Armv6-M/Armv7-M. Reimplement this sequence
// if the SCS is located at a different offset.
__var SCS_Addr = 0xE000E000;
diff --git a/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt b/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt
index ef394c6..e50c79f 100644
--- a/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt
+++ b/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt
@@ -1,5 +1,5 @@
/* ----------------------------------------------------------------------
-* Copyright (C) 2016 ARM Limited. All rights reserved.
+* Copyright (C) 2016 Arm Limited. All rights reserved.
*
* $Date: 14. April 2016
* $Revision: 1.02
@@ -132,7 +132,7 @@
<tr>
<td>V4.81</td>
<td>
- Added provisions for ARM Compiler 6.\n
+ Added provisions for Arm Compiler 6.\n
Corrected: Message Queue behavior when osMessagePut timed out due to full queue and osMessageGet was called from ISR.\n
</td>
</tr>
@@ -478,7 +478,7 @@
/**
\page genRTOSIF Generic RTOS Interface
-The CMSIS-RTOS API is a generic RTOS interface for ARM® Cortex®-M processor-based devices. CMSIS-RTOS provides a
+The CMSIS-RTOS API is a generic RTOS interface for Arm® Cortex®-M processor-based devices. CMSIS-RTOS provides a
standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users
and the software industry.
- CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
@@ -541,7 +541,7 @@
/**
\page rtosValidation RTOS Validation
-ARM offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
+Arm offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
The <b>ARM::CMSIS-RTOS_Validation</b> Pack contains the following:
- Source code of a CMSIS-RTOS Validation Suite along with configuration file.
@@ -1110,7 +1110,7 @@
- PendSV (request for system-level service) when calling certain RTX functions from \b Handler mode
Interrupts can be used without limitation. Interrupt priority grouping can be used with some restrictions:
-- IRQ interrupts are never disabled by RTX Kernel for ARMv7-M architectures (Cortex-M3/M4/M7).
+- IRQ interrupts are never disabled by RTX Kernel for Armv7-M architectures (Cortex-M3/M4/M7).
- Software interrupt 0 is used by RTX and cannot be used in an application.
- RTX uses its own SVC Handler which is automatically linked from the library. \ref svcFunctions explains how to use a custom
SVC table.
diff --git a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
index e089740..2d56bd5 100644
--- a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
@@ -2,7 +2,7 @@
/**
\mainpage
-The <b>CMSIS-RTOS API Version 2 (CMSIS-RTOS2)</b> is a generic RTOS interface for ARM® Cortex®-M processor-based
+The <b>CMSIS-RTOS API Version 2 (CMSIS-RTOS2)</b> is a generic RTOS interface for Arm® Cortex®-M processor-based
devices. It provides a standardized API for software components that require RTOS functionality and gives therefore serious
benefits to the users and the software industry:
- CMSIS-RTOS2 provides basic features that are required in many applications.
@@ -26,7 +26,7 @@
The CMSIS-RTOS2 addresses the following new requirements:
- Dynamic object creation no longer requires static memory, static memory buffers are now optional.
- - Support for ARMv8-M architecture that provides a secure and non-secure state of code execution.
+ - Support for Armv8-M architecture that provides a secure and non-secure state of code execution.
- Provisions for message passing in multi-core systems.
- Full support of C++ run-time environments.
- C interface which is binary compatible across
@@ -266,7 +266,7 @@
- Deterministic context switching.
- Round-robin context switching.
- Deadlock avoidance, for example with priority inversion.
- - Zero interrupt latency by using ARMv7-M instructions LDREX and STREX.
+ - Zero interrupt latency by using Armv7-M instructions LDREX and STREX.
\section usingOS2 Using a CMSIS-RTOS2 Implementation
@@ -338,7 +338,7 @@
/**
\page rtx5_impl RTX v5 Implementation
-Keil RTX version 5 (RTX5) implements the CMSIS-RTOS2 as a native RTOS interface for ARM Cortex-M processor-based devices.
+Keil RTX version 5 (RTX5) implements the CMSIS-RTOS2 as a native RTOS interface for Arm Cortex-M processor-based devices.
A translation layer to CMSIS-RTOS API v1 is provided. Therefore, RTX5 can be used in applications that where previously based
on RTX version 4 and CMSIS-RTOS version 1 with minimal effort.
@@ -389,9 +389,9 @@
\image html manage_rte_cortex-a.png
The default implementations provided along with CMSIS are
-- ARM <a href="../../Core_A/html/group__GIC__functions.html">Generic Interrupt Controller (GIC)</a>
-- ARM Cortex-A5, Cortex-A9 <a href="../../Core_A/html/group__PTM__timer__functions.html">Private Timer (PTIM)</a>
-- ARM Cortex-A7 <a href="../../Core_A/html/group__PL1__timer__functions.html">Generic Physical Timer (GTIM)</a>
+- Arm <a href="../../Core_A/html/group__GIC__functions.html">Generic Interrupt Controller (GIC)</a>
+- Arm Cortex-A5, Cortex-A9 <a href="../../Core_A/html/group__PTM__timer__functions.html">Private Timer (PTIM)</a>
+- Arm Cortex-A7 <a href="../../Core_A/html/group__PL1__timer__functions.html">Generic Physical Timer (GTIM)</a>
For devices not implementing GIC, PTIM nor GTIM please refer to the according device family pack and select the
proper implementations.
@@ -742,7 +742,7 @@
\endcode
\note
-\c __WFE() is not available in every ARM Cortex-M implementation. Check device manuals for availability.
+\c __WFE() is not available in every Arm Cortex-M implementation. Check device manuals for availability.
The alternative using \c __WFI() has other issues, please take note of http://www.keil.com/support/docs/3591.htm as well.
\section rtx_os_h RTX5 Header File
@@ -1079,7 +1079,7 @@
-# From the <b>Project</b> window you find the list of source files required for a complete library build.
-# Build the library of your choice using \b Project - \b Build \b Target (or press F7).
-\image html own_lib_projwin.png "Project with files for ARMv8-M Mainline"
+\image html own_lib_projwin.png "Project with files for Armv8-M Mainline"
*/
@@ -1145,7 +1145,7 @@
\section libFiles RTX v5 Library Files
The CMSIS-RTOS RTX Library is available pre-compiled for ARMCC and GCC compilers and supports all Cortex-M
-processor variants in every configuration, including ARM Cortex-M23 and Cortex-M33.
+processor variants in every configuration, including Arm Cortex-M23 and Cortex-M33.
<table class="cmtable" summary="CMSIS-RTOS RTX Library Files">
<tr>
@@ -1166,27 +1166,27 @@
</tr>
<tr>
<td>Library/ARM/RTX_V8MB.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M baseline.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline.</td>
</tr>
<tr>
<td>Library/ARM/RTX_V8MBN.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M baseline, non-secure.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline, non-secure.</td>
</tr>
<tr>
<td>Library/ARM/RTX_V8MM.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline.</td>
</tr>
<tr>
<td>Library/ARM/RTX_V8MMF.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline with FPU.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU.</td>
</tr>
<tr>
<td>Library/ARM/RTX_V8MMFN.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline with FPU, non-secure.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>
</tr>
<tr>
<td>Library/ARM/RTX_V8MMN.lib</td>
- <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline, non-secure.</td>
+ <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline, non-secure.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_CM0.a</td>
@@ -1202,27 +1202,27 @@
</tr>
<tr>
<td>Library/GCC/libRTX_V8MB.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M baseline.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_V8MBN.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M baseline, non-secure.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline, non-secure.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_V8MM.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_V8MMF.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline with FPU.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_V8MMFN.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline with FPU, non-secure.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>
</tr>
<tr>
<td>Library/GCC/libRTX_V8MMN.a</td>
- <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline, non-secure.</td>
+ <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline, non-secure.</td>
</tr>
</table>
*/
@@ -1235,14 +1235,14 @@
Keil RTX5 is developed and tested using the common toolchains and development environments.
-\subsection technicalData_Toolchain_ARM ARM Compiler (ARM/Keil MDK, uVision5)
+\subsection technicalData_Toolchain_ARM Arm Compiler (Arm/Keil MDK, uVision5)
-Major parts of RTX5 are developed and optimized using ARM Compiler and ARM/Keil MDK.
+Major parts of RTX5 are developed and optimized using Arm Compiler and Arm/Keil MDK.
The current release is tested with the following versions:
<ul>
- <li>ARM Compiler 5.06 Update 6</li>
- <li>ARM Compiler 6.6.2 (Long Term Maintenance)</li>
- <li>ARM Compiler 6.9</li>
+ <li>Arm Compiler 5.06 Update 6</li>
+ <li>Arm Compiler 6.6.2 (Long Term Maintenance)</li>
+ <li>Arm Compiler 6.9</li>
<li>RTOS-aware debugging with uVision 5.24</li>
</ul>
@@ -1260,7 +1260,7 @@
RTX5 has also been ported to support GCC, maintenance mainly relays on community contribution.
Active development is currently tested with:
<ul>
- <li>GNU Tools for ARM Embedded 6.3.1 20170620</li>
+ <li>GNU Tools for Arm Embedded 6.3.1 20170620</li>
</ul>
\section technicalData5_ControlBlockSizes Control Block Sizes
@@ -1727,7 +1727,7 @@
/**
\page rtosValidation RTOS Validation
-ARM offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
+Arm offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
The <b>ARM::CMSIS-RTOS_Validation</b> Pack contains the following:
- Source code of a CMSIS-RTOS Validation Suite along with configuration file.
@@ -1783,7 +1783,7 @@
\page functionOverview Function Overview
CMSIS-RTOS v2 provides multiple API interfaces:
- - \subpage rtos_api2 is the new C function API that supports dynamic object creation and ARMv8-M (ARM Cortex-M23 and
+ - \subpage rtos_api2 is the new C function API that supports dynamic object creation and Armv8-M (Arm Cortex-M23 and
Cortex-M33).
- <a class="el" href="../../RTOS/html/functionOverview.html">CMSIS-RTOS C API v1</a> is a C function API that is backward
compatible with CMSIS-RTOS v1.
diff --git a/CMSIS/DoxyGen/SVD/src/svd.txt b/CMSIS/DoxyGen/SVD/src/svd.txt
index ae9daaa..69650ce 100644
--- a/CMSIS/DoxyGen/SVD/src/svd.txt
+++ b/CMSIS/DoxyGen/SVD/src/svd.txt
@@ -4,7 +4,7 @@
Introduction
------------
The CMSIS System View Description format(CMSIS-SVD) formalizes the description of the system
-contained in ARM Cortex-M processor-based microcontrollers, in particular, the memory mapped
+contained in Arm Cortex-M processor-based microcontrollers, in particular, the memory mapped
registers of peripherals.
The detail contained in system view descriptions is comparable to the data in device
reference manuals. The information ranges from high level functional
@@ -233,7 +233,7 @@
</tr>
<tr>
<td> \-\-generate=partition </td>
- <td>Generate Partition file for Cortex-M Security Extensions (ARMv8M)</td>
+ <td>Generate Partition file for Cortex-M Security Extensions (Armv8-M)</td>
<td>Generates the device partition file. The name of the generated file is composed of <em>partition_</em> and the value of the device <em>\<name></em>
(for example, <em>partition_CMSDK_ARMv8MBL.h</em>).
Refer to \ref elem_device. The content of the file uses Configuration Wizard annotations and is derived
diff --git a/CMSIS/DoxyGen/SVD/src/svd_schema.txt b/CMSIS/DoxyGen/SVD/src/svd_schema.txt
index db4cf1a..c7125e2 100644
--- a/CMSIS/DoxyGen/SVD/src/svd_schema.txt
+++ b/CMSIS/DoxyGen/SVD/src/svd_schema.txt
@@ -51,11 +51,11 @@
<name>ARM_Cortex_M4</name>
<series>ARMCM4</series>
<version>0.1</version>
- <description>ARM Cortex-M4 based Microcontroller demonstration device</description>
+ <description>Arm Cortex-M4 based Microcontroller demonstration device</description>
<licenseText>
- ARM Limited (ARM) is supplying this software for use with Cortex-M \n
+ Arm Limited (Arm) is supplying this software for use with Cortex-M \n
processor based microcontrollers. This file can be freely distributed \n
- within development tools that are supporting such ARM based processors. \n
+ within development tools that are supporting such Arm based processors. \n
\n
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n
@@ -80,7 +80,7 @@
This example describes a device from the vendor \token{ARM Ltd.} using \token{ARM} as short name.
The device belongs to the device family \token{ARMCM4}. The device description is at version \token{0.1} and uniquely identifies the device by the name \token{ARM_Cortex_M4}. The legal disclaimer in the header files generated from
-this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the
+this description is captured and formatted in accordance to the standard Arm CMSIS disclaimer. The CMSIS system file included by the
generated device header file is named \token{system_ARMCM4.h} and all type definitions will be prepended with \token{ARM_}.
The peripherals are memory mapped in a byte-addressable address space with a bus width of \token{32} bits.
@@ -305,7 +305,7 @@
with fixed \token{little} endian memory scheme, including \token{Memory Protection Unit} and
\token{double precision hardware Floating Point Unit}. It has a \token{data cache} and no \token{instruction} nor
a tightly coupled memory. The Nested Vectored Interrupt Controller uses \token{4} bits
-to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM.
+to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by Arm.
\anchor elem_cpu_sc
\b /device/cpu
@@ -327,26 +327,26 @@
<tr>
<td>name</td>
<td>The predefined tokens are:
- - \token{CM0}: ARM Cortex-M0
- - \token{CM0PLUS}: ARM Cortex-M0+
- - \token{CM0+}: ARM Cortex-M0+
- - \token{CM1}: ARM Cortex-M1
- - \token{SC000}: ARM Secure Core SC000
- - \token{CM23}: ARM Cortex-M23
- - \token{CM3}: ARM Cortex-M3
- - \token{CM33}: ARM Cortex-M33
- - \token{SC300}: ARM Secure Core SC300
- - \token{CM4}: ARM Cortex-M4
- - \token{CM7}: ARM Cortex-M7
- - \token{CA5}: ARM Cortex-A5
- - \token{CA7}: ARM Cortex-A7
- - \token{CA8}: ARM Cortex-A8
- - \token{CA9}: ARM Cortex-A9
- - \token{CA15}: ARM Cortex-A15
- - \token{CA17}: ARM Cortex-A17
- - \token{CA53}: ARM Cortex-A53
- - \token{CA57}: ARM Cortex-A57
- - \token{CA72}: ARM Cortex-A72
+ - \token{CM0}: Arm Cortex-M0
+ - \token{CM0PLUS}: Arm Cortex-M0+
+ - \token{CM0+}: Arm Cortex-M0+
+ - \token{CM1}: Arm Cortex-M1
+ - \token{SC000}: Arm Secure Core SC000
+ - \token{CM23}: Arm Cortex-M23
+ - \token{CM3}: Arm Cortex-M3
+ - \token{CM33}: Arm Cortex-M33
+ - \token{SC300}: Arm Secure Core SC300
+ - \token{CM4}: Arm Cortex-M4
+ - \token{CM7}: Arm Cortex-M7
+ - \token{CA5}: Arm Cortex-A5
+ - \token{CA7}: Arm Cortex-A7
+ - \token{CA8}: Arm Cortex-A8
+ - \token{CA9}: Arm Cortex-A9
+ - \token{CA15}: Arm Cortex-A15
+ - \token{CA17}: Arm Cortex-A17
+ - \token{CA53}: Arm Cortex-A53
+ - \token{CA57}: Arm Cortex-A57
+ - \token{CA72}: Arm Cortex-A72
- \token{other}: other processor architectures
</td>
<td>cpuNameType </td>
@@ -360,11 +360,11 @@
</tr>
<tr>
<td>endian </td>
- <td>Define the endianess of the processor being one of:
+ <td>Define the endianness of the processor being one of:
- \token{little}: little endian memory (least significant byte gets allocated at the lowest address).
- \token{big}: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
- \token{selectable}: little and big endian are configurable for the device and become active after the next reset.
- - \token{other}: the endianess is neither little nor big endian.
+ - \token{other}: the endianness is neither little nor big endian.
</td>
<td>endianType </td>
<td>1..1 </td>
@@ -428,7 +428,7 @@
</tr>
<tr>
<td>vendorSystickConfig</td>
- <td>Indicate whether the processor implements a vendor-specific System Tick Timer. If \token{false}, then the ARM-defined System Tick Timer is available. If \token{true}, then a vendor-specific System Tick Timer must be implemented. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
+ <td>Indicate whether the processor implements a vendor-specific System Tick Timer. If \token{false}, then the Arm-defined System Tick Timer is available. If \token{true}, then a vendor-specific System Tick Timer must be implemented. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
<td>boolean </td>
<td>1..1 </td>
</tr>
@@ -2295,7 +2295,7 @@
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<name>ARM_Cortex_M3</name>
<version>0.1</version>
- <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+ <description>Arm Cortex-M3 based Microcontroller demonstration device</description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
diff --git a/CMSIS/DoxyGen/Zone/src/XML_Format.txt b/CMSIS/DoxyGen/Zone/src/XML_Format.txt
index 9ff2c06..9cd0b52 100644
--- a/CMSIS/DoxyGen/Zone/src/XML_Format.txt
+++ b/CMSIS/DoxyGen/Zone/src/XML_Format.txt
@@ -174,7 +174,7 @@
\code
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<system xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
- <!-- ARM SoC with Cortex-M4 processor -->
+ <!-- Arm SoC with Cortex-M4 processor -->
<device Dname="ARM32CM4128x">
<processor Pname="Cortex-M4">
:
@@ -503,13 +503,13 @@
</tr>
<tr>
<td>Dtz</td>
- <td>Specifies whether an ARMv8M based device implements TrustZone.</td>
+ <td>Specifies whether an Armv8-M based device implements TrustZone.</td>
<td>DtzEnum</td>
<td>optional</td>
</tr>
<tr>
<td>Ddsp</td>
- <td>Specifies whether an ARMv8M based device supports the DSP instructions set.</td>
+ <td>Specifies whether an Armv8-M based device supports the DSP instructions set.</td>
<td>DdspEnum</td>
<td>optional</td>
</tr>
diff --git a/CMSIS/Driver/DriverTemplates/Driver_CAN.c b/CMSIS/Driver/DriverTemplates/Driver_CAN.c
index a243062..b4fdede 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_CAN.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_CAN.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2015-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c b/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c
index 387cb0b..9e54e26 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c b/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c
index edc60b5..971fade 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_Flash.c b/CMSIS/Driver/DriverTemplates/Driver_Flash.c
index 7a5b13f..0f221da 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_Flash.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_Flash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_I2C.c b/CMSIS/Driver/DriverTemplates/Driver_I2C.c
index 580d653..99d82dd 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_I2C.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_I2C.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_MCI.c b/CMSIS/Driver/DriverTemplates/Driver_MCI.c
index 4128ee8..a515074 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_MCI.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_MCI.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_SAI.c b/CMSIS/Driver/DriverTemplates/Driver_SAI.c
index ce5c7c0..bc0746c 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_SAI.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_SAI.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_SPI.c b/CMSIS/Driver/DriverTemplates/Driver_SPI.c
index bf22540..9f31654 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_SPI.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_SPI.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_Storage.c b/CMSIS/Driver/DriverTemplates/Driver_Storage.c
index d72c9b7..2b24436 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_Storage.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_Storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_USART.c b/CMSIS/Driver/DriverTemplates/Driver_USART.c
index 38981af..6270a4c 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_USART.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_USART.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_USBD.c b/CMSIS/Driver/DriverTemplates/Driver_USBD.c
index 35b8b0c..effbdf7 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_USBD.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_USBD.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/Driver/DriverTemplates/Driver_USBH.c b/CMSIS/Driver/DriverTemplates/Driver_USBH.c
index b86622d..12074ed 100644
--- a/CMSIS/Driver/DriverTemplates/Driver_USBH.c
+++ b/CMSIS/Driver/DriverTemplates/Driver_USBH.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Config/handlers.c b/CMSIS/RTOS2/RTX/Config/handlers.c
index 193ee03..1cc56d7 100644
--- a/CMSIS/RTOS2/RTX/Config/handlers.c
+++ b/CMSIS/RTOS2/RTX/Config/handlers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -124,17 +124,17 @@
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const uint32_t THUMB = 2U;
const uint32_t ARM = 4U;
(void)LR;
//Lazy VFP/NEON initialisation and switching
- // (ARM ARM section A7.5) VFP data processing instruction?
- // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
- // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
- // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+ // (Arm Architecture Reference Manual section A7.5) VFP data processing instruction?
+ // (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction?
+ // (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction?
+ // (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction?
if ((state == ARM && ((opcode & 0x0C000000U) >> 26U == 0x03U)) ||
(state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) {
if (((opcode & 0x00000E00U) >> 9U) == 5U) {
@@ -143,10 +143,10 @@
}
}
- // (ARM ARM section A7.4) NEON data processing instruction?
+ // (Arm Architecture Reference Manual section A7.4) NEON data processing instruction?
if ((state == ARM && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) ||
(state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) ||
- // (ARM ARM section A7.7) NEON load/store instruction?
+ // (Arm Architecture Reference Manual section A7.7) NEON load/store instruction?
(state == ARM && ((opcode >> 24U) == 0xF4U)) ||
(state == THUMB && ((opcode >> 24U) == 0xF9U))) {
__FPU_Enable();
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_c.h b/CMSIS/RTOS2/RTX/Source/rtx_core_c.h
index c027cfa..343f316 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_c.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_c.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -36,7 +36,7 @@
(!defined(__ARM_ARCH_7EM__)) && \
(!defined(__ARM_ARCH_8M_BASE__)) && \
(!defined(__ARM_ARCH_8M_MAIN__)))
-#error "Unknown ARM Architecture!"
+#error "Unknown Arm Architecture!"
#endif
#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
index fe3d213..c30dac7 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -52,7 +52,7 @@
/// xPSR_Initialization Value
/// \param[in] privileged true=privileged, false=unprivileged
-/// \param[in] thumb true=Thumb, false=ARM
+/// \param[in] thumb true=Thumb, false=Arm
/// \return xPSR Init Value
__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
uint32_t psr;
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
index ec6936c..0295c19 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_delay.c b/CMSIS/RTOS2/RTX/Source/rtx_delay.c
index 30c0b95..ada82ac 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_delay.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_evflags.c b/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
index 8cdf8a6..e02560a 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_evr.c b/CMSIS/RTOS2/RTX/Source/rtx_evr.c
index 8e7740d..4148efa 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_evr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_kernel.c b/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
index e7b8e1e..21cbf73 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_lib.c b/CMSIS/RTOS2/RTX/Source/rtx_lib.c
index 1e51e59..9c52f7e 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_lib.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_lib.h b/CMSIS/RTOS2/RTX/Source/rtx_lib.h
index ef89965..1fd876c 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_lib.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_lib.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_memory.c b/CMSIS/RTOS2/RTX/Source/rtx_memory.c
index 113e668..b22bfda 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_memory.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_mempool.c b/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
index 99f1697..b048eff 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c b/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
index 28d1e92..9fbffdb 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_mutex.c b/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
index aded3f3..609d4f4 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c b/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
index 0402756..a1f8d4c 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_system.c b/CMSIS/RTOS2/RTX/Source/rtx_system.c
index c3e1719..f7acbf0 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_system.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_system.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_thread.c b/CMSIS/RTOS2/RTX/Source/rtx_thread.c
index d1053e5..2c4c4c3 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_thread.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_timer.c b/CMSIS/RTOS2/RTX/Source/rtx_timer.c
index fc81e93..450123f 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+++ b/CMSIS/RTOS2/RTX/Source/rtx_timer.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/CMSIS/RTOS2/RTX/Template/svc_user.c b/CMSIS/RTOS2/RTX/Template/svc_user.c
index 6d5583f..ee73c6f 100644
--- a/CMSIS/RTOS2/RTX/Template/svc_user.c
+++ b/CMSIS/RTOS2/RTX/Template/svc_user.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Include/ARMCA5.h b/Device/ARM/ARMCA5/Include/ARMCA5.h
index 02d80d2..ef268f7 100644
--- a/Device/ARM/ARMCA5/Include/ARMCA5.h
+++ b/Device/ARM/ARMCA5/Include/ARMCA5.h
@@ -2,13 +2,13 @@
* @file ARMCA5.h
* @brief CMSIS Cortex-A5 Core Peripheral Access Layer Header File
* @version V1.00
- * @data 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Include/mem_ARMCA5.h b/Device/ARM/ARMCA5/Include/mem_ARMCA5.h
index 10efc94..04669d0 100644
--- a/Device/ARM/ARMCA5/Include/mem_ARMCA5.h
+++ b/Device/ARM/ARMCA5/Include/mem_ARMCA5.h
@@ -2,13 +2,13 @@
* @file mem_ARMCA5.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.00
- * @date 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Include/system_ARMCA5.h b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
index 7d48ceb..6a2a6da 100644
--- a/Device/ARM/ARMCA5/Include/system_ARMCA5.h
+++ b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA5.h
- * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
* @version V1.00
- * @date 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
index 6cf9cb3..6dce5be 100644
--- a/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA5.c
- * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.00
- * @date 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
index 0bffdc8..535a200 100644
--- a/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA5.c
- * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
index 7c8c7d4..8adfa20 100644
--- a/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA5.c
- * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c b/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c
index 1633bd7..71a09e6 100644
--- a/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c
@@ -2,13 +2,13 @@
* @file mmu_ARMCA5.c
* @brief MMU Configuration for ARM Cortex-A5 Device Series
* @version V1.00
- * @date 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA5/Source/system_ARMCA5.c b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
index a8a272c..18176a8 100644
--- a/Device/ARM/ARMCA5/Source/system_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA5.c
- * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.00
- * @date 16 Mar 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Include/ARMCA7.h b/Device/ARM/ARMCA7/Include/ARMCA7.h
index b634a82..913e5be 100644
--- a/Device/ARM/ARMCA7/Include/ARMCA7.h
+++ b/Device/ARM/ARMCA7/Include/ARMCA7.h
@@ -2,13 +2,13 @@
* @file ARMCA7.h
* @brief CMSIS Cortex-A7 Core Peripheral Access Layer Header File
* @version V1.00
- * @data 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Include/mem_ARMCA7.h b/Device/ARM/ARMCA7/Include/mem_ARMCA7.h
index 70e402e..3011c98 100644
--- a/Device/ARM/ARMCA7/Include/mem_ARMCA7.h
+++ b/Device/ARM/ARMCA7/Include/mem_ARMCA7.h
@@ -2,13 +2,13 @@
* @file mem_ARMCA7.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Include/system_ARMCA7.h b/Device/ARM/ARMCA7/Include/system_ARMCA7.h
index 7012680..0405aa3 100644
--- a/Device/ARM/ARMCA7/Include/system_ARMCA7.h
+++ b/Device/ARM/ARMCA7/Include/system_ARMCA7.h
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA7.h
- * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
index 47ef974..a5047f5 100644
--- a/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA7.c
- * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
index f514de7..b523581 100644
--- a/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA7.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
index dcce016..59d8bce 100644
--- a/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA7.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c b/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c
index d65df5e..1395f5a 100644
--- a/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c
@@ -1,14 +1,14 @@
/**************************************************************************//**
* @file mmu_ARMCA7.c
- * @brief MMU Configuration for ARM Cortex-A7 Device Series
+ * @brief MMU Configuration for Arm Cortex-A7 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -25,7 +25,7 @@
* limitations under the License.
*/
-/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
diff --git a/Device/ARM/ARMCA7/Source/system_ARMCA7.c b/Device/ARM/ARMCA7/Source/system_ARMCA7.c
index 77a9780..7e566de 100644
--- a/Device/ARM/ARMCA7/Source/system_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/system_ARMCA7.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA7.c
- * @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Include/ARMCA9.h b/Device/ARM/ARMCA9/Include/ARMCA9.h
index 7e5517a..7c5c12d 100644
--- a/Device/ARM/ARMCA9/Include/ARMCA9.h
+++ b/Device/ARM/ARMCA9/Include/ARMCA9.h
@@ -2,13 +2,13 @@
* @file ARMCA9.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version V1.00
- * @data 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Include/mem_ARMCA9.h b/Device/ARM/ARMCA9/Include/mem_ARMCA9.h
index 4bebfdf..16ccb19 100644
--- a/Device/ARM/ARMCA9/Include/mem_ARMCA9.h
+++ b/Device/ARM/ARMCA9/Include/mem_ARMCA9.h
@@ -2,13 +2,13 @@
* @file mem_ARMCA9.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Include/system_ARMCA9.h b/Device/ARM/ARMCA9/Include/system_ARMCA9.h
index 97e3d39..b60ce5a 100644
--- a/Device/ARM/ARMCA9/Include/system_ARMCA9.h
+++ b/Device/ARM/ARMCA9/Include/system_ARMCA9.h
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA9.h
- * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
index c3f5696..8d3161e 100644
--- a/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA9.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
index e0a6ed7..a4b7ed8 100644
--- a/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA9.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c
index 8374fdb..460bfb6 100644
--- a/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file startup_ARMCA9.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c b/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
index 960808e..e7f05a0 100644
--- a/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
@@ -1,14 +1,14 @@
/**************************************************************************//**
* @file mmu_ARMCA9.c
- * @brief MMU Configuration for ARM Cortex-A9 Device Series
+ * @brief MMU Configuration for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -25,7 +25,7 @@
* limitations under the License.
*/
-/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
diff --git a/Device/ARM/ARMCA9/Source/system_ARMCA9.c b/Device/ARM/ARMCA9/Source/system_ARMCA9.c
index aa26f1b..eb6fdd4 100644
--- a/Device/ARM/ARMCA9/Source/system_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/system_ARMCA9.c
@@ -1,14 +1,14 @@
/******************************************************************************
* @file system_ARMCA9.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.00
- * @date 22 Feb 2017
+ * @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0/Include/ARMCM0.h b/Device/ARM/ARMCM0/Include/ARMCM0.h
index 083a219..7b20a61 100644
--- a/Device/ARM/ARMCM0/Include/ARMCM0.h
+++ b/Device/ARM/ARMCM0/Include/ARMCM0.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0/Include/system_ARMCM0.h b/Device/ARM/ARMCM0/Include/system_ARMCM0.h
index 8f2f287..ceac9d2 100644
--- a/Device/ARM/ARMCM0/Include/system_ARMCM0.h
+++ b/Device/ARM/ARMCM0/Include/system_ARMCM0.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM0 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
index 35e8427..6be97a4 100644
--- a/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
+++ b/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM0 Device Series
* @version V5.00
- * @date 26. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0/Source/system_ARMCM0.c b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
index bb0d5eb..0703ff8 100644
--- a/Device/ARM/ARMCM0/Source/system_ARMCM0.c
+++ b/Device/ARM/ARMCM0/Source/system_ARMCM0.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM0 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h b/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
index 1b66391..462f77a 100644
--- a/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
+++ b/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h b/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
index 968226b..1293e64 100644
--- a/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
+++ b/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h b/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
index 28d0c85..fa1c5cb 100644
--- a/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
+++ b/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
index c297b58..7c927f8 100644
--- a/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
+++ b/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 26. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
index 7709542..1bb66ec 100644
--- a/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
+++ b/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM0plus Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Include/ARMCM23.h b/Device/ARM/ARMCM23/Include/ARMCM23.h
index b9674fc..a11405c 100644
--- a/Device/ARM/ARMCM23/Include/ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/ARMCM23.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM23 Device Series
* @version V5.00
- * @date 09. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h b/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
index c688b53..a10bb7b 100644
--- a/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
+++ b/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM23 Device Series
* @version V5.00
- * @date 09. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h b/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
index f2354ee..165b8f5 100644
--- a/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h
@@ -2,10 +2,10 @@
* @file partition_ARMCM23.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
* @version V5.00
- * @date 28. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Include/system_ARMCM23.h b/Device/ARM/ARMCM23/Include/system_ARMCM23.h
index 5a2bf8e..f584ff3 100644
--- a/Device/ARM/ARMCM23/Include/system_ARMCM23.h
+++ b/Device/ARM/ARMCM23/Include/system_ARMCM23.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM23 Device Series
* @version V5.00
- * @date 21. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
index 46569ce..8580338 100644
--- a/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
+++ b/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM23 Device Series
* @version V5.00
- * @date 21. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM23/Source/system_ARMCM23.c b/Device/ARM/ARMCM23/Source/system_ARMCM23.c
index 0bfd52b..32e8946 100644
--- a/Device/ARM/ARMCM23/Source/system_ARMCM23.c
+++ b/Device/ARM/ARMCM23/Source/system_ARMCM23.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM23 Device Series
* @version V5.00
- * @date 21. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM3/Include/ARMCM3.h b/Device/ARM/ARMCM3/Include/ARMCM3.h
index 94e544d..d6892a9 100644
--- a/Device/ARM/ARMCM3/Include/ARMCM3.h
+++ b/Device/ARM/ARMCM3/Include/ARMCM3.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM3 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM3/Include/system_ARMCM3.h b/Device/ARM/ARMCM3/Include/system_ARMCM3.h
index d579848..3835987 100644
--- a/Device/ARM/ARMCM3/Include/system_ARMCM3.h
+++ b/Device/ARM/ARMCM3/Include/system_ARMCM3.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM3 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
index 9f7c76a..d7de2ab 100644
--- a/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
+++ b/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM3 Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM3/Source/system_ARMCM3.c b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
index 658d154..3f9abfd 100644
--- a/Device/ARM/ARMCM3/Source/system_ARMCM3.c
+++ b/Device/ARM/ARMCM3/Source/system_ARMCM3.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33.h b/Device/ARM/ARMCM33/Include/ARMCM33.h
index defcaa7..1558a10 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM33 Device Series (configured for ARMCM33 without FPU, without DSP extension, without TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
index b2c79e8..2d16a1b 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM33 Device Series (configured for ARMCM33 with FPU, with DSP extension)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
index 6afc4cb..eae3b93 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM33 Device Series (configured for ARMCM33 with FPU, with DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h b/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
index 6b0de5d..d5e5063 100644
--- a/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
+++ b/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM33 Device Series (configured for ARMCM33 without FPU, without DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
index f0a4f1b..f065734 100644
--- a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
@@ -2,10 +2,10 @@
* @file partition_ARMCM33.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
* @version V5.0.1
- * @date 07. December 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Include/system_ARMCM33.h b/Device/ARM/ARMCM33/Include/system_ARMCM33.h
index 5985e09..c4b7197 100644
--- a/Device/ARM/ARMCM33/Include/system_ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/system_ARMCM33.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM33 Device Series
* @version V5.00
- * @date 21. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
index 80702f4..e8411d6 100644
--- a/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
+++ b/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM33 Device Series
* @version V5.00
- * @date 21. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM33/Source/system_ARMCM33.c b/Device/ARM/ARMCM33/Source/system_ARMCM33.c
index 9ad7594..9006f8e 100644
--- a/Device/ARM/ARMCM33/Source/system_ARMCM33.c
+++ b/Device/ARM/ARMCM33/Source/system_ARMCM33.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM33 Device Series
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM4/Include/ARMCM4.h b/Device/ARM/ARMCM4/Include/ARMCM4.h
index e4007e1..591842c 100644
--- a/Device/ARM/ARMCM4/Include/ARMCM4.h
+++ b/Device/ARM/ARMCM4/Include/ARMCM4.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM4 Device Series (configured for CM4 without FPU)
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM4/Include/ARMCM4_FP.h b/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
index 8bed056..992597f 100644
--- a/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
+++ b/Device/ARM/ARMCM4/Include/ARMCM4_FP.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM4 Device Series (configured for CM4 with FPU)
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM4/Include/system_ARMCM4.h b/Device/ARM/ARMCM4/Include/system_ARMCM4.h
index f6e6d84..f0fe73d 100644
--- a/Device/ARM/ARMCM4/Include/system_ARMCM4.h
+++ b/Device/ARM/ARMCM4/Include/system_ARMCM4.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM4 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
index 1afe878..3b967c8 100644
--- a/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
+++ b/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM4/Source/system_ARMCM4.c b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
index af23005..7f634ab 100644
--- a/Device/ARM/ARMCM4/Source/system_ARMCM4.c
+++ b/Device/ARM/ARMCM4/Source/system_ARMCM4.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM4 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7.h b/Device/ARM/ARMCM7/Include/ARMCM7.h
index 7dcf85c..494aac3 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device Series (configured for CM7 without FPU)
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
index 535501a..10cb789 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device Series (configured for CM7 with double precision FPU)
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
index 2319621..bf79627 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device Series (configured for CM7 with single precision FPU)
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Include/system_ARMCM7.h b/Device/ARM/ARMCM7/Include/system_ARMCM7.h
index ee1c39d..66291a6 100644
--- a/Device/ARM/ARMCM7/Include/system_ARMCM7.h
+++ b/Device/ARM/ARMCM7/Include/system_ARMCM7.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMCM7 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
index 26edb9f..1c050b8 100644
--- a/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
+++ b/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMCM7 Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMCM7/Source/system_ARMCM7.c b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
index 22edd9c..9245dcf 100644
--- a/Device/ARM/ARMCM7/Source/system_ARMCM7.c
+++ b/Device/ARM/ARMCM7/Source/system_ARMCM7.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMCM7 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC000/Include/ARMSC000.h b/Device/ARM/ARMSC000/Include/ARMSC000.h
index f2fb5a9..b68565b 100644
--- a/Device/ARM/ARMSC000/Include/ARMSC000.h
+++ b/Device/ARM/ARMSC000/Include/ARMSC000.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMSC000 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC000/Include/system_ARMSC000.h b/Device/ARM/ARMSC000/Include/system_ARMSC000.h
index 0d80907..4e05e35 100644
--- a/Device/ARM/ARMSC000/Include/system_ARMSC000.h
+++ b/Device/ARM/ARMSC000/Include/system_ARMSC000.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMSC000 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
index 3a0538f..6490592 100644
--- a/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
+++ b/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMSC000 Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC000/Source/system_ARMSC000.c b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
index fabb4e9..af3668e 100644
--- a/Device/ARM/ARMSC000/Source/system_ARMSC000.c
+++ b/Device/ARM/ARMSC000/Source/system_ARMSC000.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* for ARMSC000 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC300/Include/ARMSC300.h b/Device/ARM/ARMSC300/Include/ARMSC300.h
index d5ccff0..fd46f60 100644
--- a/Device/ARM/ARMSC300/Include/ARMSC300.h
+++ b/Device/ARM/ARMSC300/Include/ARMSC300.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMSC300 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC300/Include/system_ARMSC300.h b/Device/ARM/ARMSC300/Include/system_ARMSC300.h
index 26ffa5f..f9df630 100644
--- a/Device/ARM/ARMSC300/Include/system_ARMSC300.h
+++ b/Device/ARM/ARMSC300/Include/system_ARMSC300.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMSC300 Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
index 6ecf9df..bb1ef02 100644
--- a/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
+++ b/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMSC300 Device Series
* @version V5.00
- * @date 26. Aprl 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMSC300/Source/system_ARMSC300.c b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
index adf87e9..d81c17e 100644
--- a/Device/ARM/ARMSC300/Source/system_ARMSC300.c
+++ b/Device/ARM/ARMSC300/Source/system_ARMSC300.c
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Source File for
* ARMSC300 Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
index f0b839d..c839c49 100644
--- a/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h
@@ -3,10 +3,10 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMv8MBL Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
index d8a7d67..27603ae 100644
--- a/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h
@@ -2,10 +2,10 @@
* @file partition_ARMv8MBL.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8M
* @version V5.00
- * @date 27. October 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h b/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
index 49187cc..9822a36 100644
--- a/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
+++ b/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h
@@ -3,10 +3,10 @@
* @brief CMSIS Device System Header File for
* ARMv8MBL Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
index 14242f9..0719fb9 100644
--- a/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
+++ b/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c
@@ -3,10 +3,10 @@
* @brief CMSIS Core Device Startup File for
* ARMv8MBL Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
index 2f398b7..10dfa0b 100644
--- a/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
+++ b/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file system_ARMv8MBL.c
* @brief CMSIS Device System Source File for
- * ARMv8MBL Device Series
+ * Armv8-M Baseline Device Series
* @version V5.00
- * @date 07. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML.h b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
index 3e42f4f..bf21338 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML without FPU, without DSP extension, with TrustZone)
+ * Armv8-M Mainline Device Series (configured for Armv8-M Mainline without FPU, without DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
index f709ef5..797019e 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML with double precision FPU, without DSP extension, with TrustZone)
+ * Armv8-MML Device Series (configured for Armv8-MML with double precision FPU, without DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- ARMv8 Mainline Specific Interrupt Numbers --------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
index 3cb9733..0d80498 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML without FPU, with DSP extension, with TrustZone)
+ * Armv8-M Mainline Device Series (configured for Armv8-M Mainline without FPU, with DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
index d4dd760..6c2c77f 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML with double precision FPU, with DSP extension, with TrustZone)
+ * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with double precision FPU, with DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
index 7da4723..e64c21d 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML with single precision FPU, with DSP extension, with TrustZone)
+ * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with single precision FPU, with DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h b/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
index 49ea8b3..3b22488 100644
--- a/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
+++ b/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file ARMv8MML_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
- * ARMv8MML Device Series (configured for ARMv8MML with single precision FPU, without DSP extension, with TrustZone)
+ * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with single precision FPU, without DSP extension, with TrustZone)
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -35,7 +35,7 @@
typedef enum IRQn
{
-/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
+/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -47,7 +47,7 @@
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
+/* -------------------- Armv8-M Mainline Specific Interrupt Numbers ------------- */
WDT_IRQn = 0, /* Watchdog Timer Interrupt */
RTC_IRQn = 1, /* Real Time Clock Interrupt */
TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */
diff --git a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
index 79e0c4f..1d1c4c2 100644
--- a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file partition_ARMv8MML.h
- * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8M
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8-M Mainline
* @version V5.0.1
- * @date 07. December 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h b/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
index fa9ef38..deff40d 100644
--- a/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file system_ARMv8MML.h
* @brief CMSIS Device System Header File for
- * ARMv8MML Device Series
+ * Armv8-M Mainline Device Series
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
index fef0728..564523c 100644
--- a/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
+++ b/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file startup_ARMv8MML.s
* @brief CMSIS Core Device Startup File for
- * ARMv8MML Device Series
+ * Armv8-M Mainline Device Series
* @version V5.00
- * @date 26. April 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -86,7 +86,7 @@
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
-/* ARMv8MML Processor Exceptions */
+/* Armv8-M Mainline Processor Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
@@ -98,7 +98,7 @@
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-/* ARMv8MML Specific Interrupts */
+/* Armv8-M Mainline Specific Interrupts */
void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
@@ -128,7 +128,7 @@
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
- /* ARMv8MML Exceptions Handler */
+ /* Armv8-M Mainline Exceptions Handler */
(pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
diff --git a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
index 95828e5..bb044c0 100644
--- a/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
+++ b/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c
@@ -1,12 +1,12 @@
/**************************************************************************//**
* @file system_ARMv8MML.c
* @brief CMSIS Device System Source File for
- * ARMv8MML Device Series
+ * Armv8-M Mainline Device Series
* @version V5.00
- * @date 02. November 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Flash/FlashDev.c b/Device/_Template_Flash/FlashDev.c
index 24334a9..bcdfbbd 100644
--- a/Device/_Template_Flash/FlashDev.c
+++ b/Device/_Template_Flash/FlashDev.c
@@ -1,37 +1,27 @@
-/* Copyright (c) 2010 - 2018 Arm Ltd.
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of Arm nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/***********************************************************************/
-/* */
-/* FlashDev.c: Flash Device Description */
-/* for New Device Flash */
-/* */
-/***********************************************************************/
-
+/**************************************************************************//**
+ * @file FlashDev.c
+ * @brief Flash Device Description for New Device Flash
+ * @version V1.0.0
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
#include "FlashOS.h" // FlashOS Structures
diff --git a/Device/_Template_Flash/FlashOS.h b/Device/_Template_Flash/FlashOS.h
index 8fc4c58..350e309 100644
--- a/Device/_Template_Flash/FlashOS.h
+++ b/Device/_Template_Flash/FlashOS.h
@@ -1,37 +1,27 @@
-/* Copyright (c) 2010 - 2018 Arm Ltd.
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of Arm nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/***********************************************************************/
-/* */
-/* FlashOS.h: Data structures and entries */
-/* for Flash Programming Functions */
-/* */
-/***********************************************************************/
-
+/**************************************************************************//**
+ * @file FlashOS.h
+ * @brief Data structures and entries Functions
+ * @version V1.0.0
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
#define VERS 1 // Interface Version 1.01
#define UNKNOWN 0 // Unknown
diff --git a/Device/_Template_Flash/FlashPrg.c b/Device/_Template_Flash/FlashPrg.c
index 219a7f7..c2d7412 100644
--- a/Device/_Template_Flash/FlashPrg.c
+++ b/Device/_Template_Flash/FlashPrg.c
@@ -1,37 +1,27 @@
-/* Copyright (c) 2010 - 2018 Arm Ltd.
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of Arm nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/***********************************************************************/
-/* */
-/* FlashPrg.c: Flash Programming Functions adapted */
-/* for New Device Flash */
-/* */
-/***********************************************************************/
-
+/**************************************************************************//**
+ * @file FlashPrg.c
+ * @brief Flash Programming Functions adapted for New Device Flash
+ * @version V1.0.0
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
#include "FlashOS.h" // FlashOS Structures
/*
diff --git a/Device/_Template_Vendor/ReadMe.txt b/Device/_Template_Vendor/ReadMe.txt
index af75f9e..00dbd82 100644
--- a/Device/_Template_Vendor/ReadMe.txt
+++ b/Device/_Template_Vendor/ReadMe.txt
@@ -1,8 +1,8 @@
/*****************************************************************************
* @file ReadMe.txt
* @brief Explanation how to use the Device folder and template files
- * @version V3.02
- * @date 11. June 2014
+ * @version V3.0.3
+ * @date 10. January 2018
*****************************************************************************/
Following directory structure and template files are given:
@@ -18,10 +18,10 @@
|
+- system_<Device>.c system source file
|
- +-- ARM ARM RVCT toolchain
+ +-- ARM Arm RVCT toolchain
| +- startup_<Device>.s ASM startup file for ARMCC
|
- +-- GCC ARM GNU toolchain
+ +-- GCC Arm GNU toolchain
|
+-- IAR IAR toolchain
diff --git a/Device/_Template_Vendor/Vendor/Device/Include/Device.h b/Device/_Template_Vendor/Vendor/Device/Include/Device.h
index c97a832..16f0ea2 100644
--- a/Device/_Template_Vendor/Vendor/Device/Include/Device.h
+++ b/Device/_Template_Vendor/Vendor/Device/Include/Device.h
@@ -3,10 +3,10 @@
* @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for
* Device <Device>
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -91,7 +91,7 @@
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
-/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
__CM0_REV if your device is a Cortex-M0 device
@@ -119,7 +119,7 @@
core_cm3.h if your device is a CORTEX-M3 device
core_cm4.h if your device is a CORTEX-M4 device
core_cm7.h if your device is a CORTEX-M4 device */
-#include <core_cm#.h> /*!< ARM Cortex-M# processor and core peripherals */
+#include <core_cm#.h> /*!< Arm Cortex-M# processor and core peripherals */
/* ToDo: include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /*!< <Device> System */
diff --git a/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h b/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h
index 85a6d61..eae9e09 100644
--- a/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h
+++ b/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h
@@ -3,10 +3,10 @@
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device <Device>
* @version V5.00
- * @date 02. March 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c b/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c
index 5ac6026..65e958f 100644
--- a/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c
@@ -3,10 +3,10 @@
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for
* Device <Device>
* @version V5.00
- * @date 28. September 2016
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h b/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h
index 964b558..ef203a3 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h
+++ b/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h
@@ -2,10 +2,10 @@
* @file <Device>.h
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
* @version V1.00
- * @date 30 March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -92,7 +92,7 @@
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
-/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */
+/* =========================== Configuration of the Arm Cortex-A Processor and Core Peripherals ============================ */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
5U if your device is a CORTEX-A5 device
@@ -112,7 +112,7 @@
core_ca5.h if your device is a CORTEX-A5 device
core_ca7.h if your device is a CORTEX-A7 device
core_ca9.h if your device is a CORTEX-A9 device */
-#include <core_ca#.h> /*!< ARM Cortex-A# processor and core peripherals */
+#include <core_ca#.h> /*!< Arm Cortex-A# processor and core peripherals */
/* ToDo: include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /*!< <Device> System */
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h b/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h
index 45865c8..4a116ab 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h
+++ b/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h
@@ -2,10 +2,10 @@
* @file mem_<Device>.h
* @brief CMSIS Cortex-A Memory base and size definitions (used in scatter file)
* @version V1.00
- * @date 30. March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h b/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h
index cd07e29..fb19dcd 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h
+++ b/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h
@@ -2,10 +2,10 @@
* @file system_<Device>.h
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V5.00
- * @date 30. March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c b/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
index 1a960be..d0e8384 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c
@@ -2,10 +2,10 @@
* @file startup_<Device>.c
* @brief CMSIS Cortex-A Device Startup
* @version V1.00
- * @date 30 March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c b/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c
index 31ea726..1a5cdd6 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c
@@ -3,10 +3,10 @@
* @brief MMU Configuration
* Device <DeviceAbbreviation>
* @version V1.00
- * @date 30. March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -26,7 +26,7 @@
/* Memory map description
ToDo: add in this file your device memory map description
- following is an example of a Cortex-A9 ARM FVP device
+ following is an example of a Cortex-A9 Arm FVP device
Memory Type
0xFFFFFFFF |--------------------------| ------------
diff --git a/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c b/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
index 0a1681c..98a424c 100644
--- a/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
+++ b/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c
@@ -2,10 +2,10 @@
* @file system_<Device>.c
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V1.00
- * @date 30. March 2017
+ * @date 10. January 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/README.md b/README.md
index c3c6529..bc9867c 100644
--- a/README.md
+++ b/README.md
@@ -9,14 +9,14 @@
A [pre-built documentation](http://www.keil.com/pack/doc/CMSIS_Dev/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release).
## What's Hot
- - CMSIS-RTOS2: RTX 5 is now available for IAR, GCC, ARM Compiler 5, ARM Compiler 6
+ - CMSIS-RTOS2: RTX 5 is now available for IAR, GCC, Arm Compiler 5, Arm Compiler 6
- CMSIS-RTOS2: FreeRTOS adoption (release) is available https://github.com/ARM-software/CMSIS-FreeRTOS
- CMSIS-Core: compiler agnostic features extended to simplify transition on LLVM based front-end
- CMSIS-Core-A: preview of the CMSIS-Core for Cortex-A
- Coming soon: CMSIS-RTOS2 for Cortex-A
## Implemented Enhancements
- - Support for ARMv8-M Architecture (Mainline and Baseline) as well as devices Cortex-M23 and Cortex-M33
+ - Support for Armv8-M Architecture (Mainline and Baseline) as well as devices Cortex-M23 and Cortex-M33
- CMSIS-RTOS Version 2 API and RTX reference implementation with several enhancements:
- Dynamic object creation, Flag events, C API, additional thread and timer functions
@@ -44,7 +44,7 @@
| CMSIS/Driver | CMSIS-Driver API headers and template files |
| CMSIS/DSP | CMSIS-DSP related files |
| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
-| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & ARMv8-M) |
+| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) |
| CMSIS/Pack | CMSIS-Pack examples and tutorials |
| CMSIS/DoxyGen | Source of the documentation |
| CMSIS/Utilities | Utility programs |
@@ -68,7 +68,7 @@
## License
-ARM CMSIS is licensed under Apache-2.0.
+Arm CMSIS is licensed under Apache-2.0.
## Contributions and Pull Requests