David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | menu "IRQ chip support" |
| 3 | |
| 4 | config IRQCHIP |
| 5 | def_bool y |
| 6 | depends on OF_IRQ |
| 7 | |
| 8 | config ARM_GIC |
| 9 | bool |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 10 | select IRQ_DOMAIN_HIERARCHY |
| 11 | select GENERIC_IRQ_MULTI_HANDLER |
| 12 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 13 | |
| 14 | config ARM_GIC_PM |
| 15 | bool |
| 16 | depends on PM |
| 17 | select ARM_GIC |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 18 | |
| 19 | config ARM_GIC_MAX_NR |
| 20 | int |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 21 | depends on ARM_GIC |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 22 | default 2 if ARCH_REALVIEW |
| 23 | default 1 |
| 24 | |
| 25 | config ARM_GIC_V2M |
| 26 | bool |
| 27 | depends on PCI |
| 28 | select ARM_GIC |
| 29 | select PCI_MSI |
| 30 | |
| 31 | config GIC_NON_BANKED |
| 32 | bool |
| 33 | |
| 34 | config ARM_GIC_V3 |
| 35 | bool |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 36 | select GENERIC_IRQ_MULTI_HANDLER |
| 37 | select IRQ_DOMAIN_HIERARCHY |
| 38 | select PARTITION_PERCPU |
| 39 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 40 | |
| 41 | config ARM_GIC_V3_ITS |
| 42 | bool |
| 43 | select GENERIC_MSI_IRQ_DOMAIN |
| 44 | default ARM_GIC_V3 |
| 45 | |
| 46 | config ARM_GIC_V3_ITS_PCI |
| 47 | bool |
| 48 | depends on ARM_GIC_V3_ITS |
| 49 | depends on PCI |
| 50 | depends on PCI_MSI |
| 51 | default ARM_GIC_V3_ITS |
| 52 | |
| 53 | config ARM_GIC_V3_ITS_FSL_MC |
| 54 | bool |
| 55 | depends on ARM_GIC_V3_ITS |
| 56 | depends on FSL_MC_BUS |
| 57 | default ARM_GIC_V3_ITS |
| 58 | |
| 59 | config ARM_NVIC |
| 60 | bool |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 61 | select IRQ_DOMAIN_HIERARCHY |
| 62 | select GENERIC_IRQ_CHIP |
| 63 | |
| 64 | config ARM_VIC |
| 65 | bool |
| 66 | select IRQ_DOMAIN |
| 67 | select GENERIC_IRQ_MULTI_HANDLER |
| 68 | |
| 69 | config ARM_VIC_NR |
| 70 | int |
| 71 | default 4 if ARCH_S5PV210 |
| 72 | default 2 |
| 73 | depends on ARM_VIC |
| 74 | help |
| 75 | The maximum number of VICs available in the system, for |
| 76 | power management. |
| 77 | |
| 78 | config ARMADA_370_XP_IRQ |
| 79 | bool |
| 80 | select GENERIC_IRQ_CHIP |
| 81 | select PCI_MSI if PCI |
| 82 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 83 | |
| 84 | config ALPINE_MSI |
| 85 | bool |
| 86 | depends on PCI |
| 87 | select PCI_MSI |
| 88 | select GENERIC_IRQ_CHIP |
| 89 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 90 | config AL_FIC |
| 91 | bool "Amazon's Annapurna Labs Fabric Interrupt Controller" |
| 92 | depends on OF || COMPILE_TEST |
| 93 | select GENERIC_IRQ_CHIP |
| 94 | select IRQ_DOMAIN |
| 95 | help |
| 96 | Support Amazon's Annapurna Labs Fabric Interrupt Controller. |
| 97 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 98 | config ATMEL_AIC_IRQ |
| 99 | bool |
| 100 | select GENERIC_IRQ_CHIP |
| 101 | select IRQ_DOMAIN |
| 102 | select GENERIC_IRQ_MULTI_HANDLER |
| 103 | select SPARSE_IRQ |
| 104 | |
| 105 | config ATMEL_AIC5_IRQ |
| 106 | bool |
| 107 | select GENERIC_IRQ_CHIP |
| 108 | select IRQ_DOMAIN |
| 109 | select GENERIC_IRQ_MULTI_HANDLER |
| 110 | select SPARSE_IRQ |
| 111 | |
| 112 | config I8259 |
| 113 | bool |
| 114 | select IRQ_DOMAIN |
| 115 | |
| 116 | config BCM6345_L1_IRQ |
| 117 | bool |
| 118 | select GENERIC_IRQ_CHIP |
| 119 | select IRQ_DOMAIN |
| 120 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 121 | |
| 122 | config BCM7038_L1_IRQ |
| 123 | bool |
| 124 | select GENERIC_IRQ_CHIP |
| 125 | select IRQ_DOMAIN |
| 126 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 127 | |
| 128 | config BCM7120_L2_IRQ |
| 129 | bool |
| 130 | select GENERIC_IRQ_CHIP |
| 131 | select IRQ_DOMAIN |
| 132 | |
| 133 | config BRCMSTB_L2_IRQ |
| 134 | bool |
| 135 | select GENERIC_IRQ_CHIP |
| 136 | select IRQ_DOMAIN |
| 137 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 138 | config DAVINCI_AINTC |
| 139 | bool |
| 140 | select GENERIC_IRQ_CHIP |
| 141 | select IRQ_DOMAIN |
| 142 | |
| 143 | config DAVINCI_CP_INTC |
| 144 | bool |
| 145 | select GENERIC_IRQ_CHIP |
| 146 | select IRQ_DOMAIN |
| 147 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 148 | config DW_APB_ICTL |
| 149 | bool |
| 150 | select GENERIC_IRQ_CHIP |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 151 | select IRQ_DOMAIN_HIERARCHY |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 152 | |
| 153 | config FARADAY_FTINTC010 |
| 154 | bool |
| 155 | select IRQ_DOMAIN |
| 156 | select GENERIC_IRQ_MULTI_HANDLER |
| 157 | select SPARSE_IRQ |
| 158 | |
| 159 | config HISILICON_IRQ_MBIGEN |
| 160 | bool |
| 161 | select ARM_GIC_V3 |
| 162 | select ARM_GIC_V3_ITS |
| 163 | |
| 164 | config IMGPDC_IRQ |
| 165 | bool |
| 166 | select GENERIC_IRQ_CHIP |
| 167 | select IRQ_DOMAIN |
| 168 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 169 | config IXP4XX_IRQ |
| 170 | bool |
| 171 | select IRQ_DOMAIN |
| 172 | select GENERIC_IRQ_MULTI_HANDLER |
| 173 | select SPARSE_IRQ |
| 174 | |
| 175 | config MADERA_IRQ |
| 176 | tristate |
| 177 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 178 | config IRQ_MIPS_CPU |
| 179 | bool |
| 180 | select GENERIC_IRQ_CHIP |
Olivier Deprez | 92d4c21 | 2022-12-06 15:05:30 +0100 | [diff] [blame] | 181 | select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 182 | select IRQ_DOMAIN |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 183 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 184 | |
| 185 | config CLPS711X_IRQCHIP |
| 186 | bool |
| 187 | depends on ARCH_CLPS711X |
| 188 | select IRQ_DOMAIN |
| 189 | select GENERIC_IRQ_MULTI_HANDLER |
| 190 | select SPARSE_IRQ |
| 191 | default y |
| 192 | |
| 193 | config OMPIC |
| 194 | bool |
| 195 | |
| 196 | config OR1K_PIC |
| 197 | bool |
| 198 | select IRQ_DOMAIN |
| 199 | |
| 200 | config OMAP_IRQCHIP |
| 201 | bool |
| 202 | select GENERIC_IRQ_CHIP |
| 203 | select IRQ_DOMAIN |
| 204 | |
| 205 | config ORION_IRQCHIP |
| 206 | bool |
| 207 | select IRQ_DOMAIN |
| 208 | select GENERIC_IRQ_MULTI_HANDLER |
| 209 | |
| 210 | config PIC32_EVIC |
| 211 | bool |
| 212 | select GENERIC_IRQ_CHIP |
| 213 | select IRQ_DOMAIN |
| 214 | |
| 215 | config JCORE_AIC |
| 216 | bool "J-Core integrated AIC" if COMPILE_TEST |
| 217 | depends on OF |
| 218 | select IRQ_DOMAIN |
| 219 | help |
| 220 | Support for the J-Core integrated AIC. |
| 221 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 222 | config RDA_INTC |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 223 | bool |
| 224 | select IRQ_DOMAIN |
| 225 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 226 | config RENESAS_INTC_IRQPIN |
| 227 | bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST |
| 228 | select IRQ_DOMAIN |
| 229 | help |
| 230 | Enable support for the Renesas Interrupt Controller for external |
| 231 | interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. |
| 232 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 233 | config RENESAS_IRQC |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 234 | bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 235 | select GENERIC_IRQ_CHIP |
| 236 | select IRQ_DOMAIN |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 237 | help |
| 238 | Enable support for the Renesas Interrupt Controller for external |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 239 | devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 240 | |
| 241 | config RENESAS_RZA1_IRQC |
| 242 | bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST |
| 243 | select IRQ_DOMAIN_HIERARCHY |
| 244 | help |
| 245 | Enable support for the Renesas RZ/A1 Interrupt Controller, to use up |
| 246 | to 8 external interrupts with configurable sense select. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 247 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 248 | config SL28CPLD_INTC |
| 249 | bool "Kontron sl28cpld IRQ controller" |
| 250 | depends on MFD_SL28CPLD=y || COMPILE_TEST |
| 251 | select REGMAP_IRQ |
| 252 | help |
| 253 | Interrupt controller driver for the board management controller |
| 254 | found on the Kontron sl28 CPLD. |
| 255 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 256 | config ST_IRQCHIP |
| 257 | bool |
| 258 | select REGMAP |
| 259 | select MFD_SYSCON |
| 260 | help |
| 261 | Enables SysCfg Controlled IRQs on STi based platforms. |
| 262 | |
| 263 | config TANGO_IRQ |
| 264 | bool |
| 265 | select IRQ_DOMAIN |
| 266 | select GENERIC_IRQ_CHIP |
| 267 | |
| 268 | config TB10X_IRQC |
| 269 | bool |
| 270 | select IRQ_DOMAIN |
| 271 | select GENERIC_IRQ_CHIP |
| 272 | |
| 273 | config TS4800_IRQ |
| 274 | tristate "TS-4800 IRQ controller" |
| 275 | select IRQ_DOMAIN |
| 276 | depends on HAS_IOMEM |
| 277 | depends on SOC_IMX51 || COMPILE_TEST |
| 278 | help |
| 279 | Support for the TS-4800 FPGA IRQ controller |
| 280 | |
| 281 | config VERSATILE_FPGA_IRQ |
| 282 | bool |
| 283 | select IRQ_DOMAIN |
| 284 | |
| 285 | config VERSATILE_FPGA_IRQ_NR |
| 286 | int |
| 287 | default 4 |
| 288 | depends on VERSATILE_FPGA_IRQ |
| 289 | |
| 290 | config XTENSA_MX |
| 291 | bool |
| 292 | select IRQ_DOMAIN |
| 293 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
| 294 | |
| 295 | config XILINX_INTC |
| 296 | bool |
| 297 | select IRQ_DOMAIN |
| 298 | |
| 299 | config IRQ_CROSSBAR |
| 300 | bool |
| 301 | help |
| 302 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
| 303 | The primary irqchip invokes the crossbar's callback which inturn allocates |
| 304 | a free irq and configures the IP. Thus the peripheral interrupts are |
| 305 | routed to one of the free irqchip interrupt lines. |
| 306 | |
| 307 | config KEYSTONE_IRQ |
| 308 | tristate "Keystone 2 IRQ controller IP" |
| 309 | depends on ARCH_KEYSTONE |
| 310 | help |
| 311 | Support for Texas Instruments Keystone 2 IRQ controller IP which |
| 312 | is part of the Keystone 2 IPC mechanism |
| 313 | |
| 314 | config MIPS_GIC |
| 315 | bool |
Olivier Deprez | 92d4c21 | 2022-12-06 15:05:30 +0100 | [diff] [blame] | 316 | select GENERIC_IRQ_IPI if SMP |
| 317 | select IRQ_DOMAIN_HIERARCHY |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 318 | select MIPS_CM |
| 319 | |
| 320 | config INGENIC_IRQ |
| 321 | bool |
| 322 | depends on MACH_INGENIC |
| 323 | default y |
| 324 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 325 | config INGENIC_TCU_IRQ |
| 326 | bool "Ingenic JZ47xx TCU interrupt controller" |
| 327 | default MACH_INGENIC |
| 328 | depends on MIPS || COMPILE_TEST |
| 329 | select MFD_SYSCON |
| 330 | select GENERIC_IRQ_CHIP |
| 331 | help |
| 332 | Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic |
| 333 | JZ47xx SoCs. |
| 334 | |
| 335 | If unsure, say N. |
| 336 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 337 | config RENESAS_H8300H_INTC |
| 338 | bool |
| 339 | select IRQ_DOMAIN |
| 340 | |
| 341 | config RENESAS_H8S_INTC |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 342 | bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 343 | select IRQ_DOMAIN |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 344 | help |
| 345 | Enable support for the Renesas H8/300 Interrupt Controller, as found |
| 346 | on Renesas H8S SoCs. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 347 | |
| 348 | config IMX_GPCV2 |
| 349 | bool |
| 350 | select IRQ_DOMAIN |
| 351 | help |
| 352 | Enables the wakeup IRQs for IMX platforms with GPCv2 block |
| 353 | |
| 354 | config IRQ_MXS |
| 355 | def_bool y if MACH_ASM9260 || ARCH_MXS |
| 356 | select IRQ_DOMAIN |
| 357 | select STMP_DEVICE |
| 358 | |
| 359 | config MSCC_OCELOT_IRQ |
| 360 | bool |
| 361 | select IRQ_DOMAIN |
| 362 | select GENERIC_IRQ_CHIP |
| 363 | |
| 364 | config MVEBU_GICP |
| 365 | bool |
| 366 | |
| 367 | config MVEBU_ICU |
| 368 | bool |
| 369 | |
| 370 | config MVEBU_ODMI |
| 371 | bool |
| 372 | select GENERIC_MSI_IRQ_DOMAIN |
| 373 | |
| 374 | config MVEBU_PIC |
| 375 | bool |
| 376 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 377 | config MVEBU_SEI |
| 378 | bool |
| 379 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 380 | config LS_EXTIRQ |
| 381 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
| 382 | select MFD_SYSCON |
| 383 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 384 | config LS_SCFG_MSI |
| 385 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
| 386 | depends on PCI && PCI_MSI |
| 387 | |
| 388 | config PARTITION_PERCPU |
| 389 | bool |
| 390 | |
| 391 | config EZNPS_GIC |
| 392 | bool "NPS400 Global Interrupt Manager (GIM)" |
| 393 | depends on ARC || (COMPILE_TEST && !64BIT) |
| 394 | select IRQ_DOMAIN |
| 395 | help |
| 396 | Support the EZchip NPS400 global interrupt controller |
| 397 | |
| 398 | config STM32_EXTI |
| 399 | bool |
| 400 | select IRQ_DOMAIN |
| 401 | select GENERIC_IRQ_CHIP |
| 402 | |
| 403 | config QCOM_IRQ_COMBINER |
| 404 | bool "QCOM IRQ combiner support" |
| 405 | depends on ARCH_QCOM && ACPI |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 406 | select IRQ_DOMAIN_HIERARCHY |
| 407 | help |
| 408 | Say yes here to add support for the IRQ combiner devices embedded |
| 409 | in Qualcomm Technologies chips. |
| 410 | |
| 411 | config IRQ_UNIPHIER_AIDET |
| 412 | bool "UniPhier AIDET support" if COMPILE_TEST |
| 413 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 414 | default ARCH_UNIPHIER |
| 415 | select IRQ_DOMAIN_HIERARCHY |
| 416 | help |
| 417 | Support for the UniPhier AIDET (ARM Interrupt Detector). |
| 418 | |
| 419 | config MESON_IRQ_GPIO |
| 420 | bool "Meson GPIO Interrupt Multiplexer" |
| 421 | depends on ARCH_MESON |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 422 | select IRQ_DOMAIN_HIERARCHY |
| 423 | help |
| 424 | Support Meson SoC Family GPIO Interrupt Multiplexer |
| 425 | |
| 426 | config GOLDFISH_PIC |
| 427 | bool "Goldfish programmable interrupt controller" |
| 428 | depends on MIPS && (GOLDFISH || COMPILE_TEST) |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 429 | select GENERIC_IRQ_CHIP |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 430 | select IRQ_DOMAIN |
| 431 | help |
| 432 | Say yes here to enable Goldfish interrupt controller driver used |
| 433 | for Goldfish based virtual platforms. |
| 434 | |
| 435 | config QCOM_PDC |
| 436 | bool "QCOM PDC" |
| 437 | depends on ARCH_QCOM |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 438 | select IRQ_DOMAIN_HIERARCHY |
| 439 | help |
| 440 | Power Domain Controller driver to manage and configure wakeup |
| 441 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. |
| 442 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 443 | config CSKY_MPINTC |
| 444 | bool "C-SKY Multi Processor Interrupt Controller" |
| 445 | depends on CSKY |
| 446 | help |
| 447 | Say yes here to enable C-SKY SMP interrupt controller driver used |
| 448 | for C-SKY SMP system. |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 449 | In fact it's not mmio map in hardware and it uses ld/st to visit the |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 450 | controller's register inside CPU. |
| 451 | |
| 452 | config CSKY_APB_INTC |
| 453 | bool "C-SKY APB Interrupt Controller" |
| 454 | depends on CSKY |
| 455 | help |
| 456 | Say yes here to enable C-SKY APB interrupt controller driver used |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 457 | by C-SKY single core SOC system. It uses mmio map apb-bus to visit |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 458 | the controller's register. |
| 459 | |
| 460 | config IMX_IRQSTEER |
| 461 | bool "i.MX IRQSTEER support" |
| 462 | depends on ARCH_MXC || COMPILE_TEST |
| 463 | default ARCH_MXC |
| 464 | select IRQ_DOMAIN |
| 465 | help |
| 466 | Support for the i.MX IRQSTEER interrupt multiplexer/remapper. |
| 467 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 468 | config IMX_INTMUX |
| 469 | bool "i.MX INTMUX support" if COMPILE_TEST |
| 470 | default y if ARCH_MXC |
| 471 | select IRQ_DOMAIN |
| 472 | help |
| 473 | Support for the i.MX INTMUX interrupt multiplexer. |
| 474 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 475 | config LS1X_IRQ |
| 476 | bool "Loongson-1 Interrupt Controller" |
| 477 | depends on MACH_LOONGSON32 |
| 478 | default y |
| 479 | select IRQ_DOMAIN |
| 480 | select GENERIC_IRQ_CHIP |
| 481 | help |
| 482 | Support for the Loongson-1 platform Interrupt Controller. |
| 483 | |
| 484 | config TI_SCI_INTR_IRQCHIP |
| 485 | bool |
| 486 | depends on TI_SCI_PROTOCOL |
| 487 | select IRQ_DOMAIN_HIERARCHY |
| 488 | help |
| 489 | This enables the irqchip driver support for K3 Interrupt router |
| 490 | over TI System Control Interface available on some new TI's SoCs. |
| 491 | If you wish to use interrupt router irq resources managed by the |
| 492 | TI System Controller, say Y here. Otherwise, say N. |
| 493 | |
| 494 | config TI_SCI_INTA_IRQCHIP |
| 495 | bool |
| 496 | depends on TI_SCI_PROTOCOL |
| 497 | select IRQ_DOMAIN_HIERARCHY |
| 498 | select TI_SCI_INTA_MSI_DOMAIN |
| 499 | help |
| 500 | This enables the irqchip driver support for K3 Interrupt aggregator |
| 501 | over TI System Control Interface available on some new TI's SoCs. |
| 502 | If you wish to use interrupt aggregator irq resources managed by the |
| 503 | TI System Controller, say Y here. Otherwise, say N. |
| 504 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 505 | config TI_PRUSS_INTC |
| 506 | tristate "TI PRU-ICSS Interrupt Controller" |
| 507 | depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 |
| 508 | select IRQ_DOMAIN |
| 509 | help |
| 510 | This enables support for the PRU-ICSS Local Interrupt Controller |
| 511 | present within a PRU-ICSS subsystem present on various TI SoCs. |
| 512 | The PRUSS INTC enables various interrupts to be routed to multiple |
| 513 | different processors within the SoC. |
| 514 | |
| 515 | config RISCV_INTC |
| 516 | bool "RISC-V Local Interrupt Controller" |
| 517 | depends on RISCV |
| 518 | default y |
| 519 | help |
| 520 | This enables support for the per-HART local interrupt controller |
| 521 | found in standard RISC-V systems. The per-HART local interrupt |
| 522 | controller handles timer interrupts, software interrupts, and |
| 523 | hardware interrupts. Without a per-HART local interrupt controller, |
| 524 | a RISC-V system will be unable to handle any interrupts. |
| 525 | |
| 526 | If you don't know what to do here, say Y. |
| 527 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 528 | config SIFIVE_PLIC |
| 529 | bool "SiFive Platform-Level Interrupt Controller" |
| 530 | depends on RISCV |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 531 | select IRQ_DOMAIN_HIERARCHY |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 532 | help |
| 533 | This enables support for the PLIC chip found in SiFive (and |
| 534 | potentially other) RISC-V systems. The PLIC controls devices |
| 535 | interrupts and connects them to each core's local interrupt |
| 536 | controller. Aside from timer and software interrupts, all other |
| 537 | interrupt sources are subordinate to the PLIC. |
| 538 | |
| 539 | If you don't know what to do here, say Y. |
Olivier Deprez | 0e64123 | 2021-09-23 10:07:05 +0200 | [diff] [blame] | 540 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 541 | config EXYNOS_IRQ_COMBINER |
| 542 | bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST |
| 543 | depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST |
| 544 | help |
| 545 | Say yes here to add support for the IRQ combiner devices embedded |
| 546 | in Samsung Exynos chips. |
| 547 | |
| 548 | config LOONGSON_LIOINTC |
| 549 | bool "Loongson Local I/O Interrupt Controller" |
| 550 | depends on MACH_LOONGSON64 |
| 551 | default y |
| 552 | select IRQ_DOMAIN |
| 553 | select GENERIC_IRQ_CHIP |
| 554 | help |
| 555 | Support for the Loongson Local I/O Interrupt Controller. |
| 556 | |
| 557 | config LOONGSON_HTPIC |
| 558 | bool "Loongson3 HyperTransport PIC Controller" |
| 559 | depends on MACH_LOONGSON64 |
| 560 | default y |
| 561 | select IRQ_DOMAIN |
| 562 | select GENERIC_IRQ_CHIP |
| 563 | help |
| 564 | Support for the Loongson-3 HyperTransport PIC Controller. |
| 565 | |
| 566 | config LOONGSON_HTVEC |
| 567 | bool "Loongson3 HyperTransport Interrupt Vector Controller" |
| 568 | depends on MACH_LOONGSON64 |
| 569 | default MACH_LOONGSON64 |
| 570 | select IRQ_DOMAIN_HIERARCHY |
| 571 | help |
| 572 | Support for the Loongson3 HyperTransport Interrupt Vector Controller. |
| 573 | |
| 574 | config LOONGSON_PCH_PIC |
| 575 | bool "Loongson PCH PIC Controller" |
| 576 | depends on MACH_LOONGSON64 || COMPILE_TEST |
| 577 | default MACH_LOONGSON64 |
| 578 | select IRQ_DOMAIN_HIERARCHY |
| 579 | select IRQ_FASTEOI_HIERARCHY_HANDLERS |
| 580 | help |
| 581 | Support for the Loongson PCH PIC Controller. |
| 582 | |
| 583 | config LOONGSON_PCH_MSI |
| 584 | bool "Loongson PCH MSI Controller" |
| 585 | depends on MACH_LOONGSON64 || COMPILE_TEST |
| 586 | depends on PCI |
| 587 | default MACH_LOONGSON64 |
| 588 | select IRQ_DOMAIN_HIERARCHY |
| 589 | select PCI_MSI |
| 590 | help |
| 591 | Support for the Loongson PCH MSI Controller. |
| 592 | |
| 593 | config MST_IRQ |
| 594 | bool "MStar Interrupt Controller" |
| 595 | depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST |
| 596 | default ARCH_MEDIATEK |
| 597 | select IRQ_DOMAIN |
| 598 | select IRQ_DOMAIN_HIERARCHY |
| 599 | help |
| 600 | Support MStar Interrupt Controller. |
| 601 | |
Olivier Deprez | 0e64123 | 2021-09-23 10:07:05 +0200 | [diff] [blame] | 602 | endmenu |