| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Keystone PCI Controller's common includes |
| 4 | * |
| 5 | * Copyright (C) 2013-2014 Texas Instruments., Ltd. |
| 6 | * http://www.ti.com |
| 7 | * |
| 8 | * Author: Murali Karicheri <m-karicheri2@ti.com> |
| 9 | */ |
| 10 | |
| 11 | #define MAX_MSI_HOST_IRQS 8 |
| 12 | |
| 13 | struct keystone_pcie { |
| 14 | struct dw_pcie *pci; |
| 15 | struct clk *clk; |
| 16 | /* PCI Device ID */ |
| 17 | u32 device_id; |
| 18 | int num_legacy_host_irqs; |
| 19 | int legacy_host_irqs[PCI_NUM_INTX]; |
| 20 | struct device_node *legacy_intc_np; |
| 21 | |
| 22 | int num_msi_host_irqs; |
| 23 | int msi_host_irqs[MAX_MSI_HOST_IRQS]; |
| 24 | struct device_node *msi_intc_np; |
| 25 | struct irq_domain *legacy_irq_domain; |
| 26 | struct device_node *np; |
| 27 | |
| 28 | int error_irq; |
| 29 | |
| 30 | /* Application register space */ |
| 31 | void __iomem *va_app_base; /* DT 1st resource */ |
| 32 | struct resource app; |
| 33 | }; |
| 34 | |
| 35 | /* Keystone DW specific MSI controller APIs/definitions */ |
| 36 | void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset); |
| 37 | phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp); |
| 38 | |
| 39 | /* Keystone specific PCI controller APIs */ |
| 40 | void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie); |
| 41 | void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset); |
| 42 | void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie); |
| 43 | irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie); |
| 44 | int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, |
| 45 | struct device_node *msi_intc_np); |
| 46 | int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 47 | unsigned int devfn, int where, int size, u32 val); |
| 48 | int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 49 | unsigned int devfn, int where, int size, u32 *val); |
| 50 | void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie); |
| 51 | void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie); |
| 52 | void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp); |
| 53 | void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq); |
| 54 | void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq); |
| 55 | void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp); |
| 56 | int ks_dw_pcie_msi_host_init(struct pcie_port *pp); |
| 57 | int ks_dw_pcie_link_up(struct dw_pcie *pci); |