Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | menu "DesignWare PCI Core Support" |
| 4 | depends on PCI |
| 5 | |
| 6 | config PCIE_DW |
| 7 | bool |
| 8 | |
| 9 | config PCIE_DW_HOST |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 10 | bool |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 11 | depends on PCI_MSI_IRQ_DOMAIN |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 12 | select PCIE_DW |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 13 | |
| 14 | config PCIE_DW_EP |
| 15 | bool |
| 16 | depends on PCI_ENDPOINT |
| 17 | select PCIE_DW |
| 18 | |
| 19 | config PCI_DRA7XX |
| 20 | bool |
| 21 | |
| 22 | config PCI_DRA7XX_HOST |
| 23 | bool "TI DRA7xx PCIe controller Host Mode" |
| 24 | depends on SOC_DRA7XX || COMPILE_TEST |
| 25 | depends on PCI_MSI_IRQ_DOMAIN |
| 26 | depends on OF && HAS_IOMEM && TI_PIPE3 |
| 27 | select PCIE_DW_HOST |
| 28 | select PCI_DRA7XX |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 29 | default y if SOC_DRA7XX |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 30 | help |
| 31 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
| 32 | host mode. There are two instances of PCIe controller in DRA7xx. |
| 33 | This controller can work either as EP or RC. In order to enable |
| 34 | host-specific features PCI_DRA7XX_HOST must be selected and in order |
| 35 | to enable device-specific features PCI_DRA7XX_EP must be selected. |
| 36 | This uses the DesignWare core. |
| 37 | |
| 38 | config PCI_DRA7XX_EP |
| 39 | bool "TI DRA7xx PCIe controller Endpoint Mode" |
| 40 | depends on SOC_DRA7XX || COMPILE_TEST |
| 41 | depends on PCI_ENDPOINT |
| 42 | depends on OF && HAS_IOMEM && TI_PIPE3 |
| 43 | select PCIE_DW_EP |
| 44 | select PCI_DRA7XX |
| 45 | help |
| 46 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
| 47 | endpoint mode. There are two instances of PCIe controller in DRA7xx. |
| 48 | This controller can work either as EP or RC. In order to enable |
| 49 | host-specific features PCI_DRA7XX_HOST must be selected and in order |
| 50 | to enable device-specific features PCI_DRA7XX_EP must be selected. |
| 51 | This uses the DesignWare core. |
| 52 | |
| 53 | config PCIE_DW_PLAT |
| 54 | bool |
| 55 | |
| 56 | config PCIE_DW_PLAT_HOST |
| 57 | bool "Platform bus based DesignWare PCIe Controller - Host mode" |
| 58 | depends on PCI && PCI_MSI_IRQ_DOMAIN |
| 59 | select PCIE_DW_HOST |
| 60 | select PCIE_DW_PLAT |
| 61 | help |
| 62 | Enables support for the PCIe controller in the Designware IP to |
| 63 | work in host mode. There are two instances of PCIe controller in |
| 64 | Designware IP. |
| 65 | This controller can work either as EP or RC. In order to enable |
| 66 | host-specific features PCIE_DW_PLAT_HOST must be selected and in |
| 67 | order to enable device-specific features PCI_DW_PLAT_EP must be |
| 68 | selected. |
| 69 | |
| 70 | config PCIE_DW_PLAT_EP |
| 71 | bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" |
| 72 | depends on PCI && PCI_MSI_IRQ_DOMAIN |
| 73 | depends on PCI_ENDPOINT |
| 74 | select PCIE_DW_EP |
| 75 | select PCIE_DW_PLAT |
| 76 | help |
| 77 | Enables support for the PCIe controller in the Designware IP to |
| 78 | work in endpoint mode. There are two instances of PCIe controller |
| 79 | in Designware IP. |
| 80 | This controller can work either as EP or RC. In order to enable |
| 81 | host-specific features PCIE_DW_PLAT_HOST must be selected and in |
| 82 | order to enable device-specific features PCI_DW_PLAT_EP must be |
| 83 | selected. |
| 84 | |
| 85 | config PCI_EXYNOS |
| 86 | bool "Samsung Exynos PCIe controller" |
| 87 | depends on SOC_EXYNOS5440 || COMPILE_TEST |
| 88 | depends on PCI_MSI_IRQ_DOMAIN |
| 89 | select PCIE_DW_HOST |
| 90 | |
| 91 | config PCI_IMX6 |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 92 | bool "Freescale i.MX6/7/8 PCIe controller" |
| 93 | depends on ARCH_MXC || COMPILE_TEST |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 94 | depends on PCI_MSI_IRQ_DOMAIN |
| 95 | select PCIE_DW_HOST |
| 96 | |
| 97 | config PCIE_SPEAR13XX |
| 98 | bool "STMicroelectronics SPEAr PCIe controller" |
| 99 | depends on ARCH_SPEAR13XX || COMPILE_TEST |
| 100 | depends on PCI_MSI_IRQ_DOMAIN |
| 101 | select PCIE_DW_HOST |
| 102 | help |
| 103 | Say Y here if you want PCIe support on SPEAr13XX SoCs. |
| 104 | |
| 105 | config PCI_KEYSTONE |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 106 | bool |
| 107 | |
| 108 | config PCI_KEYSTONE_HOST |
| 109 | bool "PCI Keystone Host Mode" |
| 110 | depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 111 | depends on PCI_MSI_IRQ_DOMAIN |
| 112 | select PCIE_DW_HOST |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 113 | select PCI_KEYSTONE |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 114 | help |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 115 | Enables support for the PCIe controller in the Keystone SoC to |
| 116 | work in host mode. The PCI controller on Keystone is based on |
| 117 | DesignWare hardware and therefore the driver re-uses the |
| 118 | DesignWare core functions to implement the driver. |
| 119 | |
| 120 | config PCI_KEYSTONE_EP |
| 121 | bool "PCI Keystone Endpoint Mode" |
| 122 | depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
| 123 | depends on PCI_ENDPOINT |
| 124 | select PCIE_DW_EP |
| 125 | select PCI_KEYSTONE |
| 126 | help |
| 127 | Enables support for the PCIe controller in the Keystone SoC to |
| 128 | work in endpoint mode. The PCI controller on Keystone is based |
| 129 | on DesignWare hardware and therefore the driver re-uses the |
| 130 | DesignWare core functions to implement the driver. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 131 | |
| 132 | config PCI_LAYERSCAPE |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 133 | bool "Freescale Layerscape PCIe controller - Host mode" |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 134 | depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
| 135 | depends on PCI_MSI_IRQ_DOMAIN |
| 136 | select MFD_SYSCON |
| 137 | select PCIE_DW_HOST |
| 138 | help |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 139 | Say Y here if you want to enable PCIe controller support on Layerscape |
| 140 | SoCs to work in Host mode. |
| 141 | This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
| 142 | determines which PCIe controller works in EP mode and which PCIe |
| 143 | controller works in RC mode. |
| 144 | |
| 145 | config PCI_LAYERSCAPE_EP |
| 146 | bool "Freescale Layerscape PCIe controller - Endpoint mode" |
| 147 | depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
| 148 | depends on PCI_ENDPOINT |
| 149 | select PCIE_DW_EP |
| 150 | help |
| 151 | Say Y here if you want to enable PCIe controller support on Layerscape |
| 152 | SoCs to work in Endpoint mode. |
| 153 | This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
| 154 | determines which PCIe controller works in EP mode and which PCIe |
| 155 | controller works in RC mode. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 156 | |
| 157 | config PCI_HISI |
| 158 | depends on OF && (ARM64 || COMPILE_TEST) |
| 159 | bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" |
| 160 | depends on PCI_MSI_IRQ_DOMAIN |
| 161 | select PCIE_DW_HOST |
| 162 | select PCI_HOST_COMMON |
| 163 | help |
| 164 | Say Y here if you want PCIe controller support on HiSilicon |
| 165 | Hip05 and Hip06 SoCs |
| 166 | |
| 167 | config PCIE_QCOM |
| 168 | bool "Qualcomm PCIe controller" |
| 169 | depends on OF && (ARCH_QCOM || COMPILE_TEST) |
| 170 | depends on PCI_MSI_IRQ_DOMAIN |
| 171 | select PCIE_DW_HOST |
| 172 | help |
| 173 | Say Y here to enable PCIe controller support on Qualcomm SoCs. The |
| 174 | PCIe controller uses the DesignWare core plus Qualcomm-specific |
| 175 | hardware wrappers. |
| 176 | |
| 177 | config PCIE_ARMADA_8K |
| 178 | bool "Marvell Armada-8K PCIe controller" |
| 179 | depends on ARCH_MVEBU || COMPILE_TEST |
| 180 | depends on PCI_MSI_IRQ_DOMAIN |
| 181 | select PCIE_DW_HOST |
| 182 | help |
| 183 | Say Y here if you want to enable PCIe controller support on |
| 184 | Armada-8K SoCs. The PCIe controller on Armada-8K is based on |
| 185 | DesignWare hardware and therefore the driver re-uses the |
| 186 | DesignWare core functions to implement the driver. |
| 187 | |
| 188 | config PCIE_ARTPEC6 |
| 189 | bool |
| 190 | |
| 191 | config PCIE_ARTPEC6_HOST |
| 192 | bool "Axis ARTPEC-6 PCIe controller Host Mode" |
| 193 | depends on MACH_ARTPEC6 || COMPILE_TEST |
| 194 | depends on PCI_MSI_IRQ_DOMAIN |
| 195 | select PCIE_DW_HOST |
| 196 | select PCIE_ARTPEC6 |
| 197 | help |
| 198 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
| 199 | host mode. This uses the DesignWare core. |
| 200 | |
| 201 | config PCIE_ARTPEC6_EP |
| 202 | bool "Axis ARTPEC-6 PCIe controller Endpoint Mode" |
| 203 | depends on MACH_ARTPEC6 || COMPILE_TEST |
| 204 | depends on PCI_ENDPOINT |
| 205 | select PCIE_DW_EP |
| 206 | select PCIE_ARTPEC6 |
| 207 | help |
| 208 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
| 209 | endpoint mode. This uses the DesignWare core. |
| 210 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 211 | config PCIE_INTEL_GW |
| 212 | bool "Intel Gateway PCIe host controller support" |
| 213 | depends on OF && (X86 || COMPILE_TEST) |
| 214 | depends on PCI_MSI_IRQ_DOMAIN |
| 215 | select PCIE_DW_HOST |
| 216 | help |
| 217 | Say 'Y' here to enable PCIe Host controller support on Intel |
| 218 | Gateway SoCs. |
| 219 | The PCIe controller uses the DesignWare core plus Intel-specific |
| 220 | hardware wrappers. |
| 221 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 222 | config PCIE_KIRIN |
| 223 | depends on OF && (ARM64 || COMPILE_TEST) |
| 224 | bool "HiSilicon Kirin series SoCs PCIe controllers" |
| 225 | depends on PCI_MSI_IRQ_DOMAIN |
| 226 | select PCIE_DW_HOST |
| 227 | help |
| 228 | Say Y here if you want PCIe controller support |
| 229 | on HiSilicon Kirin series SoCs. |
| 230 | |
| 231 | config PCIE_HISI_STB |
| 232 | bool "HiSilicon STB SoCs PCIe controllers" |
| 233 | depends on ARCH_HISI || COMPILE_TEST |
| 234 | depends on PCI_MSI_IRQ_DOMAIN |
| 235 | select PCIE_DW_HOST |
| 236 | help |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 237 | Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 238 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 239 | config PCI_MESON |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 240 | tristate "MESON PCIe controller" |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 241 | depends on PCI_MSI_IRQ_DOMAIN |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 242 | default m if ARCH_MESON |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 243 | select PCIE_DW_HOST |
| 244 | help |
| 245 | Say Y here if you want to enable PCI controller support on Amlogic |
| 246 | SoCs. The PCI controller on Amlogic is based on DesignWare hardware |
| 247 | and therefore the driver re-uses the DesignWare core functions to |
| 248 | implement the driver. |
| 249 | |
| 250 | config PCIE_TEGRA194 |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 251 | tristate |
| 252 | |
| 253 | config PCIE_TEGRA194_HOST |
| 254 | tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 255 | depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
| 256 | depends on PCI_MSI_IRQ_DOMAIN |
| 257 | select PCIE_DW_HOST |
| 258 | select PHY_TEGRA194_P2U |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 259 | select PCIE_TEGRA194 |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 260 | help |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 261 | Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
| 262 | work in host mode. There are two instances of PCIe controllers in |
| 263 | Tegra194. This controller can work either as EP or RC. In order to |
| 264 | enable host-specific features PCIE_TEGRA194_HOST must be selected and |
| 265 | in order to enable device-specific features PCIE_TEGRA194_EP must be |
| 266 | selected. This uses the DesignWare core. |
| 267 | |
| 268 | config PCIE_TEGRA194_EP |
| 269 | tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" |
| 270 | depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
| 271 | depends on PCI_ENDPOINT |
| 272 | select PCIE_DW_EP |
| 273 | select PHY_TEGRA194_P2U |
| 274 | select PCIE_TEGRA194 |
| 275 | help |
| 276 | Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
| 277 | work in host mode. There are two instances of PCIe controllers in |
| 278 | Tegra194. This controller can work either as EP or RC. In order to |
| 279 | enable host-specific features PCIE_TEGRA194_HOST must be selected and |
| 280 | in order to enable device-specific features PCIE_TEGRA194_EP must be |
| 281 | selected. This uses the DesignWare core. |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 282 | |
| 283 | config PCIE_UNIPHIER |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 284 | bool "Socionext UniPhier PCIe host controllers" |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 285 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 286 | depends on OF && HAS_IOMEM |
| 287 | depends on PCI_MSI_IRQ_DOMAIN |
| 288 | select PCIE_DW_HOST |
| 289 | help |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 290 | Say Y here if you want PCIe host controller support on UniPhier SoCs. |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 291 | This driver supports LD20 and PXs3 SoCs. |
| 292 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 293 | config PCIE_UNIPHIER_EP |
| 294 | bool "Socionext UniPhier PCIe endpoint controllers" |
| 295 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 296 | depends on OF && HAS_IOMEM |
| 297 | depends on PCI_ENDPOINT |
| 298 | select PCIE_DW_EP |
| 299 | help |
| 300 | Say Y here if you want PCIe endpoint controller support on |
| 301 | UniPhier SoCs. This driver supports Pro5 SoC. |
| 302 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 303 | config PCIE_AL |
| 304 | bool "Amazon Annapurna Labs PCIe controller" |
| 305 | depends on OF && (ARM64 || COMPILE_TEST) |
| 306 | depends on PCI_MSI_IRQ_DOMAIN |
| 307 | select PCIE_DW_HOST |
| 308 | help |
| 309 | Say Y here to enable support of the Amazon's Annapurna Labs PCIe |
| 310 | controller IP on Amazon SoCs. The PCIe controller uses the DesignWare |
| 311 | core plus Annapurna Labs proprietary hardware wrappers. This is |
| 312 | required only for DT-based platforms. ACPI platforms with the |
| 313 | Annapurna Labs PCIe controller don't need to enable this. |
| 314 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 315 | endmenu |