David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* Driver for Realtek PCI-Express card reader |
| 3 | * |
| 4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 5 | * |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | * Author: |
| 7 | * Wei WANG <wei_wang@realsil.com.cn> |
| 8 | */ |
| 9 | |
| 10 | #ifndef __RTSX_PCR_H |
| 11 | #define __RTSX_PCR_H |
| 12 | |
| 13 | #include <linux/rtsx_pci.h> |
| 14 | |
| 15 | #define MIN_DIV_N_PCR 80 |
| 16 | #define MAX_DIV_N_PCR 208 |
| 17 | |
| 18 | #define RTS522A_PM_CTRL3 0xFF7E |
| 19 | |
| 20 | #define RTS524A_PME_FORCE_CTL 0xFF78 |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 21 | #define REG_EFUSE_BYPASS 0x08 |
| 22 | #define REG_EFUSE_POR 0x04 |
| 23 | #define REG_EFUSE_POWER_MASK 0x03 |
| 24 | #define REG_EFUSE_POWERON 0x03 |
| 25 | #define REG_EFUSE_POWEROFF 0x00 |
| 26 | #define RTS5250_CLK_CFG3 0xFF79 |
| 27 | #define RTS525A_CFG_MEM_PD 0xF0 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 28 | #define RTS524A_PM_CTRL3 0xFF7E |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 29 | #define RTS525A_BIOS_CFG 0xFF2D |
| 30 | #define RTS525A_LOAD_BIOS_FLAG 0x01 |
| 31 | #define RTS525A_CLEAR_BIOS_FLAG 0x00 |
| 32 | |
| 33 | #define RTS525A_EFUSE_CTL 0xFC32 |
| 34 | #define REG_EFUSE_ENABLE 0x80 |
| 35 | #define REG_EFUSE_MODE 0x40 |
| 36 | #define RTS525A_EFUSE_ADD 0xFC33 |
| 37 | #define REG_EFUSE_ADD_MASK 0x3F |
| 38 | #define RTS525A_EFUSE_DATA 0xFC35 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 39 | |
| 40 | #define LTR_ACTIVE_LATENCY_DEF 0x883C |
| 41 | #define LTR_IDLE_LATENCY_DEF 0x892C |
| 42 | #define LTR_L1OFF_LATENCY_DEF 0x9003 |
| 43 | #define L1_SNOOZE_DELAY_DEF 1 |
| 44 | #define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF |
| 45 | #define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF |
| 46 | #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC |
| 47 | #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8 |
| 48 | #define CMD_TIMEOUT_DEF 100 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 49 | #define MASK_8_BIT_DEF 0xFF |
| 50 | |
| 51 | #define SSC_CLOCK_STABLE_WAIT 130 |
| 52 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 53 | #define RTS524A_OCP_THD_800 0x04 |
| 54 | #define RTS525A_OCP_THD_800 0x05 |
| 55 | #define RTS522A_OCP_THD_800 0x06 |
| 56 | |
| 57 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 58 | int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); |
| 59 | int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); |
| 60 | |
| 61 | void rts5209_init_params(struct rtsx_pcr *pcr); |
| 62 | void rts5229_init_params(struct rtsx_pcr *pcr); |
| 63 | void rtl8411_init_params(struct rtsx_pcr *pcr); |
| 64 | void rtl8402_init_params(struct rtsx_pcr *pcr); |
| 65 | void rts5227_init_params(struct rtsx_pcr *pcr); |
| 66 | void rts522a_init_params(struct rtsx_pcr *pcr); |
| 67 | void rts5249_init_params(struct rtsx_pcr *pcr); |
| 68 | void rts524a_init_params(struct rtsx_pcr *pcr); |
| 69 | void rts525a_init_params(struct rtsx_pcr *pcr); |
| 70 | void rtl8411b_init_params(struct rtsx_pcr *pcr); |
| 71 | void rts5260_init_params(struct rtsx_pcr *pcr); |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 72 | void rts5261_init_params(struct rtsx_pcr *pcr); |
| 73 | void rts5228_init_params(struct rtsx_pcr *pcr); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 74 | |
| 75 | static inline u8 map_sd_drive(int idx) |
| 76 | { |
| 77 | u8 sd_drive[4] = { |
| 78 | 0x01, /* Type D */ |
| 79 | 0x02, /* Type C */ |
| 80 | 0x05, /* Type A */ |
| 81 | 0x03 /* Type B */ |
| 82 | }; |
| 83 | |
| 84 | return sd_drive[idx]; |
| 85 | } |
| 86 | |
| 87 | #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000)) |
| 88 | #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80)) |
| 89 | #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80) |
| 90 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 91 | #define rtsx_check_mmc_support(reg) ((reg) & 0x10) |
| 92 | #define rtsx_reg_to_rtd3(reg) ((reg) & 0x02) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 93 | #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03) |
| 94 | #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03) |
| 95 | #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03) |
| 96 | #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6) |
| 97 | #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000) |
| 98 | #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03) |
| 99 | #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08)) |
| 100 | #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07) |
| 101 | #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07) |
| 102 | #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8) |
| 103 | #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07) |
| 104 | #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03) |
| 105 | |
| 106 | #define set_pull_ctrl_tables(pcr, __device) \ |
| 107 | do { \ |
| 108 | pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \ |
| 109 | pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \ |
| 110 | pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \ |
| 111 | pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \ |
| 112 | } while (0) |
| 113 | |
| 114 | /* generic operations */ |
| 115 | int rtsx_gops_pm_reset(struct rtsx_pcr *pcr); |
| 116 | int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency); |
| 117 | int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val); |
| 118 | void rtsx_pci_init_ocp(struct rtsx_pcr *pcr); |
| 119 | void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr); |
| 120 | void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr); |
| 121 | int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val); |
| 122 | void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr); |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 123 | void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr); |
| 124 | void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 125 | int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr); |
| 126 | int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr); |
| 127 | |
| 128 | #endif |