| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */ |
| 3 | |
| 4 | #include <linux/bitops.h> |
| 5 | |
| 6 | #define POWER_DOWN_ENABLE 0x01 |
| 7 | #define POWER_DOWN_DISABLE 0x00 |
| 8 | |
| 9 | /* hwrng quality: bits of true entropy per 1024 bits of input */ |
| 10 | #define CC_TRNG_QUALITY 1024 |
| 11 | |
| 12 | /* CryptoCell TRNG HW definitions */ |
| 13 | #define CC_TRNG_NUM_OF_ROSCS 4 |
| 14 | /* The number of words generated in the entropy holding register (EHR) |
| 15 | * 6 words (192 bit) according to HW implementation |
| 16 | */ |
| 17 | #define CC_TRNG_EHR_IN_WORDS 6 |
| 18 | #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32)) |
| 19 | |
| 20 | #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT) |
| 21 | |
| 22 | /* RNG interrupt mask */ |
| 23 | #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \ |
| 24 | BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ |
| 25 | BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \ |
| 26 | BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ |
| 27 | BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) |
| 28 | |
| 29 | // -------------------------------------- |
| 30 | // BLOCK: RNG |
| 31 | // -------------------------------------- |
| 32 | #define CC_RNG_IMR_REG_OFFSET 0x0100UL |
| 33 | #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL |
| 34 | #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL |
| 35 | #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL |
| 36 | #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL |
| 37 | #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL |
| 38 | #define CC_RNG_ISR_REG_OFFSET 0x0104UL |
| 39 | #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL |
| 40 | #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL |
| 41 | #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL |
| 42 | #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL |
| 43 | #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL |
| 44 | #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL |
| 45 | #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL |
| 46 | #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL |
| 47 | #define CC_RNG_ICR_REG_OFFSET 0x0108UL |
| 48 | #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL |
| 49 | #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL |
| 50 | #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL |
| 51 | #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL |
| 52 | #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL |
| 53 | #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL |
| 54 | #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL |
| 55 | #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL |
| 56 | #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL |
| 57 | // -------------------------------------- |
| 58 | // BLOCK: SEC_HOST_RGF |
| 59 | // -------------------------------------- |
| 60 | #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL |
| 61 | #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL |
| 62 | #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL |
| 63 | #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL |
| 64 | |
| 65 | #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL |
| 66 | |
| 67 | // -------------------------------------- |
| 68 | // BLOCK: NVM |
| 69 | // -------------------------------------- |
| 70 | #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL |
| 71 | #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL |
| 72 | #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL |