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review.trustedfirmware.org / hafnium / third_party / linux / 157378f43faad830e4aa3815bde5fa9f9a9f5be6 / . / arch / powerpc / include / asm / pci.h
blob: 6436f0b41539e3f7440fcbdb6b168ad279731bd1 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2#ifndef __ASM_POWERPC_PCI_H
3#define __ASM_POWERPC_PCI_H
4#ifdef __KERNEL__
5
6/*
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]7 */
8
9#include <linux/types.h>
10#include <linux/slab.h>
11#include <linux/string.h>
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]12#include <linux/dma-map-ops.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]13#include <linux/scatterlist.h>
14
15#include <asm/machdep.h>
16#include <asm/io.h>
17#include <asm/prom.h>
18#include <asm/pci-bridge.h>
19
20/* Return values for pci_controller_ops.probe_mode function */
21#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
22#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
23#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
24
25#define PCIBIOS_MIN_IO 0x1000
26#define PCIBIOS_MIN_MEM 0x10000000
27
28/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
29#define IOBASE_BRIDGE_NUMBER 0
30#define IOBASE_MEMORY 1
31#define IOBASE_IO 2
32#define IOBASE_ISA_IO 3
33#define IOBASE_ISA_MEM 4
34
35/*
36 * Set this to 1 if you want the kernel to re-assign all PCI
37 * bus numbers (don't do that on ppc64 yet !)
38 */
39#define pcibios_assign_all_busses() \
40 (pci_has_flag(PCI_REASSIGN_ALL_BUS))
41
42#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
43static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
44{
45 if (ppc_md.pci_get_legacy_ide_irq)
46 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
47 return channel ? 15 : 14;
48}
49
50#ifdef CONFIG_PCI
51extern void set_pci_dma_ops(const struct dma_map_ops *dma_ops);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]52#else /* CONFIG_PCI */
53#define set_pci_dma_ops(d)
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]54#endif
55
56#ifdef CONFIG_PPC64
57
58/*
59 * We want to avoid touching the cacheline size or MWI bit.
60 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
61 * size in all cases) and hardware treats MWI the same as memory write.
62 */
63#define PCI_DISABLE_MWI
64
65#endif /* CONFIG_PPC64 */
66
67extern int pci_domain_nr(struct pci_bus *bus);
68
69/* Decide whether to display the domain number in /proc */
70extern int pci_proc_domain(struct pci_bus *bus);
71
72struct vm_area_struct;
73
74/* Tell PCI code what kind of PCI resource mappings we support */
75#define HAVE_PCI_MMAP 1
76#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
77#define arch_can_pci_mmap_io() 1
78#define arch_can_pci_mmap_wc() 1
79
80extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
81 size_t count);
82extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
83 size_t count);
84extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
85 struct vm_area_struct *vma,
86 enum pci_mmap_state mmap_state);
87
88#define HAVE_PCI_LEGACY 1
89
90extern void pcibios_claim_one_bus(struct pci_bus *b);
91
92extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
93
94extern void pcibios_resource_survey(void);
95
96extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
97extern int remove_phb_dynamic(struct pci_controller *phb);
98
99extern struct pci_dev *of_create_pci_dev(struct device_node *node,
100 struct pci_bus *bus, int devfn);
101
102extern unsigned int pci_parse_of_flags(u32 addr0, int bridge);
103
104extern void of_scan_pci_bridge(struct pci_dev *dev);
105
106extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
107extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
108
109struct file;
110extern pgprot_t pci_phys_mem_access_prot(struct file *file,
111 unsigned long pfn,
112 unsigned long size,
113 pgprot_t prot);
114
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]115extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]116extern void pcibios_setup_bus_self(struct pci_bus *bus);
117extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
118extern void pcibios_scan_phb(struct pci_controller *hose);
119
120#endif /* __KERNEL__ */
121
122extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev);
123extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]124extern int pnv_npu2_init(struct pci_controller *hose);
125extern int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid,
126 unsigned long msr);
127extern int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]128
129#endif /* __ASM_POWERPC_PCI_H */