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David Brazdil0f672f62019-12-10 10:32:29 +00001/* SPDX-License-Identifier: GPL-2.0-only */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00002/*
3 * Copyright (C) 2014 NVIDIA Corporation
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00004 */
5
6#ifndef __SOC_TEGRA_PM_H__
7#define __SOC_TEGRA_PM_H__
8
9enum tegra_suspend_mode {
10 TEGRA_SUSPEND_NONE = 0,
11 TEGRA_SUSPEND_LP2, /* CPU voltage off */
12 TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
13 TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
14 TEGRA_MAX_SUSPEND_MODE,
15};
16
17#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
18enum tegra_suspend_mode
19tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
20
21/* low-level resume entry point */
22void tegra_resume(void);
23#else
24static inline enum tegra_suspend_mode
25tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
26{
27 return TEGRA_SUSPEND_NONE;
28}
29
30static inline void tegra_resume(void)
31{
32}
33#endif /* CONFIG_PM_SLEEP */
34
35#endif /* __SOC_TEGRA_PM_H__ */