David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 3 | * MediaTek Pulse Width Modulator driver |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2015 John Crispin <blogic@openwrt.org> |
| 6 | * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> |
| 7 | * |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <linux/err.h> |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/ioport.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/of_device.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/pwm.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/types.h> |
| 22 | |
| 23 | /* PWM registers and bits definitions */ |
| 24 | #define PWMCON 0x00 |
| 25 | #define PWMHDUR 0x04 |
| 26 | #define PWMLDUR 0x08 |
| 27 | #define PWMGDUR 0x0c |
| 28 | #define PWMWAVENUM 0x28 |
| 29 | #define PWMDWIDTH 0x2c |
| 30 | #define PWM45DWIDTH_FIXUP 0x30 |
| 31 | #define PWMTHRES 0x30 |
| 32 | #define PWM45THRES_FIXUP 0x34 |
| 33 | |
| 34 | #define PWM_CLK_DIV_MAX 7 |
| 35 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 36 | struct pwm_mediatek_of_data { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 37 | unsigned int num_pwms; |
| 38 | bool pwm45_fixup; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | /** |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 42 | * struct pwm_mediatek_chip - struct representing PWM chip |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 43 | * @chip: linux PWM chip representation |
| 44 | * @regs: base address of PWM chip |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 45 | * @clk_top: the top clock generator |
| 46 | * @clk_main: the clock used by PWM core |
| 47 | * @clk_pwms: the clock used by each PWM channel |
| 48 | * @clk_freq: the fix clock frequency of legacy MIPS SoC |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 49 | */ |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 50 | struct pwm_mediatek_chip { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 51 | struct pwm_chip chip; |
| 52 | void __iomem *regs; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 53 | struct clk *clk_top; |
| 54 | struct clk *clk_main; |
| 55 | struct clk **clk_pwms; |
| 56 | const struct pwm_mediatek_of_data *soc; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 57 | }; |
| 58 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 59 | static const unsigned int pwm_mediatek_reg_offset[] = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 60 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 |
| 61 | }; |
| 62 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 63 | static inline struct pwm_mediatek_chip * |
| 64 | to_pwm_mediatek_chip(struct pwm_chip *chip) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 65 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 66 | return container_of(chip, struct pwm_mediatek_chip, chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 67 | } |
| 68 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 69 | static int pwm_mediatek_clk_enable(struct pwm_chip *chip, |
| 70 | struct pwm_device *pwm) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 71 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 72 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 73 | int ret; |
| 74 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 75 | ret = clk_prepare_enable(pc->clk_top); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 76 | if (ret < 0) |
| 77 | return ret; |
| 78 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 79 | ret = clk_prepare_enable(pc->clk_main); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 80 | if (ret < 0) |
| 81 | goto disable_clk_top; |
| 82 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 83 | ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 84 | if (ret < 0) |
| 85 | goto disable_clk_main; |
| 86 | |
| 87 | return 0; |
| 88 | |
| 89 | disable_clk_main: |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 90 | clk_disable_unprepare(pc->clk_main); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 91 | disable_clk_top: |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 92 | clk_disable_unprepare(pc->clk_top); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 93 | |
| 94 | return ret; |
| 95 | } |
| 96 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 97 | static void pwm_mediatek_clk_disable(struct pwm_chip *chip, |
| 98 | struct pwm_device *pwm) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 99 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 100 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 101 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 102 | clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); |
| 103 | clk_disable_unprepare(pc->clk_main); |
| 104 | clk_disable_unprepare(pc->clk_top); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 105 | } |
| 106 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 107 | static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, |
| 108 | unsigned int num, unsigned int offset) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 109 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 110 | return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 111 | } |
| 112 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 113 | static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, |
| 114 | unsigned int num, unsigned int offset, |
| 115 | u32 value) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 116 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 117 | writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 118 | } |
| 119 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 120 | static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 121 | int duty_ns, int period_ns) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 122 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 123 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 124 | u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, |
| 125 | reg_thres = PWMTHRES; |
| 126 | u64 resolution; |
| 127 | int ret; |
| 128 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 129 | ret = pwm_mediatek_clk_enable(chip, pwm); |
| 130 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 131 | if (ret < 0) |
| 132 | return ret; |
| 133 | |
| 134 | /* Using resolution in picosecond gets accuracy higher */ |
| 135 | resolution = (u64)NSEC_PER_SEC * 1000; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 136 | do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 137 | |
| 138 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); |
| 139 | while (cnt_period > 8191) { |
| 140 | resolution *= 2; |
| 141 | clkdiv++; |
| 142 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, |
| 143 | resolution); |
| 144 | } |
| 145 | |
| 146 | if (clkdiv > PWM_CLK_DIV_MAX) { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 147 | pwm_mediatek_clk_disable(chip, pwm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 148 | dev_err(chip->dev, "period %d not supported\n", period_ns); |
| 149 | return -EINVAL; |
| 150 | } |
| 151 | |
| 152 | if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { |
| 153 | /* |
| 154 | * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES |
| 155 | * from the other PWMs on MT7623. |
| 156 | */ |
| 157 | reg_width = PWM45DWIDTH_FIXUP; |
| 158 | reg_thres = PWM45THRES_FIXUP; |
| 159 | } |
| 160 | |
| 161 | cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 162 | pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); |
| 163 | pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); |
| 164 | pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 165 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 166 | pwm_mediatek_clk_disable(chip, pwm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 167 | |
| 168 | return 0; |
| 169 | } |
| 170 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 171 | static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 172 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 173 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 174 | u32 value; |
| 175 | int ret; |
| 176 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 177 | ret = pwm_mediatek_clk_enable(chip, pwm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 178 | if (ret < 0) |
| 179 | return ret; |
| 180 | |
| 181 | value = readl(pc->regs); |
| 182 | value |= BIT(pwm->hwpwm); |
| 183 | writel(value, pc->regs); |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 188 | static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 189 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 190 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 191 | u32 value; |
| 192 | |
| 193 | value = readl(pc->regs); |
| 194 | value &= ~BIT(pwm->hwpwm); |
| 195 | writel(value, pc->regs); |
| 196 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 197 | pwm_mediatek_clk_disable(chip, pwm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 198 | } |
| 199 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 200 | static const struct pwm_ops pwm_mediatek_ops = { |
| 201 | .config = pwm_mediatek_config, |
| 202 | .enable = pwm_mediatek_enable, |
| 203 | .disable = pwm_mediatek_disable, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 204 | .owner = THIS_MODULE, |
| 205 | }; |
| 206 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 207 | static int pwm_mediatek_probe(struct platform_device *pdev) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 208 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 209 | struct pwm_mediatek_chip *pc; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 210 | struct resource *res; |
| 211 | unsigned int i; |
| 212 | int ret; |
| 213 | |
| 214 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
| 215 | if (!pc) |
| 216 | return -ENOMEM; |
| 217 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 218 | pc->soc = of_device_get_match_data(&pdev->dev); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 219 | |
| 220 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 221 | pc->regs = devm_ioremap_resource(&pdev->dev, res); |
| 222 | if (IS_ERR(pc->regs)) |
| 223 | return PTR_ERR(pc->regs); |
| 224 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 225 | pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms, |
| 226 | sizeof(*pc->clk_pwms), GFP_KERNEL); |
| 227 | if (!pc->clk_pwms) |
| 228 | return -ENOMEM; |
| 229 | |
| 230 | pc->clk_top = devm_clk_get(&pdev->dev, "top"); |
| 231 | if (IS_ERR(pc->clk_top)) { |
| 232 | dev_err(&pdev->dev, "clock: top fail: %ld\n", |
| 233 | PTR_ERR(pc->clk_top)); |
| 234 | return PTR_ERR(pc->clk_top); |
| 235 | } |
| 236 | |
| 237 | pc->clk_main = devm_clk_get(&pdev->dev, "main"); |
| 238 | if (IS_ERR(pc->clk_main)) { |
| 239 | dev_err(&pdev->dev, "clock: main fail: %ld\n", |
| 240 | PTR_ERR(pc->clk_main)); |
| 241 | return PTR_ERR(pc->clk_main); |
| 242 | } |
| 243 | |
| 244 | for (i = 0; i < pc->soc->num_pwms; i++) { |
| 245 | char name[8]; |
| 246 | |
| 247 | snprintf(name, sizeof(name), "pwm%d", i + 1); |
| 248 | |
| 249 | pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); |
| 250 | if (IS_ERR(pc->clk_pwms[i])) { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 251 | dev_err(&pdev->dev, "clock: %s fail: %ld\n", |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 252 | name, PTR_ERR(pc->clk_pwms[i])); |
| 253 | return PTR_ERR(pc->clk_pwms[i]); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
| 257 | platform_set_drvdata(pdev, pc); |
| 258 | |
| 259 | pc->chip.dev = &pdev->dev; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 260 | pc->chip.ops = &pwm_mediatek_ops; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 261 | pc->chip.base = -1; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 262 | pc->chip.npwm = pc->soc->num_pwms; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 263 | |
| 264 | ret = pwmchip_add(&pc->chip); |
| 265 | if (ret < 0) { |
| 266 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
| 267 | return ret; |
| 268 | } |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 273 | static int pwm_mediatek_remove(struct platform_device *pdev) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 274 | { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 275 | struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 276 | |
| 277 | return pwmchip_remove(&pc->chip); |
| 278 | } |
| 279 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 280 | static const struct pwm_mediatek_of_data mt2712_pwm_data = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 281 | .num_pwms = 8, |
| 282 | .pwm45_fixup = false, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 283 | }; |
| 284 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 285 | static const struct pwm_mediatek_of_data mt7622_pwm_data = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 286 | .num_pwms = 6, |
| 287 | .pwm45_fixup = false, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 288 | }; |
| 289 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 290 | static const struct pwm_mediatek_of_data mt7623_pwm_data = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 291 | .num_pwms = 5, |
| 292 | .pwm45_fixup = true, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 293 | }; |
| 294 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 295 | static const struct pwm_mediatek_of_data mt7628_pwm_data = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 296 | .num_pwms = 4, |
| 297 | .pwm45_fixup = true, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 298 | }; |
| 299 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 300 | static const struct pwm_mediatek_of_data mt7629_pwm_data = { |
| 301 | .num_pwms = 1, |
| 302 | .pwm45_fixup = false, |
| 303 | }; |
| 304 | |
| 305 | static const struct pwm_mediatek_of_data mt8516_pwm_data = { |
| 306 | .num_pwms = 5, |
| 307 | .pwm45_fixup = false, |
| 308 | }; |
| 309 | |
| 310 | static const struct of_device_id pwm_mediatek_of_match[] = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 311 | { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, |
| 312 | { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, |
| 313 | { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, |
| 314 | { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 315 | { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, |
| 316 | { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 317 | { }, |
| 318 | }; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 319 | MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 320 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 321 | static struct platform_driver pwm_mediatek_driver = { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 322 | .driver = { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 323 | .name = "pwm-mediatek", |
| 324 | .of_match_table = pwm_mediatek_of_match, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 325 | }, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 326 | .probe = pwm_mediatek_probe, |
| 327 | .remove = pwm_mediatek_remove, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 328 | }; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 329 | module_platform_driver(pwm_mediatek_driver); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 330 | |
| 331 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 332 | MODULE_LICENSE("GPL v2"); |