David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Avionic Design GmbH |
| 4 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <linux/bitops.h> |
| 8 | #include <linux/host1x.h> |
| 9 | #include <linux/idr.h> |
| 10 | #include <linux/iommu.h> |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/platform_device.h> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 13 | |
| 14 | #include <drm/drm_atomic.h> |
| 15 | #include <drm/drm_atomic_helper.h> |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 16 | #include <drm/drm_debugfs.h> |
| 17 | #include <drm/drm_drv.h> |
| 18 | #include <drm/drm_fourcc.h> |
| 19 | #include <drm/drm_ioctl.h> |
| 20 | #include <drm/drm_prime.h> |
| 21 | #include <drm/drm_vblank.h> |
| 22 | |
| 23 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 24 | #include <asm/dma-iommu.h> |
| 25 | #endif |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 26 | |
| 27 | #include "drm.h" |
| 28 | #include "gem.h" |
| 29 | |
| 30 | #define DRIVER_NAME "tegra" |
| 31 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 32 | #define DRIVER_DATE "20120330" |
| 33 | #define DRIVER_MAJOR 0 |
| 34 | #define DRIVER_MINOR 0 |
| 35 | #define DRIVER_PATCHLEVEL 0 |
| 36 | |
| 37 | #define CARVEOUT_SZ SZ_64M |
| 38 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
| 39 | |
| 40 | struct tegra_drm_file { |
| 41 | struct idr contexts; |
| 42 | struct mutex lock; |
| 43 | }; |
| 44 | |
| 45 | static int tegra_atomic_check(struct drm_device *drm, |
| 46 | struct drm_atomic_state *state) |
| 47 | { |
| 48 | int err; |
| 49 | |
| 50 | err = drm_atomic_helper_check(drm, state); |
| 51 | if (err < 0) |
| 52 | return err; |
| 53 | |
| 54 | return tegra_display_hub_atomic_check(drm, state); |
| 55 | } |
| 56 | |
| 57 | static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { |
| 58 | .fb_create = tegra_fb_create, |
| 59 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 60 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
| 61 | #endif |
| 62 | .atomic_check = tegra_atomic_check, |
| 63 | .atomic_commit = drm_atomic_helper_commit, |
| 64 | }; |
| 65 | |
| 66 | static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) |
| 67 | { |
| 68 | struct drm_device *drm = old_state->dev; |
| 69 | struct tegra_drm *tegra = drm->dev_private; |
| 70 | |
| 71 | if (tegra->hub) { |
| 72 | drm_atomic_helper_commit_modeset_disables(drm, old_state); |
| 73 | tegra_display_hub_atomic_commit(drm, old_state); |
| 74 | drm_atomic_helper_commit_planes(drm, old_state, 0); |
| 75 | drm_atomic_helper_commit_modeset_enables(drm, old_state); |
| 76 | drm_atomic_helper_commit_hw_done(old_state); |
| 77 | drm_atomic_helper_wait_for_vblanks(drm, old_state); |
| 78 | drm_atomic_helper_cleanup_planes(drm, old_state); |
| 79 | } else { |
| 80 | drm_atomic_helper_commit_tail_rpm(old_state); |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | static const struct drm_mode_config_helper_funcs |
| 85 | tegra_drm_mode_config_helpers = { |
| 86 | .atomic_commit_tail = tegra_atomic_commit_tail, |
| 87 | }; |
| 88 | |
| 89 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
| 90 | { |
| 91 | struct host1x_device *device = to_host1x_device(drm->dev); |
| 92 | struct tegra_drm *tegra; |
| 93 | int err; |
| 94 | |
| 95 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
| 96 | if (!tegra) |
| 97 | return -ENOMEM; |
| 98 | |
| 99 | if (iommu_present(&platform_bus_type)) { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 100 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
| 101 | if (!tegra->domain) { |
| 102 | err = -ENOMEM; |
| 103 | goto free; |
| 104 | } |
| 105 | |
| 106 | err = iova_cache_get(); |
| 107 | if (err < 0) |
| 108 | goto domain; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | mutex_init(&tegra->clients_lock); |
| 112 | INIT_LIST_HEAD(&tegra->clients); |
| 113 | |
| 114 | drm->dev_private = tegra; |
| 115 | tegra->drm = drm; |
| 116 | |
| 117 | drm_mode_config_init(drm); |
| 118 | |
| 119 | drm->mode_config.min_width = 0; |
| 120 | drm->mode_config.min_height = 0; |
| 121 | |
| 122 | drm->mode_config.max_width = 4096; |
| 123 | drm->mode_config.max_height = 4096; |
| 124 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 125 | drm->mode_config.normalize_zpos = true; |
| 126 | |
| 127 | drm->mode_config.funcs = &tegra_drm_mode_config_funcs; |
| 128 | drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; |
| 129 | |
| 130 | err = tegra_drm_fb_prepare(drm); |
| 131 | if (err < 0) |
| 132 | goto config; |
| 133 | |
| 134 | drm_kms_helper_poll_init(drm); |
| 135 | |
| 136 | err = host1x_device_init(device); |
| 137 | if (err < 0) |
| 138 | goto fbdev; |
| 139 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 140 | if (tegra->domain) { |
| 141 | u64 carveout_start, carveout_end, gem_start, gem_end; |
| 142 | u64 dma_mask = dma_get_mask(&device->dev); |
| 143 | dma_addr_t start, end; |
| 144 | unsigned long order; |
| 145 | |
| 146 | start = tegra->domain->geometry.aperture_start & dma_mask; |
| 147 | end = tegra->domain->geometry.aperture_end & dma_mask; |
| 148 | |
| 149 | gem_start = start; |
| 150 | gem_end = end - CARVEOUT_SZ; |
| 151 | carveout_start = gem_end + 1; |
| 152 | carveout_end = end; |
| 153 | |
| 154 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 155 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
| 156 | carveout_start >> order); |
| 157 | |
| 158 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 159 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 160 | |
| 161 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
| 162 | mutex_init(&tegra->mm_lock); |
| 163 | |
| 164 | DRM_DEBUG("IOMMU apertures:\n"); |
| 165 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 166 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, |
| 167 | carveout_end); |
| 168 | } |
| 169 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 170 | if (tegra->hub) { |
| 171 | err = tegra_display_hub_prepare(tegra->hub); |
| 172 | if (err < 0) |
| 173 | goto device; |
| 174 | } |
| 175 | |
| 176 | /* |
| 177 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 178 | * core, so we need to set this manually in order to allow the |
| 179 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 180 | */ |
| 181 | drm->irq_enabled = true; |
| 182 | |
| 183 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
| 184 | drm->max_vblank_count = 0xffffffff; |
| 185 | |
| 186 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 187 | if (err < 0) |
| 188 | goto hub; |
| 189 | |
| 190 | drm_mode_config_reset(drm); |
| 191 | |
| 192 | err = tegra_drm_fb_init(drm); |
| 193 | if (err < 0) |
| 194 | goto hub; |
| 195 | |
| 196 | return 0; |
| 197 | |
| 198 | hub: |
| 199 | if (tegra->hub) |
| 200 | tegra_display_hub_cleanup(tegra->hub); |
| 201 | device: |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 202 | if (tegra->domain) { |
| 203 | mutex_destroy(&tegra->mm_lock); |
| 204 | drm_mm_takedown(&tegra->mm); |
| 205 | put_iova_domain(&tegra->carveout.domain); |
| 206 | iova_cache_put(); |
| 207 | } |
Olivier Deprez | 0e64123 | 2021-09-23 10:07:05 +0200 | [diff] [blame^] | 208 | |
| 209 | host1x_device_exit(device); |
| 210 | fbdev: |
| 211 | drm_kms_helper_poll_fini(drm); |
| 212 | tegra_drm_fb_free(drm); |
| 213 | config: |
| 214 | drm_mode_config_cleanup(drm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 215 | domain: |
| 216 | if (tegra->domain) |
| 217 | iommu_domain_free(tegra->domain); |
| 218 | free: |
| 219 | kfree(tegra); |
| 220 | return err; |
| 221 | } |
| 222 | |
| 223 | static void tegra_drm_unload(struct drm_device *drm) |
| 224 | { |
| 225 | struct host1x_device *device = to_host1x_device(drm->dev); |
| 226 | struct tegra_drm *tegra = drm->dev_private; |
| 227 | int err; |
| 228 | |
| 229 | drm_kms_helper_poll_fini(drm); |
| 230 | tegra_drm_fb_exit(drm); |
| 231 | drm_atomic_helper_shutdown(drm); |
| 232 | drm_mode_config_cleanup(drm); |
| 233 | |
| 234 | err = host1x_device_exit(device); |
| 235 | if (err < 0) |
| 236 | return; |
| 237 | |
| 238 | if (tegra->domain) { |
| 239 | mutex_destroy(&tegra->mm_lock); |
| 240 | drm_mm_takedown(&tegra->mm); |
| 241 | put_iova_domain(&tegra->carveout.domain); |
| 242 | iova_cache_put(); |
| 243 | iommu_domain_free(tegra->domain); |
| 244 | } |
| 245 | |
| 246 | kfree(tegra); |
| 247 | } |
| 248 | |
| 249 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 250 | { |
| 251 | struct tegra_drm_file *fpriv; |
| 252 | |
| 253 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 254 | if (!fpriv) |
| 255 | return -ENOMEM; |
| 256 | |
Olivier Deprez | 0e64123 | 2021-09-23 10:07:05 +0200 | [diff] [blame^] | 257 | idr_init_base(&fpriv->contexts, 1); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 258 | mutex_init(&fpriv->lock); |
| 259 | filp->driver_priv = fpriv; |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
| 265 | { |
| 266 | context->client->ops->close_channel(context); |
| 267 | kfree(context); |
| 268 | } |
| 269 | |
| 270 | static struct host1x_bo * |
| 271 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
| 272 | { |
| 273 | struct drm_gem_object *gem; |
| 274 | struct tegra_bo *bo; |
| 275 | |
| 276 | gem = drm_gem_object_lookup(file, handle); |
| 277 | if (!gem) |
| 278 | return NULL; |
| 279 | |
| 280 | bo = to_tegra_bo(gem); |
| 281 | return &bo->base; |
| 282 | } |
| 283 | |
| 284 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 285 | struct drm_tegra_reloc __user *src, |
| 286 | struct drm_device *drm, |
| 287 | struct drm_file *file) |
| 288 | { |
| 289 | u32 cmdbuf, target; |
| 290 | int err; |
| 291 | |
| 292 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 293 | if (err < 0) |
| 294 | return err; |
| 295 | |
| 296 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 297 | if (err < 0) |
| 298 | return err; |
| 299 | |
| 300 | err = get_user(target, &src->target.handle); |
| 301 | if (err < 0) |
| 302 | return err; |
| 303 | |
| 304 | err = get_user(dest->target.offset, &src->target.offset); |
| 305 | if (err < 0) |
| 306 | return err; |
| 307 | |
| 308 | err = get_user(dest->shift, &src->shift); |
| 309 | if (err < 0) |
| 310 | return err; |
| 311 | |
| 312 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
| 313 | if (!dest->cmdbuf.bo) |
| 314 | return -ENOENT; |
| 315 | |
| 316 | dest->target.bo = host1x_bo_lookup(file, target); |
| 317 | if (!dest->target.bo) |
| 318 | return -ENOENT; |
| 319 | |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 324 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 325 | struct drm_file *file) |
| 326 | { |
| 327 | struct host1x_client *client = &context->client->base; |
| 328 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 329 | unsigned int num_relocs = args->num_relocs; |
| 330 | struct drm_tegra_cmdbuf __user *user_cmdbufs; |
| 331 | struct drm_tegra_reloc __user *user_relocs; |
| 332 | struct drm_tegra_syncpt __user *user_syncpt; |
| 333 | struct drm_tegra_syncpt syncpt; |
| 334 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
| 335 | struct drm_gem_object **refs; |
| 336 | struct host1x_syncpt *sp; |
| 337 | struct host1x_job *job; |
| 338 | unsigned int num_refs; |
| 339 | int err; |
| 340 | |
| 341 | user_cmdbufs = u64_to_user_ptr(args->cmdbufs); |
| 342 | user_relocs = u64_to_user_ptr(args->relocs); |
| 343 | user_syncpt = u64_to_user_ptr(args->syncpts); |
| 344 | |
| 345 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 346 | if (args->num_syncpts != 1) |
| 347 | return -EINVAL; |
| 348 | |
| 349 | /* We don't yet support waitchks */ |
| 350 | if (args->num_waitchks != 0) |
| 351 | return -EINVAL; |
| 352 | |
| 353 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
| 354 | args->num_relocs); |
| 355 | if (!job) |
| 356 | return -ENOMEM; |
| 357 | |
| 358 | job->num_relocs = args->num_relocs; |
| 359 | job->client = client; |
| 360 | job->class = client->class; |
| 361 | job->serialize = true; |
| 362 | |
| 363 | /* |
| 364 | * Track referenced BOs so that they can be unreferenced after the |
| 365 | * submission is complete. |
| 366 | */ |
| 367 | num_refs = num_cmdbufs + num_relocs * 2; |
| 368 | |
| 369 | refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); |
| 370 | if (!refs) { |
| 371 | err = -ENOMEM; |
| 372 | goto put; |
| 373 | } |
| 374 | |
| 375 | /* reuse as an iterator later */ |
| 376 | num_refs = 0; |
| 377 | |
| 378 | while (num_cmdbufs) { |
| 379 | struct drm_tegra_cmdbuf cmdbuf; |
| 380 | struct host1x_bo *bo; |
| 381 | struct tegra_bo *obj; |
| 382 | u64 offset; |
| 383 | |
| 384 | if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) { |
| 385 | err = -EFAULT; |
| 386 | goto fail; |
| 387 | } |
| 388 | |
| 389 | /* |
| 390 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 391 | * value means the words count is malformed. |
| 392 | */ |
| 393 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 394 | err = -EINVAL; |
| 395 | goto fail; |
| 396 | } |
| 397 | |
| 398 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
| 399 | if (!bo) { |
| 400 | err = -ENOENT; |
| 401 | goto fail; |
| 402 | } |
| 403 | |
| 404 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 405 | obj = host1x_to_tegra_bo(bo); |
| 406 | refs[num_refs++] = &obj->gem; |
| 407 | |
| 408 | /* |
| 409 | * Gather buffer base address must be 4-bytes aligned, |
| 410 | * unaligned offset is malformed and cause commands stream |
| 411 | * corruption on the buffer address relocation. |
| 412 | */ |
| 413 | if (offset & 3 || offset > obj->gem.size) { |
| 414 | err = -EINVAL; |
| 415 | goto fail; |
| 416 | } |
| 417 | |
| 418 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 419 | num_cmdbufs--; |
| 420 | user_cmdbufs++; |
| 421 | } |
| 422 | |
| 423 | /* copy and resolve relocations from submit */ |
| 424 | while (num_relocs--) { |
| 425 | struct host1x_reloc *reloc; |
| 426 | struct tegra_bo *obj; |
| 427 | |
| 428 | err = host1x_reloc_copy_from_user(&job->relocs[num_relocs], |
| 429 | &user_relocs[num_relocs], drm, |
| 430 | file); |
| 431 | if (err < 0) |
| 432 | goto fail; |
| 433 | |
| 434 | reloc = &job->relocs[num_relocs]; |
| 435 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
| 436 | refs[num_refs++] = &obj->gem; |
| 437 | |
| 438 | /* |
| 439 | * The unaligned cmdbuf offset will cause an unaligned write |
| 440 | * during of the relocations patching, corrupting the commands |
| 441 | * stream. |
| 442 | */ |
| 443 | if (reloc->cmdbuf.offset & 3 || |
| 444 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 445 | err = -EINVAL; |
| 446 | goto fail; |
| 447 | } |
| 448 | |
| 449 | obj = host1x_to_tegra_bo(reloc->target.bo); |
| 450 | refs[num_refs++] = &obj->gem; |
| 451 | |
| 452 | if (reloc->target.offset >= obj->gem.size) { |
| 453 | err = -EINVAL; |
| 454 | goto fail; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) { |
| 459 | err = -EFAULT; |
| 460 | goto fail; |
| 461 | } |
| 462 | |
| 463 | /* check whether syncpoint ID is valid */ |
| 464 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 465 | if (!sp) { |
| 466 | err = -ENOENT; |
| 467 | goto fail; |
| 468 | } |
| 469 | |
| 470 | job->is_addr_reg = context->client->ops->is_addr_reg; |
| 471 | job->is_valid_class = context->client->ops->is_valid_class; |
| 472 | job->syncpt_incrs = syncpt.incrs; |
| 473 | job->syncpt_id = syncpt.id; |
| 474 | job->timeout = 10000; |
| 475 | |
| 476 | if (args->timeout && args->timeout < 10000) |
| 477 | job->timeout = args->timeout; |
| 478 | |
| 479 | err = host1x_job_pin(job, context->client->base.dev); |
| 480 | if (err) |
| 481 | goto fail; |
| 482 | |
| 483 | err = host1x_job_submit(job); |
| 484 | if (err) { |
| 485 | host1x_job_unpin(job); |
| 486 | goto fail; |
| 487 | } |
| 488 | |
| 489 | args->fence = job->syncpt_end; |
| 490 | |
| 491 | fail: |
| 492 | while (num_refs--) |
| 493 | drm_gem_object_put_unlocked(refs[num_refs]); |
| 494 | |
| 495 | kfree(refs); |
| 496 | |
| 497 | put: |
| 498 | host1x_job_put(job); |
| 499 | return err; |
| 500 | } |
| 501 | |
| 502 | |
| 503 | #ifdef CONFIG_DRM_TEGRA_STAGING |
| 504 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 505 | struct drm_file *file) |
| 506 | { |
| 507 | struct drm_tegra_gem_create *args = data; |
| 508 | struct tegra_bo *bo; |
| 509 | |
| 510 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
| 511 | &args->handle); |
| 512 | if (IS_ERR(bo)) |
| 513 | return PTR_ERR(bo); |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 519 | struct drm_file *file) |
| 520 | { |
| 521 | struct drm_tegra_gem_mmap *args = data; |
| 522 | struct drm_gem_object *gem; |
| 523 | struct tegra_bo *bo; |
| 524 | |
| 525 | gem = drm_gem_object_lookup(file, args->handle); |
| 526 | if (!gem) |
| 527 | return -EINVAL; |
| 528 | |
| 529 | bo = to_tegra_bo(gem); |
| 530 | |
| 531 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
| 532 | |
| 533 | drm_gem_object_put_unlocked(gem); |
| 534 | |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 539 | struct drm_file *file) |
| 540 | { |
| 541 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
| 542 | struct drm_tegra_syncpt_read *args = data; |
| 543 | struct host1x_syncpt *sp; |
| 544 | |
| 545 | sp = host1x_syncpt_get(host, args->id); |
| 546 | if (!sp) |
| 547 | return -EINVAL; |
| 548 | |
| 549 | args->value = host1x_syncpt_read_min(sp); |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 554 | struct drm_file *file) |
| 555 | { |
| 556 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
| 557 | struct drm_tegra_syncpt_incr *args = data; |
| 558 | struct host1x_syncpt *sp; |
| 559 | |
| 560 | sp = host1x_syncpt_get(host1x, args->id); |
| 561 | if (!sp) |
| 562 | return -EINVAL; |
| 563 | |
| 564 | return host1x_syncpt_incr(sp); |
| 565 | } |
| 566 | |
| 567 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 568 | struct drm_file *file) |
| 569 | { |
| 570 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
| 571 | struct drm_tegra_syncpt_wait *args = data; |
| 572 | struct host1x_syncpt *sp; |
| 573 | |
| 574 | sp = host1x_syncpt_get(host1x, args->id); |
| 575 | if (!sp) |
| 576 | return -EINVAL; |
| 577 | |
| 578 | return host1x_syncpt_wait(sp, args->thresh, |
| 579 | msecs_to_jiffies(args->timeout), |
| 580 | &args->value); |
| 581 | } |
| 582 | |
| 583 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 584 | struct tegra_drm_client *client, |
| 585 | struct tegra_drm_context *context) |
| 586 | { |
| 587 | int err; |
| 588 | |
| 589 | err = client->ops->open_channel(client, context); |
| 590 | if (err < 0) |
| 591 | return err; |
| 592 | |
| 593 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
| 594 | if (err < 0) { |
| 595 | client->ops->close_channel(context); |
| 596 | return err; |
| 597 | } |
| 598 | |
| 599 | context->client = client; |
| 600 | context->id = err; |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 606 | struct drm_file *file) |
| 607 | { |
| 608 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 609 | struct tegra_drm *tegra = drm->dev_private; |
| 610 | struct drm_tegra_open_channel *args = data; |
| 611 | struct tegra_drm_context *context; |
| 612 | struct tegra_drm_client *client; |
| 613 | int err = -ENODEV; |
| 614 | |
| 615 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 616 | if (!context) |
| 617 | return -ENOMEM; |
| 618 | |
| 619 | mutex_lock(&fpriv->lock); |
| 620 | |
| 621 | list_for_each_entry(client, &tegra->clients, list) |
| 622 | if (client->base.class == args->client) { |
| 623 | err = tegra_client_open(fpriv, client, context); |
| 624 | if (err < 0) |
| 625 | break; |
| 626 | |
| 627 | args->context = context->id; |
| 628 | break; |
| 629 | } |
| 630 | |
| 631 | if (err < 0) |
| 632 | kfree(context); |
| 633 | |
| 634 | mutex_unlock(&fpriv->lock); |
| 635 | return err; |
| 636 | } |
| 637 | |
| 638 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 639 | struct drm_file *file) |
| 640 | { |
| 641 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 642 | struct drm_tegra_close_channel *args = data; |
| 643 | struct tegra_drm_context *context; |
| 644 | int err = 0; |
| 645 | |
| 646 | mutex_lock(&fpriv->lock); |
| 647 | |
| 648 | context = idr_find(&fpriv->contexts, args->context); |
| 649 | if (!context) { |
| 650 | err = -EINVAL; |
| 651 | goto unlock; |
| 652 | } |
| 653 | |
| 654 | idr_remove(&fpriv->contexts, context->id); |
| 655 | tegra_drm_context_free(context); |
| 656 | |
| 657 | unlock: |
| 658 | mutex_unlock(&fpriv->lock); |
| 659 | return err; |
| 660 | } |
| 661 | |
| 662 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 663 | struct drm_file *file) |
| 664 | { |
| 665 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 666 | struct drm_tegra_get_syncpt *args = data; |
| 667 | struct tegra_drm_context *context; |
| 668 | struct host1x_syncpt *syncpt; |
| 669 | int err = 0; |
| 670 | |
| 671 | mutex_lock(&fpriv->lock); |
| 672 | |
| 673 | context = idr_find(&fpriv->contexts, args->context); |
| 674 | if (!context) { |
| 675 | err = -ENODEV; |
| 676 | goto unlock; |
| 677 | } |
| 678 | |
| 679 | if (args->index >= context->client->base.num_syncpts) { |
| 680 | err = -EINVAL; |
| 681 | goto unlock; |
| 682 | } |
| 683 | |
| 684 | syncpt = context->client->base.syncpts[args->index]; |
| 685 | args->id = host1x_syncpt_id(syncpt); |
| 686 | |
| 687 | unlock: |
| 688 | mutex_unlock(&fpriv->lock); |
| 689 | return err; |
| 690 | } |
| 691 | |
| 692 | static int tegra_submit(struct drm_device *drm, void *data, |
| 693 | struct drm_file *file) |
| 694 | { |
| 695 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 696 | struct drm_tegra_submit *args = data; |
| 697 | struct tegra_drm_context *context; |
| 698 | int err; |
| 699 | |
| 700 | mutex_lock(&fpriv->lock); |
| 701 | |
| 702 | context = idr_find(&fpriv->contexts, args->context); |
| 703 | if (!context) { |
| 704 | err = -ENODEV; |
| 705 | goto unlock; |
| 706 | } |
| 707 | |
| 708 | err = context->client->ops->submit(context, args, drm, file); |
| 709 | |
| 710 | unlock: |
| 711 | mutex_unlock(&fpriv->lock); |
| 712 | return err; |
| 713 | } |
| 714 | |
| 715 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 716 | struct drm_file *file) |
| 717 | { |
| 718 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 719 | struct drm_tegra_get_syncpt_base *args = data; |
| 720 | struct tegra_drm_context *context; |
| 721 | struct host1x_syncpt_base *base; |
| 722 | struct host1x_syncpt *syncpt; |
| 723 | int err = 0; |
| 724 | |
| 725 | mutex_lock(&fpriv->lock); |
| 726 | |
| 727 | context = idr_find(&fpriv->contexts, args->context); |
| 728 | if (!context) { |
| 729 | err = -ENODEV; |
| 730 | goto unlock; |
| 731 | } |
| 732 | |
| 733 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 734 | err = -EINVAL; |
| 735 | goto unlock; |
| 736 | } |
| 737 | |
| 738 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 739 | |
| 740 | base = host1x_syncpt_get_base(syncpt); |
| 741 | if (!base) { |
| 742 | err = -ENXIO; |
| 743 | goto unlock; |
| 744 | } |
| 745 | |
| 746 | args->id = host1x_syncpt_base_id(base); |
| 747 | |
| 748 | unlock: |
| 749 | mutex_unlock(&fpriv->lock); |
| 750 | return err; |
| 751 | } |
| 752 | |
| 753 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 754 | struct drm_file *file) |
| 755 | { |
| 756 | struct drm_tegra_gem_set_tiling *args = data; |
| 757 | enum tegra_bo_tiling_mode mode; |
| 758 | struct drm_gem_object *gem; |
| 759 | unsigned long value = 0; |
| 760 | struct tegra_bo *bo; |
| 761 | |
| 762 | switch (args->mode) { |
| 763 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 764 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 765 | |
| 766 | if (args->value != 0) |
| 767 | return -EINVAL; |
| 768 | |
| 769 | break; |
| 770 | |
| 771 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 772 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 773 | |
| 774 | if (args->value != 0) |
| 775 | return -EINVAL; |
| 776 | |
| 777 | break; |
| 778 | |
| 779 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 780 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 781 | |
| 782 | if (args->value > 5) |
| 783 | return -EINVAL; |
| 784 | |
| 785 | value = args->value; |
| 786 | break; |
| 787 | |
| 788 | default: |
| 789 | return -EINVAL; |
| 790 | } |
| 791 | |
| 792 | gem = drm_gem_object_lookup(file, args->handle); |
| 793 | if (!gem) |
| 794 | return -ENOENT; |
| 795 | |
| 796 | bo = to_tegra_bo(gem); |
| 797 | |
| 798 | bo->tiling.mode = mode; |
| 799 | bo->tiling.value = value; |
| 800 | |
| 801 | drm_gem_object_put_unlocked(gem); |
| 802 | |
| 803 | return 0; |
| 804 | } |
| 805 | |
| 806 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 807 | struct drm_file *file) |
| 808 | { |
| 809 | struct drm_tegra_gem_get_tiling *args = data; |
| 810 | struct drm_gem_object *gem; |
| 811 | struct tegra_bo *bo; |
| 812 | int err = 0; |
| 813 | |
| 814 | gem = drm_gem_object_lookup(file, args->handle); |
| 815 | if (!gem) |
| 816 | return -ENOENT; |
| 817 | |
| 818 | bo = to_tegra_bo(gem); |
| 819 | |
| 820 | switch (bo->tiling.mode) { |
| 821 | case TEGRA_BO_TILING_MODE_PITCH: |
| 822 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 823 | args->value = 0; |
| 824 | break; |
| 825 | |
| 826 | case TEGRA_BO_TILING_MODE_TILED: |
| 827 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 828 | args->value = 0; |
| 829 | break; |
| 830 | |
| 831 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 832 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 833 | args->value = bo->tiling.value; |
| 834 | break; |
| 835 | |
| 836 | default: |
| 837 | err = -EINVAL; |
| 838 | break; |
| 839 | } |
| 840 | |
| 841 | drm_gem_object_put_unlocked(gem); |
| 842 | |
| 843 | return err; |
| 844 | } |
| 845 | |
| 846 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 847 | struct drm_file *file) |
| 848 | { |
| 849 | struct drm_tegra_gem_set_flags *args = data; |
| 850 | struct drm_gem_object *gem; |
| 851 | struct tegra_bo *bo; |
| 852 | |
| 853 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 854 | return -EINVAL; |
| 855 | |
| 856 | gem = drm_gem_object_lookup(file, args->handle); |
| 857 | if (!gem) |
| 858 | return -ENOENT; |
| 859 | |
| 860 | bo = to_tegra_bo(gem); |
| 861 | bo->flags = 0; |
| 862 | |
| 863 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 864 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 865 | |
| 866 | drm_gem_object_put_unlocked(gem); |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 872 | struct drm_file *file) |
| 873 | { |
| 874 | struct drm_tegra_gem_get_flags *args = data; |
| 875 | struct drm_gem_object *gem; |
| 876 | struct tegra_bo *bo; |
| 877 | |
| 878 | gem = drm_gem_object_lookup(file, args->handle); |
| 879 | if (!gem) |
| 880 | return -ENOENT; |
| 881 | |
| 882 | bo = to_tegra_bo(gem); |
| 883 | args->flags = 0; |
| 884 | |
| 885 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 886 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 887 | |
| 888 | drm_gem_object_put_unlocked(gem); |
| 889 | |
| 890 | return 0; |
| 891 | } |
| 892 | #endif |
| 893 | |
| 894 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
| 895 | #ifdef CONFIG_DRM_TEGRA_STAGING |
| 896 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 897 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 898 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 899 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 900 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 901 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 902 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 903 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 904 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 905 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 906 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 907 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 908 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 909 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 910 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 911 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 912 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 913 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 914 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 915 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 916 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 917 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 918 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 919 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 920 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 921 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 922 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 923 | DRM_RENDER_ALLOW), |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 924 | #endif |
| 925 | }; |
| 926 | |
| 927 | static const struct file_operations tegra_drm_fops = { |
| 928 | .owner = THIS_MODULE, |
| 929 | .open = drm_open, |
| 930 | .release = drm_release, |
| 931 | .unlocked_ioctl = drm_ioctl, |
| 932 | .mmap = tegra_drm_mmap, |
| 933 | .poll = drm_poll, |
| 934 | .read = drm_read, |
| 935 | .compat_ioctl = drm_compat_ioctl, |
| 936 | .llseek = noop_llseek, |
| 937 | }; |
| 938 | |
| 939 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 940 | { |
| 941 | struct tegra_drm_context *context = p; |
| 942 | |
| 943 | tegra_drm_context_free(context); |
| 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
| 948 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
| 949 | { |
| 950 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 951 | |
| 952 | mutex_lock(&fpriv->lock); |
| 953 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 954 | mutex_unlock(&fpriv->lock); |
| 955 | |
| 956 | idr_destroy(&fpriv->contexts); |
| 957 | mutex_destroy(&fpriv->lock); |
| 958 | kfree(fpriv); |
| 959 | } |
| 960 | |
| 961 | #ifdef CONFIG_DEBUG_FS |
| 962 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 963 | { |
| 964 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 965 | struct drm_device *drm = node->minor->dev; |
| 966 | struct drm_framebuffer *fb; |
| 967 | |
| 968 | mutex_lock(&drm->mode_config.fb_lock); |
| 969 | |
| 970 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 971 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
| 972 | fb->base.id, fb->width, fb->height, |
| 973 | fb->format->depth, |
| 974 | fb->format->cpp[0] * 8, |
| 975 | drm_framebuffer_read_refcount(fb)); |
| 976 | } |
| 977 | |
| 978 | mutex_unlock(&drm->mode_config.fb_lock); |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 984 | { |
| 985 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 986 | struct drm_device *drm = node->minor->dev; |
| 987 | struct tegra_drm *tegra = drm->dev_private; |
| 988 | struct drm_printer p = drm_seq_file_printer(s); |
| 989 | |
| 990 | if (tegra->domain) { |
| 991 | mutex_lock(&tegra->mm_lock); |
| 992 | drm_mm_print(&tegra->mm, &p); |
| 993 | mutex_unlock(&tegra->mm_lock); |
| 994 | } |
| 995 | |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | static struct drm_info_list tegra_debugfs_list[] = { |
| 1000 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
| 1001 | { "iova", tegra_debugfs_iova, 0 }, |
| 1002 | }; |
| 1003 | |
| 1004 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1005 | { |
| 1006 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1007 | ARRAY_SIZE(tegra_debugfs_list), |
| 1008 | minor->debugfs_root, minor); |
| 1009 | } |
| 1010 | #endif |
| 1011 | |
| 1012 | static struct drm_driver tegra_drm_driver = { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1013 | .driver_features = DRIVER_MODESET | DRIVER_GEM | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1014 | DRIVER_ATOMIC | DRIVER_RENDER, |
| 1015 | .load = tegra_drm_load, |
| 1016 | .unload = tegra_drm_unload, |
| 1017 | .open = tegra_drm_open, |
| 1018 | .postclose = tegra_drm_postclose, |
| 1019 | .lastclose = drm_fb_helper_lastclose, |
| 1020 | |
| 1021 | #if defined(CONFIG_DEBUG_FS) |
| 1022 | .debugfs_init = tegra_debugfs_init, |
| 1023 | #endif |
| 1024 | |
| 1025 | .gem_free_object_unlocked = tegra_bo_free_object, |
| 1026 | .gem_vm_ops = &tegra_bo_vm_ops, |
| 1027 | |
| 1028 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1029 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1030 | .gem_prime_export = tegra_gem_prime_export, |
| 1031 | .gem_prime_import = tegra_gem_prime_import, |
| 1032 | |
| 1033 | .dumb_create = tegra_bo_dumb_create, |
| 1034 | |
| 1035 | .ioctls = tegra_drm_ioctls, |
| 1036 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1037 | .fops = &tegra_drm_fops, |
| 1038 | |
| 1039 | .name = DRIVER_NAME, |
| 1040 | .desc = DRIVER_DESC, |
| 1041 | .date = DRIVER_DATE, |
| 1042 | .major = DRIVER_MAJOR, |
| 1043 | .minor = DRIVER_MINOR, |
| 1044 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1045 | }; |
| 1046 | |
| 1047 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1048 | struct tegra_drm_client *client) |
| 1049 | { |
| 1050 | mutex_lock(&tegra->clients_lock); |
| 1051 | list_add_tail(&client->list, &tegra->clients); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1052 | client->drm = tegra; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1053 | mutex_unlock(&tegra->clients_lock); |
| 1054 | |
| 1055 | return 0; |
| 1056 | } |
| 1057 | |
| 1058 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1059 | struct tegra_drm_client *client) |
| 1060 | { |
| 1061 | mutex_lock(&tegra->clients_lock); |
| 1062 | list_del_init(&client->list); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1063 | client->drm = NULL; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1064 | mutex_unlock(&tegra->clients_lock); |
| 1065 | |
| 1066 | return 0; |
| 1067 | } |
| 1068 | |
| 1069 | struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client, |
| 1070 | bool shared) |
| 1071 | { |
| 1072 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1073 | struct tegra_drm *tegra = drm->dev_private; |
| 1074 | struct iommu_group *group = NULL; |
| 1075 | int err; |
| 1076 | |
| 1077 | if (tegra->domain) { |
| 1078 | group = iommu_group_get(client->dev); |
| 1079 | if (!group) { |
| 1080 | dev_err(client->dev, "failed to get IOMMU group\n"); |
| 1081 | return ERR_PTR(-ENODEV); |
| 1082 | } |
| 1083 | |
| 1084 | if (!shared || (shared && (group != tegra->group))) { |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1085 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 1086 | if (client->dev->archdata.mapping) { |
| 1087 | struct dma_iommu_mapping *mapping = |
| 1088 | to_dma_iommu_mapping(client->dev); |
| 1089 | arm_iommu_detach_device(client->dev); |
| 1090 | arm_iommu_release_mapping(mapping); |
| 1091 | } |
| 1092 | #endif |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1093 | err = iommu_attach_group(tegra->domain, group); |
| 1094 | if (err < 0) { |
| 1095 | iommu_group_put(group); |
| 1096 | return ERR_PTR(err); |
| 1097 | } |
| 1098 | |
| 1099 | if (shared && !tegra->group) |
| 1100 | tegra->group = group; |
| 1101 | } |
| 1102 | } |
| 1103 | |
| 1104 | return group; |
| 1105 | } |
| 1106 | |
| 1107 | void host1x_client_iommu_detach(struct host1x_client *client, |
| 1108 | struct iommu_group *group) |
| 1109 | { |
| 1110 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1111 | struct tegra_drm *tegra = drm->dev_private; |
| 1112 | |
| 1113 | if (group) { |
| 1114 | if (group == tegra->group) { |
| 1115 | iommu_detach_group(tegra->domain, group); |
| 1116 | tegra->group = NULL; |
| 1117 | } |
| 1118 | |
| 1119 | iommu_group_put(group); |
| 1120 | } |
| 1121 | } |
| 1122 | |
| 1123 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) |
| 1124 | { |
| 1125 | struct iova *alloc; |
| 1126 | void *virt; |
| 1127 | gfp_t gfp; |
| 1128 | int err; |
| 1129 | |
| 1130 | if (tegra->domain) |
| 1131 | size = iova_align(&tegra->carveout.domain, size); |
| 1132 | else |
| 1133 | size = PAGE_ALIGN(size); |
| 1134 | |
| 1135 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1136 | if (!tegra->domain) { |
| 1137 | /* |
| 1138 | * Many units only support 32-bit addresses, even on 64-bit |
| 1139 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1140 | * virtual address space, force allocations to be in the |
| 1141 | * lower 32-bit range. |
| 1142 | */ |
| 1143 | gfp |= GFP_DMA; |
| 1144 | } |
| 1145 | |
| 1146 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1147 | if (!virt) |
| 1148 | return ERR_PTR(-ENOMEM); |
| 1149 | |
| 1150 | if (!tegra->domain) { |
| 1151 | /* |
| 1152 | * If IOMMU is disabled, devices address physical memory |
| 1153 | * directly. |
| 1154 | */ |
| 1155 | *dma = virt_to_phys(virt); |
| 1156 | return virt; |
| 1157 | } |
| 1158 | |
| 1159 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1160 | size >> tegra->carveout.shift, |
| 1161 | tegra->carveout.limit, true); |
| 1162 | if (!alloc) { |
| 1163 | err = -EBUSY; |
| 1164 | goto free_pages; |
| 1165 | } |
| 1166 | |
| 1167 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1168 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1169 | size, IOMMU_READ | IOMMU_WRITE); |
| 1170 | if (err < 0) |
| 1171 | goto free_iova; |
| 1172 | |
| 1173 | return virt; |
| 1174 | |
| 1175 | free_iova: |
| 1176 | __free_iova(&tegra->carveout.domain, alloc); |
| 1177 | free_pages: |
| 1178 | free_pages((unsigned long)virt, get_order(size)); |
| 1179 | |
| 1180 | return ERR_PTR(err); |
| 1181 | } |
| 1182 | |
| 1183 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1184 | dma_addr_t dma) |
| 1185 | { |
| 1186 | if (tegra->domain) |
| 1187 | size = iova_align(&tegra->carveout.domain, size); |
| 1188 | else |
| 1189 | size = PAGE_ALIGN(size); |
| 1190 | |
| 1191 | if (tegra->domain) { |
| 1192 | iommu_unmap(tegra->domain, dma, size); |
| 1193 | free_iova(&tegra->carveout.domain, |
| 1194 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1195 | } |
| 1196 | |
| 1197 | free_pages((unsigned long)virt, get_order(size)); |
| 1198 | } |
| 1199 | |
| 1200 | static int host1x_drm_probe(struct host1x_device *dev) |
| 1201 | { |
| 1202 | struct drm_driver *driver = &tegra_drm_driver; |
| 1203 | struct drm_device *drm; |
| 1204 | int err; |
| 1205 | |
| 1206 | drm = drm_dev_alloc(driver, &dev->dev); |
| 1207 | if (IS_ERR(drm)) |
| 1208 | return PTR_ERR(drm); |
| 1209 | |
| 1210 | dev_set_drvdata(&dev->dev, drm); |
| 1211 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1212 | err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false); |
| 1213 | if (err < 0) |
| 1214 | goto put; |
| 1215 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1216 | err = drm_dev_register(drm, 0); |
| 1217 | if (err < 0) |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1218 | goto put; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1219 | |
| 1220 | return 0; |
| 1221 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1222 | put: |
| 1223 | drm_dev_put(drm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1224 | return err; |
| 1225 | } |
| 1226 | |
| 1227 | static int host1x_drm_remove(struct host1x_device *dev) |
| 1228 | { |
| 1229 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1230 | |
| 1231 | drm_dev_unregister(drm); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1232 | drm_dev_put(drm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1233 | |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
| 1237 | #ifdef CONFIG_PM_SLEEP |
| 1238 | static int host1x_drm_suspend(struct device *dev) |
| 1239 | { |
| 1240 | struct drm_device *drm = dev_get_drvdata(dev); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1241 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1242 | return drm_mode_config_helper_suspend(drm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1243 | } |
| 1244 | |
| 1245 | static int host1x_drm_resume(struct device *dev) |
| 1246 | { |
| 1247 | struct drm_device *drm = dev_get_drvdata(dev); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1248 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1249 | return drm_mode_config_helper_resume(drm); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1250 | } |
| 1251 | #endif |
| 1252 | |
| 1253 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1254 | host1x_drm_resume); |
| 1255 | |
| 1256 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1257 | { .compatible = "nvidia,tegra20-dc", }, |
| 1258 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1259 | { .compatible = "nvidia,tegra20-gr2d", }, |
| 1260 | { .compatible = "nvidia,tegra20-gr3d", }, |
| 1261 | { .compatible = "nvidia,tegra30-dc", }, |
| 1262 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1263 | { .compatible = "nvidia,tegra30-gr2d", }, |
| 1264 | { .compatible = "nvidia,tegra30-gr3d", }, |
| 1265 | { .compatible = "nvidia,tegra114-dsi", }, |
| 1266 | { .compatible = "nvidia,tegra114-hdmi", }, |
| 1267 | { .compatible = "nvidia,tegra114-gr3d", }, |
| 1268 | { .compatible = "nvidia,tegra124-dc", }, |
| 1269 | { .compatible = "nvidia,tegra124-sor", }, |
| 1270 | { .compatible = "nvidia,tegra124-hdmi", }, |
| 1271 | { .compatible = "nvidia,tegra124-dsi", }, |
| 1272 | { .compatible = "nvidia,tegra124-vic", }, |
| 1273 | { .compatible = "nvidia,tegra132-dsi", }, |
| 1274 | { .compatible = "nvidia,tegra210-dc", }, |
| 1275 | { .compatible = "nvidia,tegra210-dsi", }, |
| 1276 | { .compatible = "nvidia,tegra210-sor", }, |
| 1277 | { .compatible = "nvidia,tegra210-sor1", }, |
| 1278 | { .compatible = "nvidia,tegra210-vic", }, |
| 1279 | { .compatible = "nvidia,tegra186-display", }, |
| 1280 | { .compatible = "nvidia,tegra186-dc", }, |
| 1281 | { .compatible = "nvidia,tegra186-sor", }, |
| 1282 | { .compatible = "nvidia,tegra186-sor1", }, |
| 1283 | { .compatible = "nvidia,tegra186-vic", }, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1284 | { .compatible = "nvidia,tegra194-display", }, |
| 1285 | { .compatible = "nvidia,tegra194-dc", }, |
| 1286 | { .compatible = "nvidia,tegra194-sor", }, |
| 1287 | { .compatible = "nvidia,tegra194-vic", }, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1288 | { /* sentinel */ } |
| 1289 | }; |
| 1290 | |
| 1291 | static struct host1x_driver host1x_drm_driver = { |
| 1292 | .driver = { |
| 1293 | .name = "drm", |
| 1294 | .pm = &host1x_drm_pm_ops, |
| 1295 | }, |
| 1296 | .probe = host1x_drm_probe, |
| 1297 | .remove = host1x_drm_remove, |
| 1298 | .subdevs = host1x_drm_subdevs, |
| 1299 | }; |
| 1300 | |
| 1301 | static struct platform_driver * const drivers[] = { |
| 1302 | &tegra_display_hub_driver, |
| 1303 | &tegra_dc_driver, |
| 1304 | &tegra_hdmi_driver, |
| 1305 | &tegra_dsi_driver, |
| 1306 | &tegra_dpaux_driver, |
| 1307 | &tegra_sor_driver, |
| 1308 | &tegra_gr2d_driver, |
| 1309 | &tegra_gr3d_driver, |
| 1310 | &tegra_vic_driver, |
| 1311 | }; |
| 1312 | |
| 1313 | static int __init host1x_drm_init(void) |
| 1314 | { |
| 1315 | int err; |
| 1316 | |
| 1317 | err = host1x_driver_register(&host1x_drm_driver); |
| 1318 | if (err < 0) |
| 1319 | return err; |
| 1320 | |
| 1321 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
| 1322 | if (err < 0) |
| 1323 | goto unregister_host1x; |
| 1324 | |
| 1325 | return 0; |
| 1326 | |
| 1327 | unregister_host1x: |
| 1328 | host1x_driver_unregister(&host1x_drm_driver); |
| 1329 | return err; |
| 1330 | } |
| 1331 | module_init(host1x_drm_init); |
| 1332 | |
| 1333 | static void __exit host1x_drm_exit(void) |
| 1334 | { |
| 1335 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
| 1336 | host1x_driver_unregister(&host1x_drm_driver); |
| 1337 | } |
| 1338 | module_exit(host1x_drm_exit); |
| 1339 | |
| 1340 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1341 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1342 | MODULE_LICENSE("GPL v2"); |