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David Brazdil0f672f62019-12-10 10:32:29 +00001# SPDX-License-Identifier: GPL-2.0-only
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00002menuconfig PM_DEVFREQ
3 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
4 select SRCU
5 select PM_OPP
6 help
7 A device may have a list of frequencies and voltages available.
8 devfreq, a generic DVFS framework can be registered for a device
9 in order to let the governor provided to devfreq choose an
10 operating frequency based on the device driver's policy.
11
12 Each device may have its own governor and policy. Devfreq can
13 reevaluate the device state periodically and/or based on the
14 notification to "nb", a notifier block, of devfreq.
15
16 Like some CPUs with CPUfreq, a device may have multiple clocks.
17 However, because the clock frequencies of a single device are
18 determined by the single device's state, an instance of devfreq
19 is attached to a single device and returns a "representative"
20 clock frequency of the device, which is also attached
21 to a device by 1-to-1. The device registering devfreq takes the
22 responsibility to "interpret" the representative frequency and
23 to set its every clock accordingly with the "target" callback
24 given to devfreq.
25
26 When OPP is used with the devfreq device, it is recommended to
27 register devfreq's nb to the OPP's notifier head. If OPP is
28 used with the devfreq device, you may use OPP helper
29 functions defined in devfreq.h.
30
31if PM_DEVFREQ
32
33comment "DEVFREQ Governors"
34
35config DEVFREQ_GOV_SIMPLE_ONDEMAND
36 tristate "Simple Ondemand"
37 help
38 Chooses frequency based on the recent load on the device. Works
39 similar as ONDEMAND governor of CPUFREQ does. A device with
40 Simple-Ondemand should be able to provide busy/total counter
41 values that imply the usage rate. A device may provide tuned
42 values to the governor with data field at devfreq_add_device().
43
44config DEVFREQ_GOV_PERFORMANCE
45 tristate "Performance"
46 help
47 Sets the frequency at the maximum available frequency.
48 This governor always returns UINT_MAX as frequency so that
49 the DEVFREQ framework returns the highest frequency available
50 at any time.
51
52config DEVFREQ_GOV_POWERSAVE
53 tristate "Powersave"
54 help
55 Sets the frequency at the minimum available frequency.
56 This governor always returns 0 as frequency so that
57 the DEVFREQ framework returns the lowest frequency available
58 at any time.
59
60config DEVFREQ_GOV_USERSPACE
61 tristate "Userspace"
62 help
63 Sets the frequency at the user specified one.
64 This governor returns the user configured frequency if there
65 has been an input to /sys/devices/.../power/devfreq_set_freq.
66 Otherwise, the governor does not change the frequency
67 given at the initialization.
68
69config DEVFREQ_GOV_PASSIVE
70 tristate "Passive"
71 help
72 Sets the frequency based on the frequency of its parent devfreq
73 device. This governor does not change the frequency by itself
74 through sysfs entries. The passive governor recommends that
75 devfreq device uses the OPP table to get the frequency/voltage.
76
77comment "DEVFREQ Drivers"
78
79config ARM_EXYNOS_BUS_DEVFREQ
80 tristate "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
81 depends on ARCH_EXYNOS || COMPILE_TEST
82 select DEVFREQ_GOV_SIMPLE_ONDEMAND
83 select DEVFREQ_GOV_PASSIVE
84 select DEVFREQ_EVENT_EXYNOS_PPMU
85 select PM_DEVFREQ_EVENT
86 select PM_OPP
87 help
88 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
89 Memory bus has one more group of memory bus (e.g, MIF and INT block).
90 Each memory bus group could contain many memoby bus block. It reads
91 PPMU counters of memory controllers by using DEVFREQ-event device
92 and adjusts the operating frequencies and voltages with OPP support.
93 This does not yet operate with optimal voltages.
94
95config ARM_TEGRA_DEVFREQ
David Brazdil0f672f62019-12-10 10:32:29 +000096 tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
97 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
98 ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
99 ARCH_TEGRA_210_SOC || \
100 COMPILE_TEST
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000101 select PM_OPP
Olivier Deprez0e641232021-09-23 10:07:05 +0200102 depends on COMMON_CLK
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000103 help
104 This adds the DEVFREQ driver for the Tegra family of SoCs.
105 It reads ACTMON counters of memory controllers and adjusts the
106 operating frequencies and voltages with OPP support.
107
David Brazdil0f672f62019-12-10 10:32:29 +0000108config ARM_TEGRA20_DEVFREQ
109 tristate "NVIDIA Tegra20 DEVFREQ Driver"
110 depends on (TEGRA_MC && TEGRA20_EMC) || COMPILE_TEST
111 depends on COMMON_CLK
112 select DEVFREQ_GOV_SIMPLE_ONDEMAND
113 select PM_OPP
114 help
115 This adds the DEVFREQ driver for the Tegra20 family of SoCs.
116 It reads Memory Controller counters and adjusts the operating
117 frequencies and voltages with OPP support.
118
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000119config ARM_RK3399_DMC_DEVFREQ
120 tristate "ARM RK3399 DMC DEVFREQ Driver"
Olivier Deprez0e641232021-09-23 10:07:05 +0200121 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
122 (COMPILE_TEST && HAVE_ARM_SMCCC)
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000123 select DEVFREQ_EVENT_ROCKCHIP_DFI
124 select DEVFREQ_GOV_SIMPLE_ONDEMAND
125 select PM_DEVFREQ_EVENT
126 select PM_OPP
127 help
128 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
129 It sets the frequency for the memory controller and reads the usage counts
130 from hardware.
131
132source "drivers/devfreq/event/Kconfig"
133
134endif # PM_DEVFREQ